Generated 2026-05-24T15:50:46+03:00. Mode: report. Target frequencies: Lattice ECP5 / Yosys + nextpnr: 100 MHz; Lattice ECP5 / Diamond: 100 MHz; AMD/Xilinx Spartan-7 / Vivado: 150 MHz.
Selection is lowest-latency timing PASS, then lowest area, then highest Fmax. If none pass, the best failing row is shown as FAIL; summary wins and winner highlights require timing PASS and RNE-comparable semantics.
Native WEXP/WMAN; staging autotuned. Semantics differ from IEEE edge-case behavior.
wF excludes the hidden bit. Generation parameters are autotuned; wide hard-multiplier rows may miss timing.
m excludes the hidden bit. Add/mul use RNE; FpxxDiv is table-based, native-rounding, and excluded from wins.
Each target row contains one chart per floating-point format. Latency bars are cycles; area bars are LUT + FF + carry, with DSP and other hard blocks shown in the detail text.
LFE5U-12F CABGA381 speed 6
yosys-nextpnr-ecp5
LFE5U-12F CABGA381 speed 6
diamond-lse-map-par-trce
xc7s50csga324-1
vivado
Device: LFE5U-12F CABGA381 speed 6. Toolchain: yosys-nextpnr-ecp5.
Timing target: 100 MHz.
ECP5 resources use LUT4, TRELLIS_FF, CCU2C carry, MULT18X18D DSP, DP16KD BRAM, and top-level IO bit counts.
| Library | Op | Variant | Entity | Generator target | Gen MHz | Latency | 100 MHz | Fmax MHz | LUT | FF | Carry | DSP | BRAM | IO | Artifacts |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ZKF | add | STAGE_DECODE=1; STAGE_ALIGN=0; STAGE_OUTPUT=0 | zkf_add | 5 | PASS | 113.49 | 821 | 368 | 50 | 0 | 0 | 82 | wrapper ys yosys log pnr log pnr json versions | ||
| FloPoCo | add | FPAdd; dualPath=0; onlyPositiveIO=0; useHardMult=1; plainVHDL=1; useTargetOpt=0 | flopoco_add_we8_wf17_dummyfpga_plain_single_f300 | DummyFPGA | 300 | 5 | PASS | 100.67 | 447 | 304 | 60 | 0 | 0 | 85 | wrapper source ys yosys log pnr log pnr json versions |
| Math Fpxx | add | FpxxAdd; pipeStages=4; stickyBit=1; rounding=even | FpxxAdd | 4 | FAIL | 71.93 | 1049 | 289 | 87 | 0 | 0 | 82 | wrapper source math log ys yosys log pnr log pnr json versions | ||
| ZKF | mul | STAGE_PRODUCT=0; STAGE_OUTPUT=0 | zkf_mul | 1 | PASS | 104.94 | 146 | 114 | 29 | 1 | 0 | 82 | wrapper ys yosys log pnr log pnr json versions | ||
| FloPoCo | mul | FPMult; correctlyRounded=1; dspThreshold=0; useHardMult=1; plainVHDL=1; useTargetOpt=0 | flopoco_mul_we8_wf17_dummyfpga_plain_f300 | DummyFPGA | 300 | 1 | PASS | 111.37 | 84 | 119 | 24 | 1 | 0 | 85 | wrapper source ys yosys log pnr log pnr json versions |
| Math Fpxx | mul | FpxxMul; pipeStages=2; rounding=even | FpxxMul | 2 | PASS | 104.68 | 201 | 167 | 29 | 1 | 0 | 82 | wrapper source math log ys yosys log pnr log pnr json versions | ||
| ZKF | div | STAGE_INPUT=0; STAGE_OUTPUT=0 | zkf_div | 12 | PASS | 133.60 | 1368 | 949 | 368 | 0 | 0 | 83 | wrapper ys yosys log pnr log pnr json versions | ||
| FloPoCo | div | FPDiv; srt=43; useHardMult=1; plainVHDL=0; useTargetOpt=0 | flopoco_div_we8_wf17_zynq7000_native_srt_43_f300 | Zynq7000 | 300 | 16 | PASS | 111.69 | 1208 | 1386 | 224 | 0 | 0 | 85 | wrapper source ys yosys log pnr log pnr json versions |
| Math Fpxx | div | FpxxDiv; pipeStages=3; rounding=native; tableSizeBits=8; lutMantBits=16 | FpxxDiv | 6 | PASS | 101.65 | 191 | 373 | 38 | 3 | 1 | 82 | wrapper source math log ys yosys log pnr log pnr json versions |
| Library | Op | Variant | Entity | Generator target | Gen MHz | Latency | 100 MHz | Fmax MHz | LUT | FF | Carry | DSP | BRAM | IO | Artifacts |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ZKF | add | STAGE_DECODE=0; STAGE_ALIGN=0; STAGE_OUTPUT=1 | zkf_add | 5 | PASS | 101.31 | 1246 | 557 | 77 | 0 | 0 | 136 | wrapper ys yosys log pnr log pnr json versions | ||
| FloPoCo | add | FPAdd; dualPath=0; onlyPositiveIO=0; useHardMult=1; plainVHDL=0; useTargetOpt=0 | flopoco_add_we8_wf35_zynq7000_native_single_f300 | Zynq7000 | 300 | 8 | PASS | 112.18 | 1035 | 707 | 87 | 0 | 0 | 139 | wrapper source ys yosys log pnr log pnr json versions |
| Math Fpxx | add | FpxxAdd; pipeStages=3; stickyBit=1; rounding=even | FpxxAdd | 3 | FAIL | 63.56 | 1506 | 393 | 134 | 0 | 0 | 136 | wrapper source math log ys yosys log pnr log pnr json versions | ||
| ZKF | mul | STAGE_PRODUCT=1; STAGE_OUTPUT=0 | zkf_mul | 2 | PASS | 116.96 | 352 | 308 | 74 | 4 | 0 | 136 | wrapper ys yosys log pnr log pnr json versions | ||
| FloPoCo | mul | FPMult; correctlyRounded=1; dspThreshold=0; useHardMult=1; plainVHDL=0; useTargetOpt=0 | flopoco_mul_we8_wf35_zynq7000_native_f500 | Zynq7000 | 500 | 13 | FAIL | 72.67 | 1414 | 1107 | 107 | 6 | 0 | 139 | wrapper source ys yosys log pnr log pnr json versions |
| Math Fpxx | mul | FpxxMul; pipeStages=2; rounding=even | FpxxMul | 2 | FAIL | 72.83 | 539 | 275 | 110 | 4 | 0 | 136 | wrapper source math log ys yosys log pnr log pnr json versions | ||
| ZKF | div | STAGE_INPUT=0; STAGE_OUTPUT=0 | zkf_div | 21 | PASS | 120.13 | 4625 | 2956 | 1196 | 0 | 0 | 137 | wrapper ys yosys log pnr log pnr json versions | ||
| FloPoCo | div | FPDiv; srt=43; useHardMult=1; plainVHDL=0; useTargetOpt=0 | flopoco_div_we8_wf35_zynq7000_native_srt_43_f500 | Zynq7000 | 500 | 72 | PASS | 137.61 | 4356 | 11344 | 755 | 0 | 0 | 139 | wrapper source ys yosys log pnr log pnr json versions |
| Math Fpxx | div | FpxxDiv; pipeStages=3; rounding=native; tableSizeBits=8; lutMantBits=16 | FpxxDiv | 6 | FAIL | 82.61 | 436 | 574 | 128 | 7 | 1 | 136 | wrapper source math log ys yosys log pnr log pnr json versions |
Device: LFE5U-12F CABGA381 speed 6. Toolchain: diamond-lse-map-par-trce.
Timing target: 100 MHz.
Diamond ECP5 resources use mapper LUT4/register/PIO/BRAM/DSP counts, with CCU2C/PFUMX/L6MUX21 primitive counts taken from the LSE area report when available.
| Library | Op | Variant | Entity | Generator target | Gen MHz | Latency | 100 MHz | Fmax MHz | LUT | FF | Carry | DSP | BRAM | IO | Artifacts |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ZKF | add | STAGE_DECODE=0; STAGE_ALIGN=0; STAGE_OUTPUT=0 | zkf_add | 4 | PASS | 110.44 | 585 | 294 | 68 | 0 | 0 | 82 | wrapper lse prj lse stdout lse log lse area map rpt par log trce rpt versions | ||
| FloPoCo | add | FPAdd; dualPath=0; onlyPositiveIO=0; useHardMult=1; plainVHDL=0; useTargetOpt=0 | flopoco_add_we8_wf17_zynq7000_native_single_f200 | Zynq7000 | 200 | 4 | PASS | 102.40 | 399 | 272 | 51 | 0 | 1 | 85 | wrapper source lse prj lse stdout lse log lse area map rpt par log trce rpt versions |
| Math Fpxx | add | FpxxAdd; pipeStages=5; stickyBit=1; rounding=even | FpxxAdd | 5 | FAIL | 79.30 | 655 | 287 | 69 | 0 | 0 | 82 | wrapper source math log lse prj lse stdout lse log lse area map rpt par log trce rpt versions | ||
| ZKF | mul | STAGE_PRODUCT=0; STAGE_OUTPUT=0 | zkf_mul | 1 | PASS | 102.45 | 137 | 94 | 30 | 1 | 0 | 82 | wrapper lse prj lse stdout lse log lse area map rpt par log trce rpt versions | ||
| FloPoCo | mul | FPMult; correctlyRounded=1; dspThreshold=0; useHardMult=1; plainVHDL=1; useTargetOpt=0 | flopoco_mul_we8_wf17_dummyfpga_plain_f300 | DummyFPGA | 300 | 1 | PASS | 115.41 | 89 | 115 | 25 | 1 | 0 | 85 | wrapper source lse prj lse stdout lse log lse area map rpt par log trce rpt versions |
| Math Fpxx | mul | FpxxMul; pipeStages=2; rounding=even | FpxxMul | 2 | FAIL | 80.15 | 166 | 143 | 21 | 1 | 0 | 82 | wrapper source math log lse prj lse stdout lse log lse area map rpt par log trce rpt versions | ||
| ZKF | div | STAGE_INPUT=0; STAGE_OUTPUT=0 | zkf_div | 12 | PASS | 131.06 | 1265 | 961 | 382 | 0 | 0 | 83 | wrapper lse prj lse stdout lse log lse area map rpt par log trce rpt versions | ||
| FloPoCo | div | FPDiv; srt=87; useHardMult=1; plainVHDL=0; useTargetOpt=0 | flopoco_div_we8_wf17_zynq7000_native_srt_87_f300 | Zynq7000 | 300 | 15 | PASS | 115.06 | 1122 | 975 | 241 | 0 | 1 | 85 | wrapper source lse prj lse stdout lse log lse area map rpt par log trce rpt versions |
| Math Fpxx | div | FpxxDiv; pipeStages=2; rounding=native; tableSizeBits=6; lutMantBits=12 | FpxxDiv | 5 | PASS | 118.69 | 172 | 295 | 26 | 3 | 1 | 82 | wrapper source math log lse prj lse stdout lse log lse area map rpt par log trce rpt versions |
| Library | Op | Variant | Entity | Generator target | Gen MHz | Latency | 100 MHz | Fmax MHz | LUT | FF | Carry | DSP | BRAM | IO | Artifacts |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ZKF | add | STAGE_DECODE=0; STAGE_ALIGN=0; STAGE_OUTPUT=0 | zkf_add | 4 | PASS | 108.97 | 1010 | 477 | 110 | 0 | 0 | 136 | wrapper lse prj lse stdout lse log lse area map rpt par log trce rpt versions | ||
| FloPoCo | add | FPAdd; dualPath=0; onlyPositiveIO=0; useHardMult=1; plainVHDL=1; useTargetOpt=0 | flopoco_add_we8_wf35_dummyfpga_plain_single_f300 | DummyFPGA | 300 | 5 | PASS | 101.80 | 754 | 478 | 79 | 0 | 1 | 139 | wrapper source lse prj lse stdout lse log lse area map rpt par log trce rpt versions |
| Math Fpxx | add | FpxxAdd; pipeStages=5; stickyBit=1; rounding=even | FpxxAdd | 5 | FAIL | 72.22 | 1208 | 486 | 113 | 0 | 0 | 136 | wrapper source math log lse prj lse stdout lse log lse area map rpt par log trce rpt versions | ||
| ZKF | mul | STAGE_PRODUCT=0; STAGE_OUTPUT=0 | zkf_mul | 1 | PASS | 102.51 | 177 | 148 | 45 | 4 | 0 | 136 | wrapper lse prj lse stdout lse log lse area map rpt par log trce rpt versions | ||
| FloPoCo | mul | FPMult; correctlyRounded=1; dspThreshold=0; useHardMult=1; plainVHDL=1; useTargetOpt=0 | flopoco_mul_we8_wf35_dummyfpga_plain_f300 | DummyFPGA | 300 | 1 | FAIL | 78.03 | 130 | 187 | 34 | 4 | 0 | 139 | wrapper source lse prj lse stdout lse log lse area map rpt par log trce rpt versions |
| Math Fpxx | mul | FpxxMul; pipeStages=2; rounding=even | FpxxMul | 2 | FAIL | 71.74 | 259 | 233 | 30 | 4 | 0 | 136 | wrapper source math log lse prj lse stdout lse log lse area map rpt par log trce rpt versions | ||
| ZKF | div | STAGE_INPUT=0; STAGE_OUTPUT=0 | zkf_div | 21 | PASS | 108.50 | 4142 | 2977 | 1219 | 0 | 0 | 137 | wrapper lse prj lse stdout lse log lse area map rpt par log trce rpt versions | ||
| FloPoCo | div | FPDiv; srt=87; useHardMult=1; plainVHDL=0; useTargetOpt=0 | flopoco_div_we8_wf35_zynq7000_native_srt_87_f300 | Zynq7000 | 300 | 33 | PASS | 102.58 | 3434 | 3637 | 716 | 0 | 6 | 139 | wrapper source lse prj lse stdout lse log lse area map rpt par log trce rpt versions |
| Math Fpxx | div | FpxxDiv; pipeStages=2; rounding=native; tableSizeBits=6; lutMantBits=12 | FpxxDiv | 5 | FAIL | 90.49 | 310 | 443 | 66 | 7 | 1 | 136 | wrapper source math log lse prj lse stdout lse log lse area map rpt par log trce rpt versions |
Device: xc7s50csga324-1. Toolchain: vivado.
Timing target: 150 MHz.
Spartan-7 resources use LUT primitives, FD* flip-flops, CARRY4 carry, DSP48* DSP, RAMB* BRAM, and top-level IO bit counts.
| Library | Op | Variant | Entity | Generator target | Gen MHz | Latency | 150 MHz | Fmax MHz | LUT | FF | Carry | DSP | BRAM | IO | Artifacts |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ZKF | add | STAGE_DECODE=0; STAGE_ALIGN=0; STAGE_OUTPUT=0 | zkf_add | 4 | PASS | 171.51 | 382 | 274 | 25 | 0 | 0 | 82 | wrapper tcl vivado log util timing metrics versions | ||
| FloPoCo | add | FPAdd; dualPath=0; onlyPositiveIO=0; useHardMult=1; plainVHDL=0; useTargetOpt=0 | flopoco_add_we8_wf17_zynq7000_native_single_f200 | Zynq7000 | 200 | 4 | PASS | 150.34 | 304 | 249 | 22 | 0 | 0 | 85 | wrapper source tcl vivado log util timing metrics versions |
| Math Fpxx | add | FpxxAdd; pipeStages=5; stickyBit=1; rounding=even | FpxxAdd | 5 | FAIL | 143.23 | 442 | 280 | 32 | 0 | 0 | 82 | wrapper source math log tcl vivado log util timing metrics versions | ||
| ZKF | mul | STAGE_PRODUCT=0; STAGE_OUTPUT=0 | zkf_mul | 1 | PASS | 173.62 | 100 | 94 | 10 | 1 | 0 | 82 | wrapper tcl vivado log util timing metrics versions | ||
| FloPoCo | mul | FPMult; correctlyRounded=1; dspThreshold=0; useHardMult=1; plainVHDL=1; useTargetOpt=0 | flopoco_mul_we8_wf17_dummyfpga_plain_f300 | DummyFPGA | 300 | 1 | PASS | 150.29 | 46 | 115 | 10 | 1 | 0 | 85 | wrapper source tcl vivado log util timing metrics versions |
| Math Fpxx | mul | FpxxMul; pipeStages=2; rounding=even | FpxxMul | 2 | PASS | 158.56 | 123 | 169 | 13 | 1 | 0 | 82 | wrapper source math log tcl vivado log util timing metrics versions | ||
| ZKF | div | STAGE_INPUT=0; STAGE_OUTPUT=0 | zkf_div | 12 | PASS | 184.45 | 1069 | 738 | 173 | 0 | 0 | 83 | wrapper tcl vivado log util timing metrics versions | ||
| FloPoCo | div | FPDiv; srt=87; useHardMult=1; plainVHDL=0; useTargetOpt=0 | flopoco_div_we8_wf17_zynq7000_native_srt_87_f300 | Zynq7000 | 300 | 15 | PASS | 161.69 | 671 | 885 | 109 | 0 | 0 | 85 | wrapper source tcl vivado log util timing metrics versions |
| Math Fpxx | div | FpxxDiv; pipeStages=2; rounding=native; tableSizeBits=9; lutMantBits=20 | FpxxDiv | 5 | PASS | 174.04 | 137 | 192 | 11 | 3 | 1 | 82 | wrapper source math log tcl vivado log util timing metrics versions |
| Library | Op | Variant | Entity | Generator target | Gen MHz | Latency | 150 MHz | Fmax MHz | LUT | FF | Carry | DSP | BRAM | IO | Artifacts |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ZKF | add | STAGE_DECODE=0; STAGE_ALIGN=0; STAGE_OUTPUT=0 | zkf_add | 4 | PASS | 162.08 | 660 | 455 | 37 | 0 | 0 | 136 | wrapper tcl vivado log util timing metrics versions | ||
| FloPoCo | add | FPAdd; dualPath=1; onlyPositiveIO=0; useHardMult=1; plainVHDL=0; useTargetOpt=0 | flopoco_add_we8_wf35_zynq7000_native_dual_f300 | Zynq7000 | 300 | 5 | PASS | 150.93 | 756 | 733 | 52 | 0 | 0 | 139 | wrapper source tcl vivado log util timing metrics versions |
| Math Fpxx | add | FpxxAdd; pipeStages=5; stickyBit=1; rounding=even | FpxxAdd | 5 | FAIL | 121.97 | 818 | 474 | 50 | 0 | 0 | 136 | wrapper source math log tcl vivado log util timing metrics versions | ||
| ZKF | mul | STAGE_PRODUCT=1; STAGE_OUTPUT=0 | zkf_mul | 2 | PASS | 163.03 | 233 | 234 | 28 | 4 | 0 | 136 | wrapper tcl vivado log util timing metrics versions | ||
| FloPoCo | mul | FPMult; correctlyRounded=1; dspThreshold=0; useHardMult=1; plainVHDL=0; useTargetOpt=0 | flopoco_mul_we8_wf35_kintex7_native_f300 | Kintex7 | 300 | 3 | PASS | 152.05 | 563 | 431 | 30 | 6 | 0 | 139 | wrapper source tcl vivado log util timing metrics versions |
| Math Fpxx | mul | FpxxMul; pipeStages=2; rounding=even | FpxxMul | 2 | FAIL | 98.61 | 290 | 330 | 40 | 4 | 0 | 136 | wrapper source math log tcl vivado log util timing metrics versions | ||
| ZKF | div | STAGE_INPUT=0; STAGE_OUTPUT=0 | zkf_div | 21 | PASS | 162.14 | 3702 | 2376 | 608 | 0 | 0 | 137 | wrapper tcl vivado log util timing metrics versions | ||
| FloPoCo | div | FPDiv; srt=42; useHardMult=1; plainVHDL=1; useTargetOpt=0 | flopoco_div_we8_wf35_dummyfpga_plain_srt_42_f700 | DummyFPGA | 700 | 33 | PASS | 157.56 | 1687 | 3152 | 225 | 0 | 6 | 139 | wrapper source tcl vivado log util timing metrics versions |
| Math Fpxx | div | FpxxDiv; pipeStages=3; rounding=native; tableSizeBits=10; lutMantBits=20 | FpxxDiv | 6 | PASS | 153.78 | 300 | 373 | 42 | 7 | 1 | 136 | wrapper source math log tcl vivado log util timing metrics versions |