****** Vivado v2025.2.1 (64-bit) **** SW Build 6403652 on Thu Mar 19 13:47:00 MDT 2026 **** IP Build 6403511 on Thu Mar 19 12:41:45 MDT 2026 **** SharedData Build 6403650 on Thu Mar 19 14:02:13 MDT 2026 **** Start of session at: Sun May 24 14:58:24 2026 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved. source /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_add_e8_m35_round_even_sticky_p5/vivado.tcl -notrace read_xdc: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1583.117 ; gain = 8.027 ; free physical = 10301 ; free virtual = 21034 Command: synth_design -top top_tommath_add_e8_m35_round_even_sticky_p5 -part xc7s50csga324-1 -mode out_of_context -flatten_hierarchy rebuilt Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7s50' INFO: [Device 21-403] Loading part xc7s50csga324-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 1 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 361336 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2193.555 ; gain = 483.156 ; free physical = 9456 ; free virtual = 20188 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'top_tommath_add_e8_m35_round_even_sticky_p5' [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_add_e8_m35_round_even_sticky_p5/src/top_tommath_add_e8_m35_round_even_sticky_p5.v:3] INFO: [Synth 8-6157] synthesizing module 'FpxxAdd' [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_add_e8_m35_round_even_sticky_p5/src/tommath_add_e8_m35_round_even_sticky_p5.v:7] INFO: [Synth 8-6155] done synthesizing module 'FpxxAdd' (0#1) [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_add_e8_m35_round_even_sticky_p5/src/tommath_add_e8_m35_round_even_sticky_p5.v:7] INFO: [Synth 8-6155] done synthesizing module 'top_tommath_add_e8_m35_round_even_sticky_p5' (0#1) [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_add_e8_m35_round_even_sticky_p5/src/top_tommath_add_e8_m35_round_even_sticky_p5.v:3] WARNING: [Synth 8-3936] Found unconnected internal register '_zz_n4__lz_reg' and it is trimmed from '7' to '6' bits. [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_add_e8_m35_round_even_sticky_p5/src/tommath_add_e8_m35_round_even_sticky_p5.v:560] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2284.523 ; gain = 574.125 ; free physical = 9174 ; free virtual = 19908 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2299.367 ; gain = 588.969 ; free physical = 9162 ; free virtual = 19896 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2299.367 ; gain = 588.969 ; free physical = 9162 ; free virtual = 19896 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2299.367 ; gain = 0.000 ; free physical = 9162 ; free virtual = 19896 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_add_e8_m35_round_even_sticky_p5/constraints.xdc] Finished Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_add_e8_m35_round_even_sticky_p5/constraints.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2380.086 ; gain = 0.000 ; free physical = 9132 ; free virtual = 19866 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2380.121 ; gain = 0.000 ; free physical = 9132 ; free virtual = 19866 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2380.121 ; gain = 669.723 ; free physical = 9177 ; free virtual = 19915 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7s50csga324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2388.090 ; gain = 677.691 ; free physical = 9177 ; free virtual = 19915 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2388.090 ; gain = 677.691 ; free physical = 9178 ; free virtual = 19916 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2388.090 ; gain = 677.691 ; free physical = 9186 ; free virtual = 19925 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 41 Bit Adders := 1 2 Input 38 Bit Adders := 1 2 Input 37 Bit Adders := 1 2 Input 36 Bit Adders := 1 3 Input 9 Bit Adders := 1 4 Input 9 Bit Adders := 1 3 Input 8 Bit Adders := 1 2 Input 8 Bit Adders := 1 2 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 1 +---Registers : 44 Bit Registers := 3 41 Bit Registers := 2 40 Bit Registers := 3 39 Bit Registers := 1 36 Bit Registers := 2 8 Bit Registers := 5 6 Bit Registers := 2 1 Bit Registers := 29 +---Muxes : 2 Input 41 Bit Muxes := 4 2 Input 39 Bit Muxes := 1 2 Input 37 Bit Muxes := 1 2 Input 36 Bit Muxes := 2 2 Input 35 Bit Muxes := 3 2 Input 8 Bit Muxes := 4 2 Input 6 Bit Muxes := 6 2 Input 5 Bit Muxes := 4 2 Input 4 Bit Muxes := 10 2 Input 3 Bit Muxes := 20 2 Input 2 Bit Muxes := 38 2 Input 1 Bit Muxes := 7 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 120 (col length:60) BRAMs: 150 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2388.090 ; gain = 677.691 ; free physical = 9234 ; free virtual = 19973 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2433.090 ; gain = 722.691 ; free physical = 9411 ; free virtual = 20147 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 2488.137 ; gain = 777.738 ; free physical = 9348 ; free virtual = 20132 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 2496.145 ; gain = 785.746 ; free physical = 9333 ; free virtual = 20116 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2633.957 ; gain = 923.559 ; free physical = 9226 ; free virtual = 20014 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2633.957 ; gain = 923.559 ; free physical = 9226 ; free virtual = 20014 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2633.957 ; gain = 923.559 ; free physical = 9226 ; free virtual = 20014 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2633.957 ; gain = 923.559 ; free physical = 9226 ; free virtual = 20014 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2633.957 ; gain = 923.559 ; free physical = 9226 ; free virtual = 20014 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2633.957 ; gain = 923.559 ; free physical = 9226 ; free virtual = 20014 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |FpxxAdd | n4_n0_is_zero_reg | 4 | 1 | NO | NO | YES | 1 | 0 | |FpxxAdd | n4_n0_exp_add_reg[7] | 4 | 8 | NO | NO | YES | 8 | 0 | |FpxxAdd | n5_n0_is_inf_reg | 5 | 1 | NO | NO | YES | 1 | 0 | |FpxxAdd | n5_n0_is_nan_reg | 5 | 1 | NO | NO | YES | 1 | 0 | |FpxxAdd | n5_n2_sign_add_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +------------+----------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |CARRY4 | 50| |2 |LUT1 | 1| |3 |LUT2 | 76| |4 |LUT3 | 130| |5 |LUT4 | 172| |6 |LUT5 | 146| |7 |LUT6 | 293| |8 |SRL16E | 12| |9 |FDCE | 5| |10 |FDRE | 469| +------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2633.957 ; gain = 923.559 ; free physical = 9226 ; free virtual = 20014 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2633.957 ; gain = 842.805 ; free physical = 9230 ; free virtual = 20018 Synthesis Optimization Complete : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2633.965 ; gain = 923.559 ; free physical = 9230 ; free virtual = 20018 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2633.965 ; gain = 0.000 ; free physical = 9230 ; free virtual = 20018 INFO: [Netlist 29-17] Analyzing 50 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top_tommath_add_e8_m35_round_even_sticky_p5' is not ideal for floorplanning, since the cellview 'FpxxAdd' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_add_e8_m35_round_even_sticky_p5/constraints.xdc] Finished Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_add_e8_m35_round_even_sticky_p5/constraints.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2633.965 ; gain = 0.000 ; free physical = 9401 ; free virtual = 20189 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Synth Design complete | Checksum: 61e4603c INFO: [Common 17-83] Releasing license: Synthesis 18 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:38 ; elapsed = 00:00:36 . Memory (MB): peak = 2633.992 ; gain = 1050.875 ; free physical = 9401 ; free virtual = 20189 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2267.795; main = 2117.698; forked = 359.652 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3607.184; main = 2633.961; forked = 1018.035 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7s50' Running DRC as a precondition to command opt_design Starting DRC Task WARNING: [DRC 23-814] Not all possible (connectivity based) DRCs may have been run because this design is seen as Out of Context. INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2633.992 ; gain = 0.000 ; free physical = 9372 ; free virtual = 20161 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 15a803efa Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2633.992 ; gain = 0.000 ; free physical = 9272 ; free virtual = 20062 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 15a803efa Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2665.957 ; gain = 0.000 ; free physical = 9259 ; free virtual = 20050 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 15a803efa Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2665.957 ; gain = 0.000 ; free physical = 9259 ; free virtual = 20050 Phase 1 Initialization | Checksum: 15a803efa Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2665.957 ; gain = 0.000 ; free physical = 9259 ; free virtual = 20050 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Detect if minReqCache needed Phase 2.1 Detect if minReqCache needed | Checksum: 15a803efa Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2665.957 ; gain = 0.000 ; free physical = 9260 ; free virtual = 20051 Phase 2.2 Timer Update Phase 2.2 Timer Update | Checksum: 15a803efa Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2665.957 ; gain = 0.000 ; free physical = 9260 ; free virtual = 20051 Phase 2 Timer Update And Timing Data Collection | Checksum: 15a803efa Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2665.957 ; gain = 0.000 ; free physical = 9260 ; free virtual = 20051 Phase 3 Retarget INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 15a803efa Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2665.957 ; gain = 0.000 ; free physical = 9260 ; free virtual = 20051 Retarget | Checksum: 15a803efa INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 15a803efa Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2665.957 ; gain = 0.000 ; free physical = 9260 ; free virtual = 20051 Constant propagation | Checksum: 15a803efa INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2665.957 ; gain = 0.000 ; free physical = 9260 ; free virtual = 20051 Phase 5 Sweep | Checksum: 1513e0298 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2665.957 ; gain = 0.000 ; free physical = 9260 ; free virtual = 20051 Sweep | Checksum: 1513e0298 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Sweep, 268 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 1513e0298 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2697.973 ; gain = 32.016 ; free physical = 9260 ; free virtual = 20051 BUFG optimization | Checksum: 1513e0298 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 1513e0298 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2697.973 ; gain = 32.016 ; free physical = 9260 ; free virtual = 20051 Shift Register Optimization | Checksum: 1513e0298 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 1513e0298 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2697.973 ; gain = 32.016 ; free physical = 9260 ; free virtual = 20051 Post Processing Netlist | Checksum: 1513e0298 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1562262d3 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2697.973 ; gain = 32.016 ; free physical = 9260 ; free virtual = 20051 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9260 ; free virtual = 20051 Phase 9.2 Verifying Netlist Connectivity | Checksum: 1562262d3 Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2697.973 ; gain = 32.016 ; free physical = 9260 ; free virtual = 20051 Phase 9 Finalization | Checksum: 1562262d3 Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2697.973 ; gain = 32.016 ; free physical = 9260 ; free virtual = 20051 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 0 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 0 | 268 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 1562262d3 Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2697.973 ; gain = 32.016 ; free physical = 9260 ; free virtual = 20051 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 1562262d3 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9259 ; free virtual = 20050 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 1562262d3 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9259 ; free virtual = 20050 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9259 ; free virtual = 20050 INFO: [Common 17-83] Releasing license: Implementation 40 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2697.973 ; gain = 63.980 ; free physical = 9259 ; free virtual = 20050 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-83] Releasing license: Implementation WARNING: [DRC 23-814] Not all possible (connectivity based) DRCs may have been run because this design is seen as Out of Context. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Timing 38-35] Done setting XDC timing constraints. Running DRC as a precondition to command place_design WARNING: [DRC 23-814] Not all possible (connectivity based) DRCs may have been run because this design is seen as Out of Context. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9268 ; free virtual = 20059 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 10fa769af Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9268 ; free virtual = 20059 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9268 ; free virtual = 20059 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 156e294d6 Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9267 ; free virtual = 20058 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 19079003b Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9267 ; free virtual = 20058 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 19079003b Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.52 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9267 ; free virtual = 20058 Phase 1 Placer Initialization | Checksum: 19079003b Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.52 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9267 ; free virtual = 20058 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1f98ff662 Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.69 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9268 ; free virtual = 20059 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1d1085295 Time (s): cpu = 00:00:00.81 ; elapsed = 00:00:00.84 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9286 ; free virtual = 20077 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 1f70b7328 Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.84 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9286 ; free virtual = 20077 Phase 2.4 Global Place Phase1 Phase 2.4 Global Place Phase1 | Checksum: 1c5d766fb Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9313 ; free virtual = 20104 Phase 2.5 Global Place Phase2 Phase 2.5.1 UpdateTiming Before Physical Synthesis Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 18f3a70d3 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9313 ; free virtual = 20104 Phase 2.5.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 2 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 1 net or LUT. Breaked 0 LUT, combined 1 existing LUT and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization. INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9313 ; free virtual = 20104 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 1 | 1 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 1 | 1 | 0 | 9 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.5.2 Physical Synthesis In Placer | Checksum: 218706fff Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9313 ; free virtual = 20104 Phase 2.5 Global Place Phase2 | Checksum: 18927bfd3 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9306 ; free virtual = 20097 Phase 2 Global Placement | Checksum: 18927bfd3 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9306 ; free virtual = 20097 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 21fd36d0a Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9310 ; free virtual = 20101 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1aa31e4e8 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9310 ; free virtual = 20101 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 105bcc9f3 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9310 ; free virtual = 20101 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 174626c65 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9310 ; free virtual = 20101 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 141e8a35c Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9276 ; free virtual = 20067 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 2a7c25efe Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9253 ; free virtual = 20045 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 2a65e4199 Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9240 ; free virtual = 20032 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 230012027 Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9239 ; free virtual = 20031 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 1dfa3795c Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9272 ; free virtual = 20066 Phase 3 Detail Placement | Checksum: 1dfa3795c Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9272 ; free virtual = 20066 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 230df61c1 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.083 | TNS=-39.395 | Phase 1 Physical Synthesis Initialization | Checksum: 19b0bf76a Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9267 ; free virtual = 20061 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 17a106e40 Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9267 ; free virtual = 20061 Phase 4.1.1.1 BUFG Insertion | Checksum: 230df61c1 Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9267 ; free virtual = 20061 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.951. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 2ed7fee8b Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9004 ; free virtual = 19914 Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9004 ; free virtual = 19914 Phase 4.1 Post Commit Optimization | Checksum: 2ed7fee8b Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9004 ; free virtual = 19914 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 2ed7fee8b Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9004 ; free virtual = 19915 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 2x2| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 2ed7fee8b Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9004 ; free virtual = 19915 Phase 4.3 Placer Reporting | Checksum: 2ed7fee8b Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9004 ; free virtual = 19915 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9004 ; free virtual = 19915 Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9004 ; free virtual = 19915 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2a431c1ad Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9004 ; free virtual = 19915 Ending Placer Task | Checksum: 1ab21c2f3 Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9004 ; free virtual = 19915 74 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 9004 ; free virtual = 19915 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7s50' Starting Routing Task Phase 1 Build RT Design Checksum: PlaceDB: f297aafa ConstDB: 0 ShapeSum: df8e4c3 RouteDB: aa913336 WARNING: [Route 35-197] Clock port "clk" does not have an associated HD.CLK_SRC. Without this constraint, timing analysis may not be accurate and upstream checks cannot be done to ensure correct clock placement. WARNING: [Route 35-198] Port "b_i[41]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[41]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[40]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[40]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[39]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[39]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[40]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[40]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[39]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[39]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[42]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[42]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[36]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[36]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[35]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[35]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[35]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[35]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[42]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[42]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[41]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[41]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[38]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[38]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[37]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[37]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[38]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[38]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[36]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[36]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[37]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[37]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[32]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[32]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[32]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[32]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[34]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[34]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[33]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[33]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[29]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[29]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[28]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[28]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[27]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[27]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[27]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[27]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[29]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[29]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[31]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[31]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[30]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[30]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[31]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[31]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[24]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[24]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[30]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[30]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[28]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[28]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[26]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[26]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[24]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[24]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[34]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[34]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[33]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[33]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[43]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[43]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[43]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[43]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[19]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[19]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[18]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[18]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[19]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[19]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[18]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[18]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[23]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[23]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[20]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[20]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[23]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[23]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[22]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[22]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[21]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[21]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[20]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[20]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[21]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[21]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[17]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[17]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[17]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[17]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[26]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[26]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[25]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[25]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[22]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[22]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[25]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[25]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[16]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[16]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[16]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[16]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[5]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[5]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[13]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[13]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[5]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[5]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[15]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[15]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[14]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[14]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[13]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[13]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[12]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[12]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[3]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[3]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[7]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[7]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[6]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[6]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[6]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[6]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[15]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[15]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[14]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[14]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[12]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[12]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[3]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[3]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[7]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[7]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[11]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[11]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[9]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[9]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[8]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[8]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[9]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[9]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[11]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[11]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[8]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[8]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "rst" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "rst". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "in_valid_i" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "in_valid_i". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Constraints 18-8777] Unable to split tiles. All required files are not available. Post Restoration Checksum: NetGraph: e7573066 | NumContArr: 839bbf79 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 2f044e519 Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 8782 ; free virtual = 19855 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 2f044e519 Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 8778 ; free virtual = 19850 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 2f044e519 Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 8778 ; free virtual = 19850 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 21fd39343 Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2697.973 ; gain = 0.000 ; free physical = 8701 ; free virtual = 19773 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.713 | TNS=-24.890| WHS=0.134 | THS=0.000 | Phase 2.4 Soft Constraint Pins - Fast Budgeting Phase 2.4 Soft Constraint Pins - Fast Budgeting | Checksum: 22d7248d1 Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8684 ; free virtual = 19756 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 940 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 940 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 2 Router Initialization | Checksum: 22d7248d1 Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8681 ; free virtual = 19753 Phase 3 Global Routing Phase 3 Global Routing | Checksum: 22d7248d1 Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8681 ; free virtual = 19753 Phase 4 Initial Routing Phase 4.1 Initial Net Routing Pass Phase 4.1 Initial Net Routing Pass | Checksum: 16fbb5f03 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8665 ; free virtual = 19738 Phase 4 Initial Routing | Checksum: 16fbb5f03 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8665 ; free virtual = 19738 Phase 5 Rip-up And Reroute Phase 5.1 Global Iteration 0 Number of Nodes with overlaps = 444 Number of Nodes with overlaps = 219 Number of Nodes with overlaps = 169 Number of Nodes with overlaps = 84 Number of Nodes with overlaps = 38 Number of Nodes with overlaps = 25 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.728 | TNS=-65.904| WHS=N/A | THS=N/A | Phase 5.1 Global Iteration 0 | Checksum: 22c273666 Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8464 ; free virtual = 19547 Phase 5.2 Global Iteration 1 Number of Nodes with overlaps = 194 Number of Nodes with overlaps = 116 Number of Nodes with overlaps = 64 Number of Nodes with overlaps = 50 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.705 | TNS=-64.688| WHS=N/A | THS=N/A | Phase 5.2 Global Iteration 1 | Checksum: 21b99e9d8 Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8453 ; free virtual = 19550 Phase 5.3 Global Iteration 2 Number of Nodes with overlaps = 132 Number of Nodes with overlaps = 122 Number of Nodes with overlaps = 58 Number of Nodes with overlaps = 34 Number of Nodes with overlaps = 35 Number of Nodes with overlaps = 20 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.553 | TNS=-58.152| WHS=N/A | THS=N/A | Phase 5.3 Global Iteration 2 | Checksum: 2cd04854e Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8343 ; free virtual = 19440 Phase 5.4 Global Iteration 3 Number of Nodes with overlaps = 181 Number of Nodes with overlaps = 92 Number of Nodes with overlaps = 66 Number of Nodes with overlaps = 22 Number of Nodes with overlaps = 18 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.812 | TNS=-69.289| WHS=N/A | THS=N/A | Phase 5.4 Global Iteration 3 | Checksum: 29e36abed Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8276 ; free virtual = 19364 Phase 5 Rip-up And Reroute | Checksum: 29e36abed Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8276 ; free virtual = 19364 Phase 6 Delay and Skew Optimization Phase 6.1 Delay CleanUp Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 29e36abed Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8306 ; free virtual = 19395 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.553 | TNS=-58.152| WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 6.1 Delay CleanUp | Checksum: 26f198fee Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8307 ; free virtual = 19395 Phase 6.2 Clock Skew Optimization Phase 6.2 Clock Skew Optimization | Checksum: 26f198fee Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8307 ; free virtual = 19395 Phase 6 Delay and Skew Optimization | Checksum: 26f198fee Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8307 ; free virtual = 19395 Phase 7 Post Hold Fix Phase 7.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.536 | TNS=-57.421| WHS=0.130 | THS=0.000 | Phase 7.1 Hold Fix Iter | Checksum: 2927a4b99 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8306 ; free virtual = 19395 Phase 7 Post Hold Fix | Checksum: 2927a4b99 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8306 ; free virtual = 19395 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.276569 % Global Horizontal Routing Utilization = 0.282405 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --GLOBAL Congestion: Utilization threshold used for congestion level computation: 0.85 Congestion Report North Dir 1x1 Area, Max Cong = 35.1351%, No Congested Regions. South Dir 1x1 Area, Max Cong = 49.5495%, No Congested Regions. East Dir 1x1 Area, Max Cong = 30.8824%, No Congested Regions. West Dir 1x1 Area, Max Cong = 36.7647%, No Congested Regions. ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Phase 8 Route finalize | Checksum: 2927a4b99 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8306 ; free virtual = 19394 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 2927a4b99 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8306 ; free virtual = 19394 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 28b22eff3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8307 ; free virtual = 19395 Phase 11 Post Process Routing Phase 11 Post Process Routing | Checksum: 28b22eff3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8307 ; free virtual = 19395 Phase 12 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=-1.536 | TNS=-57.421| WHS=0.130 | THS=0.000 | WARNING: [Route 35-328] Router estimated timing not met. Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. Phase 12 Post Router Timing | Checksum: 28b22eff3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8307 ; free virtual = 19395 Total Elapsed time in route_design: 41.45 secs Phase 13 Post-Route Event Processing Phase 13 Post-Route Event Processing | Checksum: 1363800a2 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8307 ; free virtual = 19396 INFO: [Route 35-16] Router Completed Successfully Ending Routing Task | Checksum: 1363800a2 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8307 ; free virtual = 19395 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 85 Infos, 98 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2713.973 ; gain = 16.000 ; free physical = 8306 ; free virtual = 19394 INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {REF_NAME =~ DSP*}'. WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {REF_NAME =~ RAMB*}'. INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2713.973 ; gain = 0.000 ; free physical = 8322 ; free virtual = 19412 Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2713.973 ; gain = 0.000 ; free physical = 8322 ; free virtual = 19412 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2713.973 ; gain = 0.000 ; free physical = 8322 ; free virtual = 19412 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2713.973 ; gain = 0.000 ; free physical = 8322 ; free virtual = 19412 Wrote PlaceStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2713.973 ; gain = 0.000 ; free physical = 8322 ; free virtual = 19413 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2713.973 ; gain = 0.000 ; free physical = 8322 ; free virtual = 19413 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2713.973 ; gain = 0.000 ; free physical = 8322 ; free virtual = 19413 Write Physdb Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2713.973 ; gain = 0.000 ; free physical = 8322 ; free virtual = 19413 INFO: [Common 17-1381] The checkpoint '/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_add_e8_m35_round_even_sticky_p5/post_route.dcp' has been generated. INFO: [Common 17-206] Exiting Vivado at Sun May 24 15:00:24 2026... $ /mnt/storage/xilinx/2025.2.1/Vivado/bin/vivado -mode batch -nojournal -nolog -notrace -source /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_add_e8_m35_round_even_sticky_p5/vivado.tcl [exit code 0]