Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2025.2.1 (lin64) Build 6403652 Thu Mar 19 13:47:00 MDT 2026
| Date         : Sat May 23 22:41:59 2026
| Host         : deep-thought running 64-bit Manjaro Linux
| Command      : report_timing_summary -file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/zkf_add_w8_m18_base/timing_summary.rpt -max_paths 10 -nworst 10
| Design       : top_zkf_add_w8_m18_base
| Device       : 7s50-csga324
| Speed File   : -1  PRODUCTION 1.23 2018-06-13
| Design State : Routed
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (54)
6. checking no_output_delay (27)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (54)
-------------------------------
 There are 54 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (27)
--------------------------------
 There are 27 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.836        0.000                      0                  250        0.104        0.000                      0                  250        2.353        0.000                       0                   283  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock  Waveform(ns)         Period(ns)      Frequency(MHz)
-----  ------------         ----------      --------------
clk    {0.000 3.333}        6.667           149.993         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
clk                 0.836        0.000                      0                  250        0.104        0.000                      0                  250        2.353        0.000                       0                   283  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  clk
  To Clock:  clk

Setup :            0  Failing Endpoints,  Worst Slack        0.836ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.104ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.353ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.836ns  (required time - arrival time)
  Source:                 u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.778ns  (logic 1.970ns (34.098%)  route 3.808ns (65.902%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=2 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.973     0.973    u_dut/u_sub_norm/clk
    SLICE_X1Y78          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X1Y78          FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/Q
                         net (fo=23, routed)          0.983     2.412    u_dut/u_sub_norm/g_data[2].g_split.data_r[20]
    SLICE_X2Y81          LUT4 (Prop_lut4_I1_O)        0.124     2.536 r  u_dut/u_sub_norm/y[24]_INST_0_i_20/O
                         net (fo=1, routed)           0.000     2.536    u_dut/u_sub_norm/y[24]_INST_0_i_20_n_0
    SLICE_X2Y81          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     3.049 r  u_dut/u_sub_norm/y[24]_INST_0_i_16/CO[3]
                         net (fo=1, routed)           0.000     3.049    u_dut/u_sub_norm/y[24]_INST_0_i_16_n_0
    SLICE_X2Y82          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323     3.372 r  u_dut/u_sub_norm/y[25]_INST_0_i_4/O[1]
                         net (fo=2, routed)           0.654     4.025    u_dut/u_sub_norm/s3_sub_exp_biased[5]
    SLICE_X3Y81          LUT3 (Prop_lut3_I2_O)        0.306     4.331 r  u_dut/u_sub_norm/y[24]_INST_0_i_4/O
                         net (fo=2, routed)           1.017     5.348    u_dut/u_sub_norm/s3_pack_exp_biased__0[5]
    SLICE_X3Y80          LUT6 (Prop_lut6_I0_O)        0.124     5.472 f  u_dut/u_sub_norm/y[24]_INST_0_i_2/O
                         net (fo=25, routed)          1.154     6.627    u_dut/u_sub_norm/y[24]_INST_0_i_2_n_0
    SLICE_X3Y76          LUT4 (Prop_lut4_I2_O)        0.124     6.751 r  u_dut/u_sub_norm/y[7]_INST_0/O
                         net (fo=1, routed)           0.000     6.751    dut_y[7]
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=282, unset)          0.924     7.591    clk
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X3Y76          FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[7]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -6.751    
  -------------------------------------------------------------------
                         slack                                  0.836    

Slack (MET) :             0.836ns  (required time - arrival time)
  Source:                 u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.778ns  (logic 1.970ns (34.098%)  route 3.808ns (65.902%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=2 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.973     0.973    u_dut/u_sub_norm/clk
    SLICE_X1Y78          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X1Y78          FDRE (Prop_fdre_C_Q)         0.456     1.429 f  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/Q
                         net (fo=23, routed)          0.983     2.412    u_dut/u_sub_norm/g_data[2].g_split.data_r[20]
    SLICE_X2Y81          LUT4 (Prop_lut4_I1_O)        0.124     2.536 r  u_dut/u_sub_norm/y[24]_INST_0_i_20/O
                         net (fo=1, routed)           0.000     2.536    u_dut/u_sub_norm/y[24]_INST_0_i_20_n_0
    SLICE_X2Y81          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     3.049 r  u_dut/u_sub_norm/y[24]_INST_0_i_16/CO[3]
                         net (fo=1, routed)           0.000     3.049    u_dut/u_sub_norm/y[24]_INST_0_i_16_n_0
    SLICE_X2Y82          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323     3.372 r  u_dut/u_sub_norm/y[25]_INST_0_i_4/O[1]
                         net (fo=2, routed)           0.654     4.025    u_dut/u_sub_norm/s3_sub_exp_biased[5]
    SLICE_X3Y81          LUT3 (Prop_lut3_I2_O)        0.306     4.331 r  u_dut/u_sub_norm/y[24]_INST_0_i_4/O
                         net (fo=2, routed)           1.017     5.348    u_dut/u_sub_norm/s3_pack_exp_biased__0[5]
    SLICE_X3Y80          LUT6 (Prop_lut6_I0_O)        0.124     5.472 f  u_dut/u_sub_norm/y[24]_INST_0_i_2/O
                         net (fo=25, routed)          1.154     6.627    u_dut/u_sub_norm/y[24]_INST_0_i_2_n_0
    SLICE_X3Y76          LUT4 (Prop_lut4_I2_O)        0.124     6.751 r  u_dut/u_sub_norm/y[7]_INST_0/O
                         net (fo=1, routed)           0.000     6.751    dut_y[7]
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=282, unset)          0.924     7.591    clk
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X3Y76          FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[7]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -6.751    
  -------------------------------------------------------------------
                         slack                                  0.836    

Slack (MET) :             0.836ns  (required time - arrival time)
  Source:                 u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.778ns  (logic 1.970ns (34.098%)  route 3.808ns (65.902%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=2 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.973     0.973    u_dut/u_sub_norm/clk
    SLICE_X1Y78          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X1Y78          FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/Q
                         net (fo=23, routed)          0.983     2.412    u_dut/u_sub_norm/g_data[2].g_split.data_r[20]
    SLICE_X2Y81          LUT4 (Prop_lut4_I1_O)        0.124     2.536 f  u_dut/u_sub_norm/y[24]_INST_0_i_20/O
                         net (fo=1, routed)           0.000     2.536    u_dut/u_sub_norm/y[24]_INST_0_i_20_n_0
    SLICE_X2Y81          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     3.049 r  u_dut/u_sub_norm/y[24]_INST_0_i_16/CO[3]
                         net (fo=1, routed)           0.000     3.049    u_dut/u_sub_norm/y[24]_INST_0_i_16_n_0
    SLICE_X2Y82          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323     3.372 r  u_dut/u_sub_norm/y[25]_INST_0_i_4/O[1]
                         net (fo=2, routed)           0.654     4.025    u_dut/u_sub_norm/s3_sub_exp_biased[5]
    SLICE_X3Y81          LUT3 (Prop_lut3_I2_O)        0.306     4.331 r  u_dut/u_sub_norm/y[24]_INST_0_i_4/O
                         net (fo=2, routed)           1.017     5.348    u_dut/u_sub_norm/s3_pack_exp_biased__0[5]
    SLICE_X3Y80          LUT6 (Prop_lut6_I0_O)        0.124     5.472 f  u_dut/u_sub_norm/y[24]_INST_0_i_2/O
                         net (fo=25, routed)          1.154     6.627    u_dut/u_sub_norm/y[24]_INST_0_i_2_n_0
    SLICE_X3Y76          LUT4 (Prop_lut4_I2_O)        0.124     6.751 r  u_dut/u_sub_norm/y[7]_INST_0/O
                         net (fo=1, routed)           0.000     6.751    dut_y[7]
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=282, unset)          0.924     7.591    clk
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X3Y76          FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[7]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -6.751    
  -------------------------------------------------------------------
                         slack                                  0.836    

Slack (MET) :             0.836ns  (required time - arrival time)
  Source:                 u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.778ns  (logic 1.970ns (34.098%)  route 3.808ns (65.902%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=2 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.973     0.973    u_dut/u_sub_norm/clk
    SLICE_X1Y78          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X1Y78          FDRE (Prop_fdre_C_Q)         0.456     1.429 f  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/Q
                         net (fo=23, routed)          0.983     2.412    u_dut/u_sub_norm/g_data[2].g_split.data_r[20]
    SLICE_X2Y81          LUT4 (Prop_lut4_I1_O)        0.124     2.536 f  u_dut/u_sub_norm/y[24]_INST_0_i_20/O
                         net (fo=1, routed)           0.000     2.536    u_dut/u_sub_norm/y[24]_INST_0_i_20_n_0
    SLICE_X2Y81          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     3.049 r  u_dut/u_sub_norm/y[24]_INST_0_i_16/CO[3]
                         net (fo=1, routed)           0.000     3.049    u_dut/u_sub_norm/y[24]_INST_0_i_16_n_0
    SLICE_X2Y82          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323     3.372 r  u_dut/u_sub_norm/y[25]_INST_0_i_4/O[1]
                         net (fo=2, routed)           0.654     4.025    u_dut/u_sub_norm/s3_sub_exp_biased[5]
    SLICE_X3Y81          LUT3 (Prop_lut3_I2_O)        0.306     4.331 r  u_dut/u_sub_norm/y[24]_INST_0_i_4/O
                         net (fo=2, routed)           1.017     5.348    u_dut/u_sub_norm/s3_pack_exp_biased__0[5]
    SLICE_X3Y80          LUT6 (Prop_lut6_I0_O)        0.124     5.472 f  u_dut/u_sub_norm/y[24]_INST_0_i_2/O
                         net (fo=25, routed)          1.154     6.627    u_dut/u_sub_norm/y[24]_INST_0_i_2_n_0
    SLICE_X3Y76          LUT4 (Prop_lut4_I2_O)        0.124     6.751 r  u_dut/u_sub_norm/y[7]_INST_0/O
                         net (fo=1, routed)           0.000     6.751    dut_y[7]
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=282, unset)          0.924     7.591    clk
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X3Y76          FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[7]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -6.751    
  -------------------------------------------------------------------
                         slack                                  0.836    

Slack (MET) :             0.836ns  (required time - arrival time)
  Source:                 u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.778ns  (logic 1.970ns (34.098%)  route 3.808ns (65.902%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=2 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.973     0.973    u_dut/u_sub_norm/clk
    SLICE_X1Y78          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X1Y78          FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/Q
                         net (fo=23, routed)          0.983     2.412    u_dut/u_sub_norm/g_data[2].g_split.data_r[20]
    SLICE_X2Y81          LUT4 (Prop_lut4_I1_O)        0.124     2.536 r  u_dut/u_sub_norm/y[24]_INST_0_i_20/O
                         net (fo=1, routed)           0.000     2.536    u_dut/u_sub_norm/y[24]_INST_0_i_20_n_0
    SLICE_X2Y81          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     3.049 f  u_dut/u_sub_norm/y[24]_INST_0_i_16/CO[3]
                         net (fo=1, routed)           0.000     3.049    u_dut/u_sub_norm/y[24]_INST_0_i_16_n_0
    SLICE_X2Y82          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323     3.372 r  u_dut/u_sub_norm/y[25]_INST_0_i_4/O[1]
                         net (fo=2, routed)           0.654     4.025    u_dut/u_sub_norm/s3_sub_exp_biased[5]
    SLICE_X3Y81          LUT3 (Prop_lut3_I2_O)        0.306     4.331 r  u_dut/u_sub_norm/y[24]_INST_0_i_4/O
                         net (fo=2, routed)           1.017     5.348    u_dut/u_sub_norm/s3_pack_exp_biased__0[5]
    SLICE_X3Y80          LUT6 (Prop_lut6_I0_O)        0.124     5.472 f  u_dut/u_sub_norm/y[24]_INST_0_i_2/O
                         net (fo=25, routed)          1.154     6.627    u_dut/u_sub_norm/y[24]_INST_0_i_2_n_0
    SLICE_X3Y76          LUT4 (Prop_lut4_I2_O)        0.124     6.751 r  u_dut/u_sub_norm/y[7]_INST_0/O
                         net (fo=1, routed)           0.000     6.751    dut_y[7]
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=282, unset)          0.924     7.591    clk
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X3Y76          FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[7]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -6.751    
  -------------------------------------------------------------------
                         slack                                  0.836    

Slack (MET) :             0.836ns  (required time - arrival time)
  Source:                 u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.778ns  (logic 1.970ns (34.098%)  route 3.808ns (65.902%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=2 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.973     0.973    u_dut/u_sub_norm/clk
    SLICE_X1Y78          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X1Y78          FDRE (Prop_fdre_C_Q)         0.456     1.429 f  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/Q
                         net (fo=23, routed)          0.983     2.412    u_dut/u_sub_norm/g_data[2].g_split.data_r[20]
    SLICE_X2Y81          LUT4 (Prop_lut4_I1_O)        0.124     2.536 r  u_dut/u_sub_norm/y[24]_INST_0_i_20/O
                         net (fo=1, routed)           0.000     2.536    u_dut/u_sub_norm/y[24]_INST_0_i_20_n_0
    SLICE_X2Y81          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     3.049 f  u_dut/u_sub_norm/y[24]_INST_0_i_16/CO[3]
                         net (fo=1, routed)           0.000     3.049    u_dut/u_sub_norm/y[24]_INST_0_i_16_n_0
    SLICE_X2Y82          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323     3.372 r  u_dut/u_sub_norm/y[25]_INST_0_i_4/O[1]
                         net (fo=2, routed)           0.654     4.025    u_dut/u_sub_norm/s3_sub_exp_biased[5]
    SLICE_X3Y81          LUT3 (Prop_lut3_I2_O)        0.306     4.331 r  u_dut/u_sub_norm/y[24]_INST_0_i_4/O
                         net (fo=2, routed)           1.017     5.348    u_dut/u_sub_norm/s3_pack_exp_biased__0[5]
    SLICE_X3Y80          LUT6 (Prop_lut6_I0_O)        0.124     5.472 f  u_dut/u_sub_norm/y[24]_INST_0_i_2/O
                         net (fo=25, routed)          1.154     6.627    u_dut/u_sub_norm/y[24]_INST_0_i_2_n_0
    SLICE_X3Y76          LUT4 (Prop_lut4_I2_O)        0.124     6.751 r  u_dut/u_sub_norm/y[7]_INST_0/O
                         net (fo=1, routed)           0.000     6.751    dut_y[7]
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=282, unset)          0.924     7.591    clk
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X3Y76          FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[7]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -6.751    
  -------------------------------------------------------------------
                         slack                                  0.836    

Slack (MET) :             0.836ns  (required time - arrival time)
  Source:                 u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.778ns  (logic 1.970ns (34.098%)  route 3.808ns (65.902%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=2 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.973     0.973    u_dut/u_sub_norm/clk
    SLICE_X1Y78          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X1Y78          FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/Q
                         net (fo=23, routed)          0.983     2.412    u_dut/u_sub_norm/g_data[2].g_split.data_r[20]
    SLICE_X2Y81          LUT4 (Prop_lut4_I1_O)        0.124     2.536 f  u_dut/u_sub_norm/y[24]_INST_0_i_20/O
                         net (fo=1, routed)           0.000     2.536    u_dut/u_sub_norm/y[24]_INST_0_i_20_n_0
    SLICE_X2Y81          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     3.049 f  u_dut/u_sub_norm/y[24]_INST_0_i_16/CO[3]
                         net (fo=1, routed)           0.000     3.049    u_dut/u_sub_norm/y[24]_INST_0_i_16_n_0
    SLICE_X2Y82          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323     3.372 r  u_dut/u_sub_norm/y[25]_INST_0_i_4/O[1]
                         net (fo=2, routed)           0.654     4.025    u_dut/u_sub_norm/s3_sub_exp_biased[5]
    SLICE_X3Y81          LUT3 (Prop_lut3_I2_O)        0.306     4.331 r  u_dut/u_sub_norm/y[24]_INST_0_i_4/O
                         net (fo=2, routed)           1.017     5.348    u_dut/u_sub_norm/s3_pack_exp_biased__0[5]
    SLICE_X3Y80          LUT6 (Prop_lut6_I0_O)        0.124     5.472 f  u_dut/u_sub_norm/y[24]_INST_0_i_2/O
                         net (fo=25, routed)          1.154     6.627    u_dut/u_sub_norm/y[24]_INST_0_i_2_n_0
    SLICE_X3Y76          LUT4 (Prop_lut4_I2_O)        0.124     6.751 r  u_dut/u_sub_norm/y[7]_INST_0/O
                         net (fo=1, routed)           0.000     6.751    dut_y[7]
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=282, unset)          0.924     7.591    clk
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X3Y76          FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[7]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -6.751    
  -------------------------------------------------------------------
                         slack                                  0.836    

Slack (MET) :             0.836ns  (required time - arrival time)
  Source:                 u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.778ns  (logic 1.970ns (34.098%)  route 3.808ns (65.902%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=2 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.973     0.973    u_dut/u_sub_norm/clk
    SLICE_X1Y78          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X1Y78          FDRE (Prop_fdre_C_Q)         0.456     1.429 f  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/Q
                         net (fo=23, routed)          0.983     2.412    u_dut/u_sub_norm/g_data[2].g_split.data_r[20]
    SLICE_X2Y81          LUT4 (Prop_lut4_I1_O)        0.124     2.536 f  u_dut/u_sub_norm/y[24]_INST_0_i_20/O
                         net (fo=1, routed)           0.000     2.536    u_dut/u_sub_norm/y[24]_INST_0_i_20_n_0
    SLICE_X2Y81          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     3.049 f  u_dut/u_sub_norm/y[24]_INST_0_i_16/CO[3]
                         net (fo=1, routed)           0.000     3.049    u_dut/u_sub_norm/y[24]_INST_0_i_16_n_0
    SLICE_X2Y82          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323     3.372 r  u_dut/u_sub_norm/y[25]_INST_0_i_4/O[1]
                         net (fo=2, routed)           0.654     4.025    u_dut/u_sub_norm/s3_sub_exp_biased[5]
    SLICE_X3Y81          LUT3 (Prop_lut3_I2_O)        0.306     4.331 r  u_dut/u_sub_norm/y[24]_INST_0_i_4/O
                         net (fo=2, routed)           1.017     5.348    u_dut/u_sub_norm/s3_pack_exp_biased__0[5]
    SLICE_X3Y80          LUT6 (Prop_lut6_I0_O)        0.124     5.472 f  u_dut/u_sub_norm/y[24]_INST_0_i_2/O
                         net (fo=25, routed)          1.154     6.627    u_dut/u_sub_norm/y[24]_INST_0_i_2_n_0
    SLICE_X3Y76          LUT4 (Prop_lut4_I2_O)        0.124     6.751 r  u_dut/u_sub_norm/y[7]_INST_0/O
                         net (fo=1, routed)           0.000     6.751    dut_y[7]
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=282, unset)          0.924     7.591    clk
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X3Y76          FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[7]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -6.751    
  -------------------------------------------------------------------
                         slack                                  0.836    

Slack (MET) :             0.836ns  (required time - arrival time)
  Source:                 u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.778ns  (logic 1.970ns (34.098%)  route 3.808ns (65.902%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=2 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.973     0.973    u_dut/u_sub_norm/clk
    SLICE_X1Y78          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X1Y78          FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/Q
                         net (fo=23, routed)          0.983     2.412    u_dut/u_sub_norm/g_data[2].g_split.data_r[20]
    SLICE_X2Y81          LUT4 (Prop_lut4_I1_O)        0.124     2.536 r  u_dut/u_sub_norm/y[24]_INST_0_i_20/O
                         net (fo=1, routed)           0.000     2.536    u_dut/u_sub_norm/y[24]_INST_0_i_20_n_0
    SLICE_X2Y81          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     3.049 r  u_dut/u_sub_norm/y[24]_INST_0_i_16/CO[3]
                         net (fo=1, routed)           0.000     3.049    u_dut/u_sub_norm/y[24]_INST_0_i_16_n_0
    SLICE_X2Y82          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323     3.372 f  u_dut/u_sub_norm/y[25]_INST_0_i_4/O[1]
                         net (fo=2, routed)           0.654     4.025    u_dut/u_sub_norm/s3_sub_exp_biased[5]
    SLICE_X3Y81          LUT3 (Prop_lut3_I2_O)        0.306     4.331 f  u_dut/u_sub_norm/y[24]_INST_0_i_4/O
                         net (fo=2, routed)           1.017     5.348    u_dut/u_sub_norm/s3_pack_exp_biased__0[5]
    SLICE_X3Y80          LUT6 (Prop_lut6_I0_O)        0.124     5.472 r  u_dut/u_sub_norm/y[24]_INST_0_i_2/O
                         net (fo=25, routed)          1.154     6.627    u_dut/u_sub_norm/y[24]_INST_0_i_2_n_0
    SLICE_X3Y76          LUT4 (Prop_lut4_I2_O)        0.124     6.751 f  u_dut/u_sub_norm/y[7]_INST_0/O
                         net (fo=1, routed)           0.000     6.751    dut_y[7]
    SLICE_X3Y76          FDRE                                         f  y_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=282, unset)          0.924     7.591    clk
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X3Y76          FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[7]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -6.751    
  -------------------------------------------------------------------
                         slack                                  0.836    

Slack (MET) :             0.836ns  (required time - arrival time)
  Source:                 u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.778ns  (logic 1.970ns (34.098%)  route 3.808ns (65.902%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=2 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.973     0.973    u_dut/u_sub_norm/clk
    SLICE_X1Y78          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X1Y78          FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[20]/Q
                         net (fo=23, routed)          0.983     2.412    u_dut/u_sub_norm/g_data[2].g_split.data_r[20]
    SLICE_X2Y81          LUT4 (Prop_lut4_I1_O)        0.124     2.536 r  u_dut/u_sub_norm/y[24]_INST_0_i_20/O
                         net (fo=1, routed)           0.000     2.536    u_dut/u_sub_norm/y[24]_INST_0_i_20_n_0
    SLICE_X2Y81          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     3.049 f  u_dut/u_sub_norm/y[24]_INST_0_i_16/CO[3]
                         net (fo=1, routed)           0.000     3.049    u_dut/u_sub_norm/y[24]_INST_0_i_16_n_0
    SLICE_X2Y82          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323     3.372 f  u_dut/u_sub_norm/y[25]_INST_0_i_4/O[1]
                         net (fo=2, routed)           0.654     4.025    u_dut/u_sub_norm/s3_sub_exp_biased[5]
    SLICE_X3Y81          LUT3 (Prop_lut3_I2_O)        0.306     4.331 f  u_dut/u_sub_norm/y[24]_INST_0_i_4/O
                         net (fo=2, routed)           1.017     5.348    u_dut/u_sub_norm/s3_pack_exp_biased__0[5]
    SLICE_X3Y80          LUT6 (Prop_lut6_I0_O)        0.124     5.472 r  u_dut/u_sub_norm/y[24]_INST_0_i_2/O
                         net (fo=25, routed)          1.154     6.627    u_dut/u_sub_norm/y[24]_INST_0_i_2_n_0
    SLICE_X3Y76          LUT4 (Prop_lut4_I2_O)        0.124     6.751 f  u_dut/u_sub_norm/y[7]_INST_0/O
                         net (fo=1, routed)           0.000     6.751    dut_y[7]
    SLICE_X3Y76          FDRE                                         f  y_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=282, unset)          0.924     7.591    clk
    SLICE_X3Y76          FDRE                                         r  y_r_reg[7]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X3Y76          FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[7]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -6.751    
  -------------------------------------------------------------------
                         slack                                  0.836    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.104ns  (arrival time - required time)
  Source:                 u_dut/s2_same_sign_reg/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s3_same_sign_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.410     0.410    u_dut/clk
    SLICE_X3Y81          FDRE                                         r  u_dut/s2_same_sign_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y81          FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/s2_same_sign_reg/Q
                         net (fo=1, routed)           0.056     0.607    u_dut/s2_same_sign
    SLICE_X3Y81          FDRE                                         r  u_dut/s3_same_sign_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.432     0.432    u_dut/clk
    SLICE_X3Y81          FDRE                                         r  u_dut/s3_same_sign_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X3Y81          FDRE (Hold_fdre_C_D)         0.071     0.503    u_dut/s3_same_sign_reg
  -------------------------------------------------------------------
                         required time                         -0.503    
                         arrival time                           0.607    
  -------------------------------------------------------------------
                         slack                                  0.104    

Slack (MET) :             0.104ns  (arrival time - required time)
  Source:                 u_dut/s2_same_sign_reg/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s3_same_sign_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.410     0.410    u_dut/clk
    SLICE_X3Y81          FDRE                                         r  u_dut/s2_same_sign_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y81          FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/s2_same_sign_reg/Q
                         net (fo=1, routed)           0.056     0.607    u_dut/s2_same_sign
    SLICE_X3Y81          FDRE                                         f  u_dut/s3_same_sign_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.432     0.432    u_dut/clk
    SLICE_X3Y81          FDRE                                         r  u_dut/s3_same_sign_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X3Y81          FDRE (Hold_fdre_C_D)         0.071     0.503    u_dut/s3_same_sign_reg
  -------------------------------------------------------------------
                         required time                         -0.503    
                         arrival time                           0.607    
  -------------------------------------------------------------------
                         slack                                  0.104    

Slack (MET) :             0.144ns  (arrival time - required time)
  Source:                 u_dut/s0_large_sig_exp_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_large_ext_exp_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.240ns  (logic 0.141ns (58.691%)  route 0.099ns (41.309%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.410     0.410    u_dut/clk
    SLICE_X5Y81          FDRE                                         r  u_dut/s0_large_sig_exp_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y81          FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/s0_large_sig_exp_reg[17]/Q
                         net (fo=1, routed)           0.099     0.650    u_dut/s0_large_sig_exp[17]
    SLICE_X7Y80          FDRE                                         r  u_dut/s1_large_ext_exp_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.432     0.432    u_dut/clk
    SLICE_X7Y80          FDRE                                         r  u_dut/s1_large_ext_exp_reg[20]/C
                         clock pessimism              0.000     0.432    
    SLICE_X7Y80          FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/s1_large_ext_exp_reg[20]
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.650    
  -------------------------------------------------------------------
                         slack                                  0.144    

Slack (MET) :             0.144ns  (arrival time - required time)
  Source:                 u_dut/s0_large_sig_exp_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_large_ext_exp_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.240ns  (logic 0.141ns (58.691%)  route 0.099ns (41.309%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.410     0.410    u_dut/clk
    SLICE_X5Y81          FDRE                                         r  u_dut/s0_large_sig_exp_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y81          FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/s0_large_sig_exp_reg[17]/Q
                         net (fo=1, routed)           0.099     0.650    u_dut/s0_large_sig_exp[17]
    SLICE_X7Y80          FDRE                                         f  u_dut/s1_large_ext_exp_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.432     0.432    u_dut/clk
    SLICE_X7Y80          FDRE                                         r  u_dut/s1_large_ext_exp_reg[20]/C
                         clock pessimism              0.000     0.432    
    SLICE_X7Y80          FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/s1_large_ext_exp_reg[20]
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.650    
  -------------------------------------------------------------------
                         slack                                  0.144    

Slack (MET) :             0.162ns  (arrival time - required time)
  Source:                 u_dut/s0_inf_sign_reg/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_inf_sign_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.258ns  (logic 0.141ns (54.595%)  route 0.117ns (45.405%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.410     0.410    u_dut/clk
    SLICE_X4Y83          FDRE                                         r  u_dut/s0_inf_sign_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X4Y83          FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/s0_inf_sign_reg/Q
                         net (fo=1, routed)           0.117     0.668    u_dut/s0_inf_sign
    SLICE_X3Y83          FDRE                                         r  u_dut/s1_inf_sign_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.432     0.432    u_dut/clk
    SLICE_X3Y83          FDRE                                         r  u_dut/s1_inf_sign_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X3Y83          FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/s1_inf_sign_reg
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.668    
  -------------------------------------------------------------------
                         slack                                  0.162    

Slack (MET) :             0.162ns  (arrival time - required time)
  Source:                 u_dut/s0_inf_sign_reg/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_inf_sign_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.258ns  (logic 0.141ns (54.595%)  route 0.117ns (45.405%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.410     0.410    u_dut/clk
    SLICE_X4Y83          FDRE                                         r  u_dut/s0_inf_sign_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X4Y83          FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/s0_inf_sign_reg/Q
                         net (fo=1, routed)           0.117     0.668    u_dut/s0_inf_sign
    SLICE_X3Y83          FDRE                                         f  u_dut/s1_inf_sign_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.432     0.432    u_dut/clk
    SLICE_X3Y83          FDRE                                         r  u_dut/s1_inf_sign_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X3Y83          FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/s1_inf_sign_reg
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.668    
  -------------------------------------------------------------------
                         slack                                  0.162    

Slack (MET) :             0.169ns  (arrival time - required time)
  Source:                 u_dut/s1_inf_sign_reg/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s2_sign_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.281ns  (logic 0.227ns (80.665%)  route 0.054ns (19.335%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.410     0.410    u_dut/clk
    SLICE_X3Y83          FDRE                                         r  u_dut/s1_inf_sign_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y83          FDRE (Prop_fdre_C_Q)         0.128     0.538 r  u_dut/s1_inf_sign_reg/Q
                         net (fo=1, routed)           0.054     0.593    u_dut/s1_inf_sign
    SLICE_X3Y83          LUT3 (Prop_lut3_I0_O)        0.099     0.692 r  u_dut/s2_sign_i_1/O
                         net (fo=1, routed)           0.000     0.692    u_dut/s1_result_sign
    SLICE_X3Y83          FDRE                                         r  u_dut/s2_sign_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.432     0.432    u_dut/clk
    SLICE_X3Y83          FDRE                                         r  u_dut/s2_sign_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X3Y83          FDRE (Hold_fdre_C_D)         0.091     0.523    u_dut/s2_sign_reg
  -------------------------------------------------------------------
                         required time                         -0.523    
                         arrival time                           0.692    
  -------------------------------------------------------------------
                         slack                                  0.169    

Slack (MET) :             0.169ns  (arrival time - required time)
  Source:                 u_dut/s1_inf_sign_reg/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s2_sign_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.281ns  (logic 0.227ns (80.665%)  route 0.054ns (19.335%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.410     0.410    u_dut/clk
    SLICE_X3Y83          FDRE                                         r  u_dut/s1_inf_sign_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y83          FDRE (Prop_fdre_C_Q)         0.128     0.538 f  u_dut/s1_inf_sign_reg/Q
                         net (fo=1, routed)           0.054     0.593    u_dut/s1_inf_sign
    SLICE_X3Y83          LUT3 (Prop_lut3_I0_O)        0.099     0.692 f  u_dut/s2_sign_i_1/O
                         net (fo=1, routed)           0.000     0.692    u_dut/s1_result_sign
    SLICE_X3Y83          FDRE                                         f  u_dut/s2_sign_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.432     0.432    u_dut/clk
    SLICE_X3Y83          FDRE                                         r  u_dut/s2_sign_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X3Y83          FDRE (Hold_fdre_C_D)         0.091     0.523    u_dut/s2_sign_reg
  -------------------------------------------------------------------
                         required time                         -0.523    
                         arrival time                           0.692    
  -------------------------------------------------------------------
                         slack                                  0.169    

Slack (MET) :             0.170ns  (arrival time - required time)
  Source:                 in_valid_r_reg/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s0_valid_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.257ns  (logic 0.141ns (54.828%)  route 0.116ns (45.172%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.410     0.410    clk
    SLICE_X37Y75         FDRE                                         r  in_valid_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y75         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  in_valid_r_reg/Q
                         net (fo=1, routed)           0.116     0.667    u_dut/in_valid
    SLICE_X37Y75         FDRE                                         r  u_dut/s0_valid_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.432     0.432    u_dut/clk
    SLICE_X37Y75         FDRE                                         r  u_dut/s0_valid_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X37Y75         FDRE (Hold_fdre_C_D)         0.066     0.498    u_dut/s0_valid_reg
  -------------------------------------------------------------------
                         required time                         -0.498    
                         arrival time                           0.667    
  -------------------------------------------------------------------
                         slack                                  0.170    

Slack (MET) :             0.170ns  (arrival time - required time)
  Source:                 in_valid_r_reg/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s0_valid_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.257ns  (logic 0.141ns (54.828%)  route 0.116ns (45.172%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.410     0.410    clk
    SLICE_X37Y75         FDRE                                         r  in_valid_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y75         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  in_valid_r_reg/Q
                         net (fo=1, routed)           0.116     0.667    u_dut/in_valid
    SLICE_X37Y75         FDRE                                         f  u_dut/s0_valid_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=282, unset)          0.432     0.432    u_dut/clk
    SLICE_X37Y75         FDRE                                         r  u_dut/s0_valid_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X37Y75         FDRE (Hold_fdre_C_D)         0.066     0.498    u_dut/s0_valid_reg
  -------------------------------------------------------------------
                         required time                         -0.498    
                         arrival time                           0.667    
  -------------------------------------------------------------------
                         slack                                  0.170    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.667
Sources:            { clk }

Check Type        Corner  Lib Pin     Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X11Y76  a_r_reg[0]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X11Y77  a_r_reg[10]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X11Y78  a_r_reg[11]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X10Y80  a_r_reg[12]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X10Y80  a_r_reg[13]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X10Y79  a_r_reg[14]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X10Y80  a_r_reg[15]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X11Y80  a_r_reg[16]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X10Y81  a_r_reg[17]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X10Y81  a_r_reg[18]/C
Low Pulse Width   Slow    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y81   u_dut/s1_exp_biased_reg[0]_srl2/CLK
Low Pulse Width   Fast    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y81   u_dut/s1_exp_biased_reg[0]_srl2/CLK
Low Pulse Width   Slow    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y81   u_dut/s1_exp_biased_reg[1]_srl2/CLK
Low Pulse Width   Fast    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y81   u_dut/s1_exp_biased_reg[1]_srl2/CLK
Low Pulse Width   Slow    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y81   u_dut/s1_exp_biased_reg[2]_srl2/CLK
Low Pulse Width   Fast    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y81   u_dut/s1_exp_biased_reg[2]_srl2/CLK
Low Pulse Width   Slow    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y81   u_dut/s1_exp_biased_reg[3]_srl2/CLK
Low Pulse Width   Fast    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y81   u_dut/s1_exp_biased_reg[3]_srl2/CLK
Low Pulse Width   Slow    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y81   u_dut/s1_exp_biased_reg[4]_srl2/CLK
Low Pulse Width   Fast    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y81   u_dut/s1_exp_biased_reg[4]_srl2/CLK
High Pulse Width  Slow    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y81   u_dut/s1_exp_biased_reg[0]_srl2/CLK
High Pulse Width  Fast    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y81   u_dut/s1_exp_biased_reg[0]_srl2/CLK
High Pulse Width  Slow    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y81   u_dut/s1_exp_biased_reg[1]_srl2/CLK
High Pulse Width  Fast    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y81   u_dut/s1_exp_biased_reg[1]_srl2/CLK
High Pulse Width  Slow    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y81   u_dut/s1_exp_biased_reg[2]_srl2/CLK
High Pulse Width  Fast    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y81   u_dut/s1_exp_biased_reg[2]_srl2/CLK
High Pulse Width  Slow    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y81   u_dut/s1_exp_biased_reg[3]_srl2/CLK
High Pulse Width  Fast    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y81   u_dut/s1_exp_biased_reg[3]_srl2/CLK
High Pulse Width  Slow    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y81   u_dut/s1_exp_biased_reg[4]_srl2/CLK
High Pulse Width  Fast    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y81   u_dut/s1_exp_biased_reg[4]_srl2/CLK



