Lattice Place and Route Report for Design "/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/tommath_div_e8_m17_compact_p2/top_tommath_div_e8_m17_compact_p2_map.ncd" Sun May 24 13:51:40 2026 PAR: Place And Route Diamond (64-bit) 3.14.0.75.2. Command Line: /usr/local/diamond/3.14/ispfpga/bin/lin64/par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/tommath_div_e8_m17_compact_p2/top_tommath_div_e8_m17_compact_p2_map.ncd /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/tommath_div_e8_m17_compact_p2/top_tommath_div_e8_m17_compact_p2.ncd /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/tommath_div_e8_m17_compact_p2/top_tommath_div_e8_m17_compact_p2.prf Preference file: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/tommath_div_e8_m17_compact_p2/top_tommath_div_e8_m17_compact_p2.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/tommath_div_e8_m17_compact_p2/top_tommath_div_e8_m17_compact_p2_map.ncd. Design name: top_tommath_div_e8_m17_compact_p2 NCD version: 3.3 Vendor: LATTICE Device: LFE5U-12F Package: CABGA381 Performance: 6 Loading device for application par from file 'sa5p25.nph' in environment: /usr/local/diamond/3.14/ispfpga. Package Status: Final Version 1.44. Performance Hardware Data Status: Final Version 55.1. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 82/197 41% used 82/197 41% bonded SLICE 217/6048 3% used GSR 1/1 100% used EBR 1/32 3% used MULT18 3/28 10% used ALU54 1/14 7% used Number of Signals: 664 Number of Connections: 1281 Pin Constraint Summary: 0 out of 82 pins locked (0% locked). The following 6 signals are selected to use the primary clock routing resources: clk_c (driver: clk, clk/ce/sr load #: 175/0/0) u_dut/p1_vld (driver: u_dut/SLICE_145, clk/ce/sr load #: 0/27/0) u_dut/p2_vld (driver: u_dut/SLICE_145, clk/ce/sr load #: 0/27/0) in_valid_r (driver: SLICE_198, clk/ce/sr load #: 0/23/0) u_dut/p3_vld (driver: u_dut/SLICE_146, clk/ce/sr load #: 0/22/0) p4_vld (driver: u_dut/SLICE_86, clk/ce/sr load #: 0/21/0) Signal rst_c is selected as Global Set/Reset. . Starting Placer Phase 0. ................. Finished Placer Phase 0. REAL time: 3 secs Starting Placer Phase 1. ....................... Placer score = 143647. Finished Placer Phase 1. REAL time: 10 secs Starting Placer Phase 2. . Placer score = 139839 Finished Placer Phase 2. REAL time: 10 secs ------------------ Clock Report ------------------ Global Clock Resources: CLK_PIN : 1 out of 12 (8%) GR_PCLK : 0 out of 12 (0%) PLL : 0 out of 2 (0%) DCS : 0 out of 2 (0%) DCC : 0 out of 60 (0%) CLKDIV : 0 out of 4 (0%) Quadrant TL Clocks: PRIMARY "clk_c" from comp "clk" on CLK_PIN site "B11 (PT29A)", CLK/CE/SR load = 158 PRIMARY "u_dut/p1_vld" from Q1 on comp "u_dut/SLICE_145" on site "R41C11A", CLK/CE/SR load = 26 PRIMARY "u_dut/p2_vld" from Q0 on comp "u_dut/SLICE_145" on site "R41C11A", CLK/CE/SR load = 26 PRIMARY "in_valid_r" from Q0 on comp "SLICE_198" on site "R26C13C", CLK/CE/SR load = 22 PRIMARY "u_dut/p3_vld" from Q0 on comp "u_dut/SLICE_146" on site "R32C62A", CLK/CE/SR load = 21 PRIMARY "p4_vld" from Q0 on comp "u_dut/SLICE_86" on site "R48C6D", CLK/CE/SR load = 20 PRIMARY : 6 out of 16 (37%) Quadrant TR Clocks: PRIMARY : 0 out of 16 (0%) Quadrant BL Clocks: PRIMARY "clk_c" from comp "clk" on CLK_PIN site "B11 (PT29A)", CLK/CE/SR load = 16 PRIMARY "u_dut/p1_vld" from Q1 on comp "u_dut/SLICE_145" on site "R41C11A", CLK/CE/SR load = 1 PRIMARY "u_dut/p2_vld" from Q0 on comp "u_dut/SLICE_145" on site "R41C11A", CLK/CE/SR load = 1 PRIMARY "in_valid_r" from Q0 on comp "SLICE_198" on site "R26C13C", CLK/CE/SR load = 1 PRIMARY "u_dut/p3_vld" from Q0 on comp "u_dut/SLICE_146" on site "R32C62A", CLK/CE/SR load = 1 PRIMARY "p4_vld" from Q0 on comp "u_dut/SLICE_86" on site "R48C6D", CLK/CE/SR load = 1 PRIMARY : 6 out of 16 (37%) Quadrant BR Clocks: PRIMARY "clk_c" from comp "clk" on CLK_PIN site "B11 (PT29A)", CLK/CE/SR load = 1 PRIMARY : 1 out of 16 (6%) Edge Clocks: No edge clock selected. --------------- End of Clock Report --------------- + I/O Usage Summary (final): 82 out of 197 (41.6%) PIO sites used. 82 out of 197 (41.6%) bonded PIO sites used. Number of PIO comps: 82; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+----------------+------------+------------+------------+ | I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | +----------+----------------+------------+------------+------------+ | 0 | 24 / 24 (100%) | 2.5V | - | - | | 1 | 8 / 32 ( 25%) | 2.5V | - | - | | 2 | 0 / 32 ( 0%) | - | - | - | | 3 | 0 / 32 ( 0%) | - | - | - | | 6 | 13 / 32 ( 40%) | 2.5V | - | - | | 7 | 30 / 32 ( 93%) | 2.5V | - | - | | 8 | 7 / 13 ( 53%) | 2.5V | - | - | +----------+----------------+------------+------------+------------+ ---------------------------------- DSP Report ---------------------------------- DSP Slice #: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 # of MULT9 # of MULT18 2 1 # of ALU24 # of ALU54 1 # of PRADD9 # of PRADD18 DSP Slice 5 Component_Type Physical_Type Instance_Name MULT18_R13C22 MULT18X18D MULT18 u_dut/div_p5_res5_mult_2 MULT18_R13C23 MULT18X18D MULT18 u_dut/lat_mult_0 ALU54_R13C25 ALU54B ALU54 u_dut/lat_alu_1 DSP Slice 6 Component_Type Physical_Type Instance_Name MULT18_R13C26 MULT18X18D MULT18 u_dut/x_mul_yhyl_p3_res3_mult_2 ------------------------------ End of DSP Report ------------------------------- Total placer CPU time: 9 secs Dumping design to file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/tommath_div_e8_m17_compact_p2/top_tommath_div_e8_m17_compact_p2.ncd. 0 connections routed; 1281 unrouted. Starting router resource preassignment DSP info: No dsp pins have been swapped. Completed router resource preassignment. Real time: 15 secs Start NBR router at Sun May 24 13:51:55 EEST 2026 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at Sun May 24 13:51:55 EEST 2026 Start NBR section for initial routing at Sun May 24 13:51:55 EEST 2026 Level 1, iteration 1 3(0.00%) conflicts; 791(61.75%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 1.372ns/0.000ns; real time: 16 secs Level 2, iteration 1 15(0.00%) conflicts; 731(57.06%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 1.579ns/0.000ns; real time: 16 secs Level 3, iteration 1 12(0.00%) conflicts; 603(47.07%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 1.579ns/0.000ns; real time: 16 secs Level 4, iteration 1 28(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.579ns/0.000ns; real time: 16 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) Start NBR section for normal routing at Sun May 24 13:51:56 EEST 2026 Level 1, iteration 1 7(0.00%) conflicts; 21(1.64%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 1.579ns/0.000ns; real time: 16 secs Level 2, iteration 1 8(0.00%) conflicts; 21(1.64%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 1.579ns/0.000ns; real time: 16 secs Level 3, iteration 1 7(0.00%) conflicts; 21(1.64%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 1.579ns/0.000ns; real time: 16 secs Level 4, iteration 1 15(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.579ns/0.000ns; real time: 16 secs Level 4, iteration 2 6(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.575ns/0.000ns; real time: 17 secs Level 4, iteration 3 3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.575ns/0.000ns; real time: 17 secs Level 4, iteration 4 3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.575ns/0.000ns; real time: 17 secs Level 4, iteration 5 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.575ns/0.000ns; real time: 17 secs Level 4, iteration 6 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.575ns/0.000ns; real time: 17 secs Level 4, iteration 7 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.575ns/0.000ns; real time: 17 secs Start NBR section for setup/hold timing optimization with effort level 3 at Sun May 24 13:51:57 EEST 2026 Start NBR section for re-routing at Sun May 24 13:51:58 EEST 2026 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.575ns/0.000ns; real time: 18 secs Start NBR section for post-routing at Sun May 24 13:51:58 EEST 2026 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) Estimated worst slack : 1.575ns Timing score : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. Total CPU time 19 secs Total REAL time: 19 secs Completely routed. End of route. 1281 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 Timing score: 0 Dumping design to file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/tommath_div_e8_m17_compact_p2/top_tommath_div_e8_m17_compact_p2.ncd. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack> = 1.575 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Worst slack> = 0.174 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 19 secs Total REAL time to completion: 20 secs par done! Note: user must run 'Trace' for timing closure signoff. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2024 Lattice Semiconductor Corporation, All rights reserved. $ /usr/local/diamond/3.14/ispfpga/bin/lin64/par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/tommath_div_e8_m17_compact_p2/top_tommath_div_e8_m17_compact_p2_map.ncd /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/tommath_div_e8_m17_compact_p2/top_tommath_div_e8_m17_compact_p2.ncd /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/tommath_div_e8_m17_compact_p2/top_tommath_div_e8_m17_compact_p2.prf [exit code 0]