****** Vivado v2025.2.1 (64-bit) **** SW Build 6403652 on Thu Mar 19 13:47:00 MDT 2026 **** IP Build 6403511 on Thu Mar 19 12:41:45 MDT 2026 **** SharedData Build 6403650 on Thu Mar 19 14:02:13 MDT 2026 **** Start of session at: Sun May 24 15:24:55 2026 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved. source /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m35_large_p3/vivado.tcl -notrace read_xdc: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1552.828 ; gain = 37.840 ; free physical = 9322 ; free virtual = 20747 Command: synth_design -top top_tommath_div_e8_m35_large_p3 -part xc7s50csga324-1 -mode out_of_context -flatten_hierarchy rebuilt Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7s50' INFO: [Device 21-403] Loading part xc7s50csga324-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 1 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 385961 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2194.172 ; gain = 482.156 ; free physical = 8430 ; free virtual = 19855 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'top_tommath_div_e8_m35_large_p3' [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m35_large_p3/src/top_tommath_div_e8_m35_large_p3.v:3] INFO: [Synth 8-6157] synthesizing module 'FpxxDiv' [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m35_large_p3/src/tommath_div_e8_m35_large_p3.v:7] INFO: [Synth 8-3876] $readmem data file 'FpxxDiv.v_toplevel_div_table.bin' is read successfully [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m35_large_p3/src/tommath_div_e8_m35_large_p3.v:141] INFO: [Synth 8-6155] done synthesizing module 'FpxxDiv' (0#1) [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m35_large_p3/src/tommath_div_e8_m35_large_p3.v:7] INFO: [Synth 8-6155] done synthesizing module 'top_tommath_div_e8_m35_large_p3' (0#1) [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m35_large_p3/src/top_tommath_div_e8_m35_large_p3.v:3] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2282.141 ; gain = 570.125 ; free physical = 8349 ; free virtual = 19776 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2299.953 ; gain = 587.938 ; free physical = 8337 ; free virtual = 19763 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2299.953 ; gain = 587.938 ; free physical = 8337 ; free virtual = 19763 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2299.953 ; gain = 0.000 ; free physical = 8337 ; free virtual = 19763 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m35_large_p3/constraints.xdc] Finished Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m35_large_p3/constraints.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2376.672 ; gain = 0.000 ; free physical = 8299 ; free virtual = 19725 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2376.707 ; gain = 0.000 ; free physical = 8299 ; free virtual = 19725 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2376.707 ; gain = 664.691 ; free physical = 8240 ; free virtual = 19668 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7s50csga324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2384.676 ; gain = 672.660 ; free physical = 8240 ; free virtual = 19667 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2384.676 ; gain = 672.660 ; free physical = 8240 ; free virtual = 19667 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 2384.676 ; gain = 672.660 ; free physical = 8230 ; free virtual = 19659 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 3 Input 36 Bit Adders := 1 3 Input 10 Bit Adders := 1 2 Input 10 Bit Adders := 1 3 Input 9 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 72 Bit Registers := 1 60 Bit Registers := 1 44 Bit Registers := 3 39 Bit Registers := 1 36 Bit Registers := 2 35 Bit Registers := 3 21 Bit Registers := 3 20 Bit Registers := 1 10 Bit Registers := 5 9 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 32 +---Multipliers : 36x36 Multipliers := 1 21x39 Multipliers := 1 +---ROMs : ROMs := 1 +---Muxes : 2 Input 35 Bit Muxes := 3 2 Input 8 Bit Muxes := 3 4 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 120 (col length:60) BRAMs: 150 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element x_mul_yhyl_p3_reg was removed. [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m35_large_p3/src/tommath_div_e8_m35_large_p3.v:352] WARNING: [Synth 8-6014] Unused sequential element div_p5_reg was removed. [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m35_large_p3/src/tommath_div_e8_m35_large_p3.v:137] DSP Report: Generating DSP x_mul_yhyl_full_p2, operation Mode is: A*B''. DSP Report: register x_mul_yhyl_full_p2 is absorbed into DSP x_mul_yhyl_full_p2. DSP Report: register x_mul_yhyl_full_p2 is absorbed into DSP x_mul_yhyl_full_p2. DSP Report: operator x_mul_yhyl_full_p2 is absorbed into DSP x_mul_yhyl_full_p2. DSP Report: operator x_mul_yhyl_full_p2 is absorbed into DSP x_mul_yhyl_full_p2. DSP Report: Generating DSP x_mul_yhyl_p3_reg, operation Mode is: (PCIN>>17)+A''*B''. DSP Report: register x_mul_yhyl_p3_reg is absorbed into DSP x_mul_yhyl_p3_reg. DSP Report: register x_mul_yhyl_p3_reg is absorbed into DSP x_mul_yhyl_p3_reg. DSP Report: register yh_m_yl_p1_reg is absorbed into DSP x_mul_yhyl_p3_reg. DSP Report: register yh_m_yl_p2_reg is absorbed into DSP x_mul_yhyl_p3_reg. DSP Report: register x_mul_yhyl_p3_reg is absorbed into DSP x_mul_yhyl_p3_reg. DSP Report: operator x_mul_yhyl_full_p2 is absorbed into DSP x_mul_yhyl_p3_reg. DSP Report: operator x_mul_yhyl_full_p2 is absorbed into DSP x_mul_yhyl_p3_reg. DSP Report: Generating DSP x_mul_yhyl_full_p2, operation Mode is: A''*B''. DSP Report: register x_mul_yhyl_full_p2 is absorbed into DSP x_mul_yhyl_full_p2. DSP Report: register x_mul_yhyl_full_p2 is absorbed into DSP x_mul_yhyl_full_p2. DSP Report: register x_mul_yhyl_full_p2 is absorbed into DSP x_mul_yhyl_full_p2. DSP Report: register x_mul_yhyl_full_p2 is absorbed into DSP x_mul_yhyl_full_p2. DSP Report: operator x_mul_yhyl_full_p2 is absorbed into DSP x_mul_yhyl_full_p2. DSP Report: operator x_mul_yhyl_full_p2 is absorbed into DSP x_mul_yhyl_full_p2. DSP Report: Generating DSP x_mul_yhyl_p3_reg, operation Mode is: (PCIN>>17)+A''*B''. DSP Report: register x_mul_yhyl_p3_reg is absorbed into DSP x_mul_yhyl_p3_reg. DSP Report: register x_mul_yhyl_p3_reg is absorbed into DSP x_mul_yhyl_p3_reg. DSP Report: register yh_m_yl_p1_reg is absorbed into DSP x_mul_yhyl_p3_reg. DSP Report: register yh_m_yl_p2_reg is absorbed into DSP x_mul_yhyl_p3_reg. DSP Report: register x_mul_yhyl_p3_reg is absorbed into DSP x_mul_yhyl_p3_reg. DSP Report: operator x_mul_yhyl_full_p2 is absorbed into DSP x_mul_yhyl_p3_reg. DSP Report: operator x_mul_yhyl_full_p2 is absorbed into DSP x_mul_yhyl_p3_reg. DSP Report: Generating DSP div_p5_reg, operation Mode is: (A''*B2)'. DSP Report: register div_p5_reg is absorbed into DSP div_p5_reg. DSP Report: register div_p5_reg is absorbed into DSP div_p5_reg. DSP Report: register div_p5_reg is absorbed into DSP div_p5_reg. DSP Report: register div_p5_reg is absorbed into DSP div_p5_reg. DSP Report: operator div_full_p4 is absorbed into DSP div_p5_reg. DSP Report: operator div_full_p4 is absorbed into DSP div_p5_reg. DSP Report: Generating DSP div_full_p4, operation Mode is: A''*B2. DSP Report: register div_full_p4 is absorbed into DSP div_full_p4. DSP Report: register div_full_p4 is absorbed into DSP div_full_p4. DSP Report: register div_full_p4 is absorbed into DSP div_full_p4. DSP Report: operator div_full_p4 is absorbed into DSP div_full_p4. DSP Report: operator div_full_p4 is absorbed into DSP div_full_p4. DSP Report: Generating DSP div_p5_reg, operation Mode is: (PCIN>>17)+A''*B2. DSP Report: register div_p5_reg is absorbed into DSP div_p5_reg. DSP Report: register div_p5_reg is absorbed into DSP div_p5_reg. DSP Report: register div_p5_reg is absorbed into DSP div_p5_reg. DSP Report: register div_p5_reg is absorbed into DSP div_p5_reg. DSP Report: operator div_full_p4 is absorbed into DSP div_p5_reg. DSP Report: operator div_full_p4 is absorbed into DSP div_p5_reg. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[47]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[46]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[45]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[44]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[43]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[42]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[41]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[40]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[39]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[38]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[37]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[36]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[35]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[34]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[33]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[32]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[31]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[30]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[29]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[28]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[27]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[26]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[25]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[24]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[23]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[22]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[21]) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[47]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[46]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[45]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[44]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[43]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[42]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[41]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[40]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[39]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[38]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[37]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[36]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[35]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[34]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[33]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[32]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[31]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[30]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[29]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[28]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[27]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[26]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[25]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[24]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[23]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[22]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[21]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[20]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[19]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[18]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[17]__0) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[47]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[46]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[45]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[44]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[43]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[42]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[41]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[40]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[39]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[38]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[37]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[36]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[35]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[34]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[33]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[32]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[31]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[30]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[29]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[28]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[27]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[26]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[25]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[24]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[23]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[22]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[21]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[20]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[19]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[18]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[17]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[15]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[14]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[13]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[12]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[11]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[10]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[9]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[8]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[7]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[6]__1) is unused and will be removed from module FpxxDiv. WARNING: [Synth 8-3332] Sequential element (x_mul_yhyl_p3_reg[5]__1) is unused and will be removed from module FpxxDiv. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2384.676 ; gain = 672.660 ; free physical = 8238 ; free virtual = 19667 --------------------------------------------------------------------------------- Sort Area is x_mul_yhyl_full_p2_3 : 0 0 : 3272 6651 : Used 1 time 0 Sort Area is x_mul_yhyl_full_p2_3 : 0 1 : 3379 6651 : Used 1 time 0 Sort Area is x_mul_yhyl_full_p2_0 : 0 0 : 3173 6552 : Used 1 time 0 Sort Area is x_mul_yhyl_full_p2_0 : 0 1 : 3379 6552 : Used 1 time 0 Sort Area is div_full_p4_5 : 0 0 : 3190 6441 : Used 1 time 0 Sort Area is div_full_p4_5 : 0 1 : 3251 6441 : Used 1 time 0 Sort Area is div_p5_reg_8 : 0 0 : 1038 1038 : Used 1 time 0 --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- ROM: Preliminary Mapping Report +------------+-------------------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------+-------------------------+---------------+----------------+ |FpxxDiv | _zz_div_table_port0_reg | 1024x20 | Block RAM | +------------+-------------------------+---------------+----------------+ DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set) +------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | +------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |FpxxDiv | A*B'' | 20 | 18 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | |FpxxDiv | (PCIN>>17)+A''*B'' | 20 | 18 | - | - | 48 | 2 | 2 | - | - | - | 0 | 1 | |FpxxDiv | A''*B'' | 18 | 18 | - | - | 48 | 2 | 2 | - | - | - | 0 | 0 | |FpxxDiv | (PCIN>>17)+A''*B'' | 20 | 18 | - | - | 48 | 2 | 2 | - | - | - | 0 | 1 | |FpxxDiv | (A''*B2)' | 22 | 6 | - | - | 48 | 2 | 1 | - | - | - | 1 | 0 | |FpxxDiv | A''*B2 | 22 | 18 | - | - | 48 | 2 | 1 | - | - | - | 0 | 0 | |FpxxDiv | (PCIN>>17)+A''*B2 | 22 | 18 | - | - | 48 | 2 | 1 | - | - | - | 0 | 1 | +------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 2490.676 ; gain = 778.660 ; free physical = 8138 ; free virtual = 19567 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2493.676 ; gain = 781.660 ; free physical = 8130 ; free virtual = 19559 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 2521.723 ; gain = 809.707 ; free physical = 8105 ; free virtual = 19535 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2695.535 ; gain = 983.520 ; free physical = 7940 ; free virtual = 19369 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2695.535 ; gain = 983.520 ; free physical = 7940 ; free virtual = 19369 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2695.535 ; gain = 983.520 ; free physical = 7993 ; free virtual = 19422 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2695.535 ; gain = 983.520 ; free physical = 7993 ; free virtual = 19422 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2698.504 ; gain = 986.488 ; free physical = 7985 ; free virtual = 19414 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2698.504 ; gain = 986.488 ; free physical = 7985 ; free virtual = 19414 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- DSP Final Report (the ' indicates corresponding REG is set) +------------+---------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | +------------+---------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |FpxxDiv | A*B'' | 19 | 17 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | |FpxxDiv | (PCIN>>17+A''*B'')' | 19 | 17 | - | - | 48 | 2 | 2 | - | - | - | 0 | 1 | |FpxxDiv | A''*B'' | 17 | 17 | - | - | 48 | 2 | 2 | - | - | - | 0 | 0 | |FpxxDiv | (PCIN>>17+A''*B'')' | 19 | 17 | - | - | 48 | 2 | 2 | - | - | - | 0 | 1 | |FpxxDiv | (A''*B')' | 21 | 5 | - | - | 48 | 2 | 1 | - | - | - | 0 | 1 | |FpxxDiv | A''*B' | 21 | 17 | - | - | 48 | 2 | 1 | - | - | - | 0 | 0 | |FpxxDiv | (PCIN>>17+A''*B')' | 21 | 17 | - | - | 48 | 2 | 1 | - | - | - | 0 | 1 | +------------+---------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |CARRY4 | 42| |2 |DSP48E1 | 7| |8 |LUT1 | 35| |9 |LUT2 | 80| |10 |LUT3 | 39| |11 |LUT4 | 32| |12 |LUT5 | 59| |13 |LUT6 | 55| |14 |RAMB36E1 | 1| |15 |FDCE | 6| |16 |FDRE | 367| +------+---------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2698.504 ; gain = 986.488 ; free physical = 7985 ; free virtual = 19414 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 155 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2698.504 ; gain = 909.734 ; free physical = 7985 ; free virtual = 19414 Synthesis Optimization Complete : Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2698.512 ; gain = 986.488 ; free physical = 7985 ; free virtual = 19414 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2698.512 ; gain = 0.000 ; free physical = 7985 ; free virtual = 19414 INFO: [Netlist 29-17] Analyzing 50 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m35_large_p3/constraints.xdc] Finished Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m35_large_p3/constraints.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2698.512 ; gain = 0.000 ; free physical = 8157 ; free virtual = 19587 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Synth Design complete | Checksum: c0e8b42e INFO: [Common 17-83] Releasing license: Synthesis 20 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:30 . Memory (MB): peak = 2698.539 ; gain = 1145.711 ; free physical = 8157 ; free virtual = 19587 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2199.192; main = 2199.192; forked = 359.594 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3425.715; main = 2698.508; forked = 1018.035 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7s50' Running DRC as a precondition to command opt_design Starting DRC Task WARNING: [DRC 23-814] Not all possible (connectivity based) DRCs may have been run because this design is seen as Out of Context. INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2698.539 ; gain = 0.000 ; free physical = 8154 ; free virtual = 19583 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1e4f07164 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2698.539 ; gain = 0.000 ; free physical = 7985 ; free virtual = 19405 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 1e4f07164 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2698.539 ; gain = 0.000 ; free physical = 7975 ; free virtual = 19395 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1e4f07164 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2698.539 ; gain = 0.000 ; free physical = 7975 ; free virtual = 19395 Phase 1 Initialization | Checksum: 1e4f07164 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2698.539 ; gain = 0.000 ; free physical = 7975 ; free virtual = 19395 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Detect if minReqCache needed Phase 2.1 Detect if minReqCache needed | Checksum: 1e4f07164 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2698.539 ; gain = 0.000 ; free physical = 7975 ; free virtual = 19395 Phase 2.2 Timer Update Phase 2.2 Timer Update | Checksum: 1e4f07164 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2698.539 ; gain = 0.000 ; free physical = 7975 ; free virtual = 19395 Phase 2 Timer Update And Timing Data Collection | Checksum: 1e4f07164 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2698.539 ; gain = 0.000 ; free physical = 7975 ; free virtual = 19395 Phase 3 Retarget INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 1e4f07164 Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2698.539 ; gain = 0.000 ; free physical = 7975 ; free virtual = 19395 Retarget | Checksum: 1e4f07164 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 1c33e059a Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2698.539 ; gain = 0.000 ; free physical = 7975 ; free virtual = 19395 Constant propagation | Checksum: 1c33e059a INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2698.539 ; gain = 0.000 ; free physical = 7975 ; free virtual = 19395 Phase 5 Sweep | Checksum: 12c39d2c7 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2698.539 ; gain = 0.000 ; free physical = 7975 ; free virtual = 19395 Sweep | Checksum: 12c39d2c7 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Sweep, 268 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 12c39d2c7 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2730.520 ; gain = 31.980 ; free physical = 7975 ; free virtual = 19395 BUFG optimization | Checksum: 12c39d2c7 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 12c39d2c7 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2730.520 ; gain = 31.980 ; free physical = 7975 ; free virtual = 19395 Shift Register Optimization | Checksum: 12c39d2c7 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 12c39d2c7 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2730.520 ; gain = 31.980 ; free physical = 7975 ; free virtual = 19395 Post Processing Netlist | Checksum: 12c39d2c7 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 14742102e Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2730.520 ; gain = 31.980 ; free physical = 7975 ; free virtual = 19395 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2730.520 ; gain = 0.000 ; free physical = 7975 ; free virtual = 19395 Phase 9.2 Verifying Netlist Connectivity | Checksum: 14742102e Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2730.520 ; gain = 31.980 ; free physical = 7975 ; free virtual = 19395 Phase 9 Finalization | Checksum: 14742102e Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2730.520 ; gain = 31.980 ; free physical = 7975 ; free virtual = 19395 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 0 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 0 | 268 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 14742102e Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2730.520 ; gain = 31.980 ; free physical = 7975 ; free virtual = 19395 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 1 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 2 Ending PowerOpt Patch Enables Task | Checksum: 14742102e Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8361 ; free virtual = 19783 Ending Power Optimization Task | Checksum: 14742102e Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2801.547 ; gain = 71.027 ; free physical = 8361 ; free virtual = 19783 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 14742102e Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8361 ; free virtual = 19783 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8361 ; free virtual = 19783 INFO: [Common 17-83] Releasing license: Implementation 47 Infos, 103 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2801.547 ; gain = 103.008 ; free physical = 8361 ; free virtual = 19783 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-83] Releasing license: Implementation WARNING: [DRC 23-814] Not all possible (connectivity based) DRCs may have been run because this design is seen as Out of Context. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Timing 38-35] Done setting XDC timing constraints. Running DRC as a precondition to command place_design WARNING: [DRC 23-814] Not all possible (connectivity based) DRCs may have been run because this design is seen as Out of Context. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8358 ; free virtual = 19780 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 143410925 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8358 ; free virtual = 19780 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8358 ; free virtual = 19780 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: e9e465c4 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8339 ; free virtual = 19760 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1a1a83479 Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8335 ; free virtual = 19756 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1a1a83479 Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8335 ; free virtual = 19756 Phase 1 Placer Initialization | Checksum: 1a1a83479 Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8335 ; free virtual = 19756 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: f169e09a Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.74 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8338 ; free virtual = 19758 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1d973b272 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8328 ; free virtual = 19750 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 1d973b272 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8328 ; free virtual = 19749 Phase 2.4 Global Place Phase1 Phase 2.4 Global Place Phase1 | Checksum: 1c0d8e67c Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8319 ; free virtual = 19741 Phase 2.5 Global Place Phase2 Phase 2.5.1 UpdateTiming Before Physical Synthesis Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 1c0d8e67c Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8319 ; free virtual = 19741 Phase 2.5.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 6 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 3 nets or LUTs. Breaked 0 LUT, combined 3 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8299 ; free virtual = 19721 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 3 | 3 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 3 | 3 | 0 | 4 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.5.2 Physical Synthesis In Placer | Checksum: 23137f15f Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8299 ; free virtual = 19721 Phase 2.5 Global Place Phase2 | Checksum: 1ab8df68b Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8304 ; free virtual = 19726 Phase 2 Global Placement | Checksum: 1ab8df68b Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8304 ; free virtual = 19726 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 204e6f997 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8304 ; free virtual = 19726 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 21469b9ea Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8304 ; free virtual = 19726 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23ceb12bb Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8304 ; free virtual = 19726 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 271cf7087 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8304 ; free virtual = 19726 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 2476b5284 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8296 ; free virtual = 19718 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 25222015c Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8296 ; free virtual = 19718 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 245ffad9f Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8296 ; free virtual = 19718 Phase 3 Detail Placement | Checksum: 245ffad9f Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8296 ; free virtual = 19718 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 280aa87be Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.017 | TNS=-0.816 | Phase 1 Physical Synthesis Initialization | Checksum: f7d076af Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8295 ; free virtual = 19715 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 19741dcc4 Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8295 ; free virtual = 19715 Phase 4.1.1.1 BUFG Insertion | Checksum: 280aa87be Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8295 ; free virtual = 19715 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=0.230. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 26e37527d Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8251 ; free virtual = 19684 Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8251 ; free virtual = 19684 Phase 4.1 Post Commit Optimization | Checksum: 26e37527d Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8251 ; free virtual = 19684 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 26e37527d Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8251 ; free virtual = 19684 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 2x2| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 26e37527d Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8251 ; free virtual = 19684 Phase 4.3 Placer Reporting | Checksum: 26e37527d Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8251 ; free virtual = 19684 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8251 ; free virtual = 19684 Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8251 ; free virtual = 19684 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2a21fb659 Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8251 ; free virtual = 19684 Ending Placer Task | Checksum: 1a5b33734 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8251 ; free virtual = 19684 73 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8251 ; free virtual = 19683 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7s50' Starting Routing Task Phase 1 Build RT Design Checksum: PlaceDB: c0d3e27f ConstDB: 0 ShapeSum: 3a4e217f RouteDB: aa913336 WARNING: [Route 35-197] Clock port "clk" does not have an associated HD.CLK_SRC. Without this constraint, timing analysis may not be accurate and upstream checks cannot be done to ensure correct clock placement. WARNING: [Route 35-198] Port "rst" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "rst". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[43]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[43]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[43]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[43]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[35]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[35]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[40]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[40]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[39]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[39]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[38]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[38]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[37]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[37]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[36]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[36]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[42]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[42]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[41]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[41]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[40]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[40]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[41]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[41]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[42]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[42]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[39]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[39]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[38]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[38]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[37]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[37]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[36]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[36]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[35]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[35]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[34]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[34]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[33]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[33]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[32]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[32]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[31]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[31]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[30]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[30]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[29]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[29]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[28]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[28]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[27]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[27]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[34]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[34]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[33]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[33]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[32]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[32]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[30]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[30]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[28]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[28]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[26]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[26]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[24]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[24]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[31]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[31]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[29]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[29]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[27]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[27]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[25]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[25]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[23]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[23]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[22]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[22]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[21]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[21]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "in_valid_i" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "in_valid_i". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[23]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[23]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[21]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[21]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[19]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[19]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[20]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[20]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[18]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[18]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[17]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[17]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[15]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[15]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[12]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[12]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[24]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[24]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[22]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[22]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[20]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[20]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[18]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[18]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[19]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[19]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[16]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[16]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[26]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[26]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[25]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[25]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[11]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[11]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[16]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[16]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[8]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[8]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[7]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[7]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[5]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[5]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[13]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[13]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[9]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[9]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[15]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[15]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[14]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[14]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[13]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[13]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[12]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[12]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[17]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[17]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[14]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[14]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[11]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[11]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[9]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[9]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[8]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[8]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[6]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[6]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[3]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[3]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[7]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[7]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[6]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[6]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[5]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[5]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[3]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[3]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Constraints 18-8777] Unable to split tiles. All required files are not available. Post Restoration Checksum: NetGraph: 4664a000 | NumContArr: 53fceee9 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 21fb38423 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8192 ; free virtual = 19625 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 21fb38423 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8192 ; free virtual = 19625 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 21fb38423 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8192 ; free virtual = 19625 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 2d0b4acd4 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8195 ; free virtual = 19628 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.230 | TNS=0.000 | WHS=0.151 | THS=0.000 | Phase 2.4 Soft Constraint Pins - Fast Budgeting Phase 2.4 Soft Constraint Pins - Fast Budgeting | Checksum: 28fd0ee58 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8183 ; free virtual = 19616 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 851 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 851 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 2 Router Initialization | Checksum: 28fd0ee58 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8183 ; free virtual = 19616 Phase 3 Global Routing Phase 3 Global Routing | Checksum: 28fd0ee58 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8183 ; free virtual = 19616 Phase 4 Initial Routing Phase 4.1 Initial Net Routing Pass Phase 4.1 Initial Net Routing Pass | Checksum: 2484fd88a Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8183 ; free virtual = 19616 Phase 4 Initial Routing | Checksum: 2484fd88a Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8183 ; free virtual = 19616 Phase 5 Rip-up And Reroute Phase 5.1 Global Iteration 0 Number of Nodes with overlaps = 35 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.163 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 5.1 Global Iteration 0 | Checksum: 12666e903 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8182 ; free virtual = 19615 Phase 5 Rip-up And Reroute | Checksum: 12666e903 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8182 ; free virtual = 19615 Phase 6 Delay and Skew Optimization Phase 6.1 Delay CleanUp Phase 6.1 Delay CleanUp | Checksum: 12666e903 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8182 ; free virtual = 19615 Phase 6.2 Clock Skew Optimization Phase 6.2 Clock Skew Optimization | Checksum: 12666e903 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8182 ; free virtual = 19615 Phase 6 Delay and Skew Optimization | Checksum: 12666e903 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8182 ; free virtual = 19615 Phase 7 Post Hold Fix Phase 7.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.163 | TNS=0.000 | WHS=0.131 | THS=0.000 | Phase 7.1 Hold Fix Iter | Checksum: 1fb0f9904 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8182 ; free virtual = 19615 Phase 7 Post Hold Fix | Checksum: 1fb0f9904 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8182 ; free virtual = 19615 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.168221 % Global Horizontal Routing Utilization = 0.161504 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 8 Route finalize | Checksum: 1fb0f9904 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8182 ; free virtual = 19615 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 1fb0f9904 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8182 ; free virtual = 19615 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 1d10ed33e Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8182 ; free virtual = 19615 Phase 11 Post Process Routing Phase 11 Post Process Routing | Checksum: 1d10ed33e Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8182 ; free virtual = 19615 Phase 12 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=0.163 | TNS=0.000 | WHS=0.131 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 12 Post Router Timing | Checksum: 1d10ed33e Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8182 ; free virtual = 19615 Total Elapsed time in route_design: 16.92 secs Phase 13 Post-Route Event Processing Phase 13 Post-Route Event Processing | Checksum: 12980dd01 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8182 ; free virtual = 19615 INFO: [Route 35-16] Router Completed Successfully Ending Routing Task | Checksum: 12980dd01 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8182 ; free virtual = 19615 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 81 Infos, 197 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8182 ; free virtual = 19615 INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8157 ; free virtual = 19591 Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8157 ; free virtual = 19591 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8157 ; free virtual = 19591 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8157 ; free virtual = 19591 Wrote PlaceStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8154 ; free virtual = 19588 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8154 ; free virtual = 19588 Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8154 ; free virtual = 19589 Write Physdb Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2801.547 ; gain = 0.000 ; free physical = 8154 ; free virtual = 19589 INFO: [Common 17-1381] The checkpoint '/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m35_large_p3/post_route.dcp' has been generated. INFO: [Common 17-206] Exiting Vivado at Sun May 24 15:26:10 2026... $ /mnt/storage/xilinx/2025.2.1/Vivado/bin/vivado -mode batch -nojournal -nolog -notrace -source /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m35_large_p3/vivado.tcl [exit code 0]