/----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3) -- Executing script file `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/yosys.ys' -- 1. Executing Verilog-2005 frontend: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v Parsing SystemVerilog input from `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v' to AST representation. Generating RTLIL representation for module `\FpxxMul'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/top_tommath_mul_e8_m17_round_even_p2.v Parsing SystemVerilog input from `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/top_tommath_mul_e8_m17_round_even_p2.v' to AST representation. Generating RTLIL representation for module `\top_tommath_mul_e8_m17_round_even_p2'. Successfully finished Verilog frontend. 3. Executing SYNTH_LATTICE pass. 3.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\VLO'. Generating RTLIL representation for module `\VHI'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\DP16KD'. Replacing existing blackbox module `\FD1P3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:2.1-2.261. Generating RTLIL representation for module `\FD1P3AX'. Replacing existing blackbox module `\FD1P3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:3.1-3.261. Generating RTLIL representation for module `\FD1P3AY'. Replacing existing blackbox module `\FD1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:4.1-4.261. Generating RTLIL representation for module `\FD1P3BX'. Replacing existing blackbox module `\FD1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:5.1-5.261. Generating RTLIL representation for module `\FD1P3DX'. Replacing existing blackbox module `\FD1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:6.1-6.261. Generating RTLIL representation for module `\FD1P3IX'. Replacing existing blackbox module `\FD1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:7.1-7.261. Generating RTLIL representation for module `\FD1P3JX'. Replacing existing blackbox module `\FD1S3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:8.1-8.261. Generating RTLIL representation for module `\FD1S3AX'. Replacing existing blackbox module `\FD1S3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:9.1-9.261. Generating RTLIL representation for module `\FD1S3AY'. Replacing existing blackbox module `\FD1S3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:10.1-10.261. Generating RTLIL representation for module `\FD1S3BX'. Replacing existing blackbox module `\FD1S3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:11.1-11.261. Generating RTLIL representation for module `\FD1S3DX'. Replacing existing blackbox module `\FD1S3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:12.1-12.261. Generating RTLIL representation for module `\FD1S3IX'. Replacing existing blackbox module `\FD1S3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:13.1-13.261. Generating RTLIL representation for module `\FD1S3JX'. Replacing existing blackbox module `\IFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:26.1-26.301. Generating RTLIL representation for module `\IFS1P3BX'. Replacing existing blackbox module `\IFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:27.1-27.301. Generating RTLIL representation for module `\IFS1P3DX'. Replacing existing blackbox module `\IFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:28.1-28.301. Generating RTLIL representation for module `\IFS1P3IX'. Replacing existing blackbox module `\IFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:29.1-29.301. Generating RTLIL representation for module `\IFS1P3JX'. Replacing existing blackbox module `\OFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:31.1-31.302. Generating RTLIL representation for module `\OFS1P3BX'. Replacing existing blackbox module `\OFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:32.1-32.302. Generating RTLIL representation for module `\OFS1P3DX'. Replacing existing blackbox module `\OFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:33.1-33.302. Generating RTLIL representation for module `\OFS1P3IX'. Replacing existing blackbox module `\OFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:34.1-34.302. Generating RTLIL representation for module `\OFS1P3JX'. Replacing existing blackbox module `\IB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:2.1-2.157. Generating RTLIL representation for module `\IB'. Replacing existing blackbox module `\IBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:3.1-3.157. Generating RTLIL representation for module `\IBPU'. Replacing existing blackbox module `\IBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:4.1-4.157. Generating RTLIL representation for module `\IBPD'. Replacing existing blackbox module `\OB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:5.1-5.157. Generating RTLIL representation for module `\OB'. Replacing existing blackbox module `\OBZ' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:6.1-6.164. Generating RTLIL representation for module `\OBZ'. Replacing existing blackbox module `\OBZPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:7.1-7.164. Generating RTLIL representation for module `\OBZPU'. Replacing existing blackbox module `\OBZPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:8.1-8.164. Generating RTLIL representation for module `\OBZPD'. Replacing existing blackbox module `\OBCO' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:9.1-9.90. Generating RTLIL representation for module `\OBCO'. Replacing existing blackbox module `\BB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:10.1-10.179. Generating RTLIL representation for module `\BB'. Replacing existing blackbox module `\BBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:11.1-11.179. Generating RTLIL representation for module `\BBPU'. Replacing existing blackbox module `\BBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:12.1-12.179. Generating RTLIL representation for module `\BBPD'. Replacing existing blackbox module `\ILVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:13.1-13.139. Generating RTLIL representation for module `\ILVDS'. Replacing existing blackbox module `\OLVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:14.1-14.146. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 3.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DCUA'. Successfully finished Verilog frontend. 3.3. Executing HIERARCHY pass (managing design hierarchy). 3.3.1. Analyzing design hierarchy.. Top module: \top_tommath_mul_e8_m17_round_even_p2 Used module: \FpxxMul 3.3.2. Analyzing design hierarchy.. Top module: \top_tommath_mul_e8_m17_round_even_p2 Used module: \FpxxMul Removed 0 unused modules. 3.4. Executing PROC pass (convert processes to netlists). 3.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/top_tommath_mul_e8_m17_round_even_p2.v:43$68 in module top_tommath_mul_e8_m17_round_even_p2. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:188$66 in module FpxxMul. Marked 4 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:163$62 in module FpxxMul. Marked 4 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:143$61 in module FpxxMul. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:132$58 in module FpxxMul. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:124$56 in module FpxxMul. Removed a total of 0 dead cases. 3.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 4 redundant assignments. Promoted 25 assignments to connections. 3.4.4. Executing PROC_INIT pass (extract init attributes). 3.4.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \reset in `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:188$66'. 3.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\top_tommath_mul_e8_m17_round_even_p2.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/top_tommath_mul_e8_m17_round_even_p2.v:43$68'. 1/2: $0\out_valid_r[0:0] 2/2: $0\in_valid_r[0:0] Creating decoders for process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. Creating decoders for process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:188$66'. 1/2: $0\n2_valid[0:0] 2/2: $0\n1_valid[0:0] Creating decoders for process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:163$62'. 1/4: $4\io_result_payload_mant[16:0] 2/4: $3\io_result_payload_mant[16:0] 3/4: $2\io_result_payload_mant[16:0] 4/4: $1\io_result_payload_mant[16:0] Creating decoders for process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:143$61'. 1/4: $4\io_result_payload_exp[7:0] 2/4: $3\io_result_payload_exp[7:0] 3/4: $2\io_result_payload_exp[7:0] 4/4: $1\io_result_payload_exp[7:0] Creating decoders for process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:132$58'. 1/1: $1\_zz_n2_mant_mul_rounded[17:0] Creating decoders for process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:124$56'. 1/1: $1\_zz_n2_mant_mul_rounded_1[17:0] 3.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `\FpxxMul.\io_result_payload_mant' from process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:163$62'. No latch inferred for signal `\FpxxMul.\io_result_payload_exp' from process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:143$61'. No latch inferred for signal `\FpxxMul.\_zz_n2_mant_mul_rounded' from process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:132$58'. No latch inferred for signal `\FpxxMul.\_zz_n2_mant_mul_rounded_1' from process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:124$56'. 3.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\top_tommath_mul_e8_m17_round_even_p2.\a_r' using process `\top_tommath_mul_e8_m17_round_even_p2.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/top_tommath_mul_e8_m17_round_even_p2.v:43$68'. created $dff cell `$procdff$366' with positive edge clock. Creating register for signal `\top_tommath_mul_e8_m17_round_even_p2.\b_r' using process `\top_tommath_mul_e8_m17_round_even_p2.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/top_tommath_mul_e8_m17_round_even_p2.v:43$68'. created $dff cell `$procdff$367' with positive edge clock. Creating register for signal `\top_tommath_mul_e8_m17_round_even_p2.\in_valid_r' using process `\top_tommath_mul_e8_m17_round_even_p2.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/top_tommath_mul_e8_m17_round_even_p2.v:43$68'. created $dff cell `$procdff$368' with positive edge clock. Creating register for signal `\top_tommath_mul_e8_m17_round_even_p2.\y_r' using process `\top_tommath_mul_e8_m17_round_even_p2.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/top_tommath_mul_e8_m17_round_even_p2.v:43$68'. created $dff cell `$procdff$369' with positive edge clock. Creating register for signal `\top_tommath_mul_e8_m17_round_even_p2.\out_valid_r' using process `\top_tommath_mul_e8_m17_round_even_p2.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/top_tommath_mul_e8_m17_round_even_p2.v:43$68'. created $dff cell `$procdff$370' with positive edge clock. Creating register for signal `\FpxxMul.\n1_n0_sign_mul' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$371' with positive edge clock. Creating register for signal `\FpxxMul.\n1_n0_is_zero' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$372' with positive edge clock. Creating register for signal `\FpxxMul.\n1_n0_is_inf' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$373' with positive edge clock. Creating register for signal `\FpxxMul.\n1_n0_is_nan' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$374' with positive edge clock. Creating register for signal `\FpxxMul.\n2_n0_is_zero' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$375' with positive edge clock. Creating register for signal `\FpxxMul.\n2_n0_is_inf' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$376' with positive edge clock. Creating register for signal `\FpxxMul.\n2_n0_is_nan' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$377' with positive edge clock. Creating register for signal `\FpxxMul.\n2_n0_sign_mul' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$378' with positive edge clock. Creating register for signal `\FpxxMul.\n2_n1_exp_mul' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$379' with positive edge clock. Creating register for signal `\FpxxMul.\n2_n1_mant_mul' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$380' with positive edge clock. Creating register for signal `\FpxxMul.\n1_n0_mant_b' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$381' with positive edge clock. Creating register for signal `\FpxxMul.\n1_n0_mant_a' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$382' with positive edge clock. Creating register for signal `\FpxxMul.\n1_n0_b_mant' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$383' with positive edge clock. Creating register for signal `\FpxxMul.\n1_n0_b_exp' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$384' with positive edge clock. Creating register for signal `\FpxxMul.\n1_n0_b_sign' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$385' with positive edge clock. Creating register for signal `\FpxxMul.\n1_n0_a_mant' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$386' with positive edge clock. Creating register for signal `\FpxxMul.\n1_n0_a_exp' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$387' with positive edge clock. Creating register for signal `\FpxxMul.\n1_n0_a_sign' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. created $dff cell `$procdff$388' with positive edge clock. Creating register for signal `\FpxxMul.\n2_valid' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:188$66'. created $adff cell `$procdff$391' with positive edge clock and positive level reset. Creating register for signal `\FpxxMul.\n1_valid' using process `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:188$66'. created $adff cell `$procdff$394' with positive edge clock and positive level reset. 3.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\top_tommath_mul_e8_m17_round_even_p2.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/top_tommath_mul_e8_m17_round_even_p2.v:43$68'. Removing empty process `top_tommath_mul_e8_m17_round_even_p2.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/top_tommath_mul_e8_m17_round_even_p2.v:43$68'. Removing empty process `FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:198$67'. Removing empty process `FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:188$66'. Found and cleaned up 4 empty switches in `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:163$62'. Removing empty process `FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:163$62'. Found and cleaned up 4 empty switches in `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:143$61'. Removing empty process `FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:143$61'. Found and cleaned up 1 empty switch in `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:132$58'. Removing empty process `FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:132$58'. Found and cleaned up 1 empty switch in `\FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:124$56'. Removing empty process `FpxxMul.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:124$56'. Cleaned up 11 empty switches. 3.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_mul_e8_m17_round_even_p2. Optimizing module FpxxMul. 3.5. Executing CHECK pass (checking for obvious problems). Checking module top_tommath_mul_e8_m17_round_even_p2... Checking module FpxxMul... Found and reported 0 problems. 3.6. Executing FLATTEN pass (flatten design). Keeping top_tommath_mul_e8_m17_round_even_p2.u_dut (found keep_hierarchy attribute). 3.7. Executing TRIBUF pass. 3.8. Executing DEMINOUT pass (demote inout ports to input or output). 3.9. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_mul_e8_m17_round_even_p2. Optimizing module FpxxMul. 3.10. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. Removed 5 unused cells and 93 unused wires. 3.11. Executing CHECK pass (checking for obvious problems). Checking module top_tommath_mul_e8_m17_round_even_p2... Checking module FpxxMul... Found and reported 0 problems. 3.12. Executing OPT pass (performing simple optimizations). 3.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_mul_e8_m17_round_even_p2. Optimizing module FpxxMul. 3.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_mul_e8_m17_round_even_p2'. Computing hashes of 8 cells of `\top_tommath_mul_e8_m17_round_even_p2'. Finding duplicate cells in `\top_tommath_mul_e8_m17_round_even_p2'. Finding identical cells in module `\FpxxMul'. Computing hashes of 97 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Computing hashes of 83 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Computing hashes of 79 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Computing hashes of 77 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Removed a total of 20 cells. 3.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_mul_e8_m17_round_even_p2.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \FpxxMul.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port A of cell $procmux$364: { 1'0 \_zz_n2_mant_mul_adj [34:18] } -> { 1'0 \_zz_n2_mant_mul_adj [34:19] 1'0 } Analyzing evaluation results. dead port 1/2 on $mux $procmux$346. dead port 1/2 on $mux $procmux$340. dead port 1/2 on $mux $procmux$337. dead port 1/2 on $mux $procmux$334. dead port 1/2 on $mux $procmux$325. dead port 1/2 on $mux $procmux$319. dead port 1/2 on $mux $procmux$316. dead port 1/2 on $mux $procmux$310. dead port 1/2 on $mux $procmux$307. dead port 1/2 on $mux $procmux$304. dead port 1/2 on $mux $procmux$349. dead port 1/2 on $mux $procmux$355. Removed 12 multiplexer ports. 3.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_mul_e8_m17_round_even_p2. Optimizing cells in module \FpxxMul. Performed a total of 0 changes. 3.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_mul_e8_m17_round_even_p2'. Computing hashes of 8 cells of `\top_tommath_mul_e8_m17_round_even_p2'. Finding duplicate cells in `\top_tommath_mul_e8_m17_round_even_p2'. Finding identical cells in module `\FpxxMul'. Computing hashes of 65 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Removed a total of 0 cells. 3.12.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 17 on $procdff$382 ($dff) from module FpxxMul. Setting constant 1-bit at position 17 on $procdff$381 ($dff) from module FpxxMul. 3.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. Removed 0 unused cells and 32 unused wires. 3.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_mul_e8_m17_round_even_p2. Optimizing module FpxxMul. 3.12.9. Rerunning OPT passes. (Maybe there is more to do..) 3.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_mul_e8_m17_round_even_p2.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \FpxxMul.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_mul_e8_m17_round_even_p2. Optimizing cells in module \FpxxMul. Performed a total of 0 changes. 3.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_mul_e8_m17_round_even_p2'. Computing hashes of 8 cells of `\top_tommath_mul_e8_m17_round_even_p2'. Finding duplicate cells in `\top_tommath_mul_e8_m17_round_even_p2'. Finding identical cells in module `\FpxxMul'. Computing hashes of 65 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Removed a total of 0 cells. 3.12.13. Executing OPT_DFF pass (perform DFF optimizations). 3.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. 3.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_mul_e8_m17_round_even_p2. Optimizing module FpxxMul. 3.12.16. Finished fast OPT passes. (There is nothing left to do.) 3.13. Executing FSM pass (extract and optimize FSM). 3.13.1. Executing FSM_DETECT pass (finding FSMs in design). 3.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). 3.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). 3.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. 3.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). 3.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 3.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 3.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 3.14. Executing OPT pass (performing simple optimizations). 3.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_mul_e8_m17_round_even_p2. Optimizing module FpxxMul. 3.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_mul_e8_m17_round_even_p2'. Computing hashes of 8 cells of `\top_tommath_mul_e8_m17_round_even_p2'. Finding duplicate cells in `\top_tommath_mul_e8_m17_round_even_p2'. Finding identical cells in module `\FpxxMul'. Computing hashes of 65 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Removed a total of 0 cells. 3.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_mul_e8_m17_round_even_p2.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \FpxxMul.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_mul_e8_m17_round_even_p2. Optimizing cells in module \FpxxMul. Performed a total of 0 changes. 3.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_mul_e8_m17_round_even_p2'. Computing hashes of 8 cells of `\top_tommath_mul_e8_m17_round_even_p2'. Finding duplicate cells in `\top_tommath_mul_e8_m17_round_even_p2'. Finding identical cells in module `\FpxxMul'. Computing hashes of 65 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Removed a total of 0 cells. 3.14.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $procdff$368 ($dff) from module top_tommath_mul_e8_m17_round_even_p2 (D = \in_valid_i, Q = \in_valid_r, rval = 1'0). Adding SRST signal on $procdff$370 ($dff) from module top_tommath_mul_e8_m17_round_even_p2 (D = \dut_valid, Q = \out_valid_r, rval = 1'0). 3.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. Removed 2 unused cells and 2 unused wires. 3.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_mul_e8_m17_round_even_p2. Optimizing module FpxxMul. 3.14.9. Rerunning OPT passes. (Maybe there is more to do..) 3.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_mul_e8_m17_round_even_p2.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \FpxxMul.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_mul_e8_m17_round_even_p2. Optimizing cells in module \FpxxMul. Performed a total of 0 changes. 3.14.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_mul_e8_m17_round_even_p2'. Computing hashes of 6 cells of `\top_tommath_mul_e8_m17_round_even_p2'. Finding duplicate cells in `\top_tommath_mul_e8_m17_round_even_p2'. Finding identical cells in module `\FpxxMul'. Computing hashes of 65 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Removed a total of 0 cells. 3.14.13. Executing OPT_DFF pass (perform DFF optimizations). 3.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. 3.14.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_mul_e8_m17_round_even_p2. Optimizing module FpxxMul. 3.14.16. Finished fast OPT passes. (There is nothing left to do.) 3.15. Executing WREDUCE pass (reducing word size of cells). Removed top 1 bits (of 9) from port A of cell FpxxMul.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:89$1 ($add). Removed top 1 bits (of 9) from port B of cell FpxxMul.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:89$1 ($add). Removed top 2 bits (of 37) from port Y of cell FpxxMul.$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:90$2 ($sshr). Removed top 1 bits (of 19) from port A of cell FpxxMul.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:93$3 ($add). Removed top 18 bits (of 19) from port B of cell FpxxMul.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:93$3 ($add). Removed top 8 bits (of 10) from port B of cell FpxxMul.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:94$4 ($add). Removed top 2 bits (of 10) from port B of cell FpxxMul.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:118$51 ($sub). Converting cell FpxxMul.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:118$51 ($sub) from signed to unsigned. Removed top 1 bits (of 10) from port A of cell FpxxMul.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:118$51 ($sub). Removed top 1 bits (of 8) from port B of cell FpxxMul.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:118$51 ($sub). Removed top 1 bits (of 18) from port A of cell FpxxMul.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:126$57 ($add). Removed top 17 bits (of 18) from port B of cell FpxxMul.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:126$57 ($add). Removed top 8 bits (of 10) from port B of cell FpxxMul.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:141$60 ($add). Removed top 9 bits (of 10) from port B of cell FpxxMul.$le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:183$63 ($le). Removed top 1 bits (of 10) from port A of cell FpxxMul.$le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:184$65 ($le). Removed top 1 bits (of 18) from wire FpxxMul.n1_n0_mant_a. Removed top 1 bits (of 18) from wire FpxxMul.n1_n0_mant_b. Removed top 1 bits (of 2) from wire FpxxMul._zz_n2_exp_mul_adj_4. Removed top 9 bits (of 10) from wire FpxxMul._zz_n2_exp_mul_adj_3. Removed top 1 bits (of 2) from wire FpxxMul._zz_n2_exp_mul_adj_2. Removed top 9 bits (of 10) from wire FpxxMul._zz_n2_exp_mul_adj_1. 3.16. Executing PEEPOPT pass (run peephole optimizers). 3.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. Removed 0 unused cells and 6 unused wires. 3.18. Executing SHARE pass (SAT-based resource sharing). 3.19. Executing TECHMAP pass (map to technology primitives). 3.19.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 3.19.2. Continuing TECHMAP pass. No more expansions possible. 3.20. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_mul_e8_m17_round_even_p2. Optimizing module FpxxMul. 3.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. 3.22. Executing TECHMAP pass (map to technology primitives). 3.22.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 3.22.2. Continuing TECHMAP pass. Using template $paramod$55e849a2191f17b159b997340cb0ebb72d635590\_80_mul for cells of type $mul. No more expansions possible. 3.23. Executing TECHMAP pass (map to technology primitives). 3.23.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. Generating RTLIL representation for module `$__MUL18X18'. Successfully finished Verilog frontend. 3.23.2. Continuing TECHMAP pass. Using template $paramod$6d12bf30e693aad43884066ff41c02c3d61c4f33$__MUL18X18 for cells of type $__MUL18X18. No more expansions possible. 3.24. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top_tommath_mul_e8_m17_round_even_p2: created 0 $alu and 0 $macc cells. Extracting $alu and $macc cells in module FpxxMul: creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:141$60 ($add). creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:126$57 ($add). creating $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:118$51 ($sub). creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:94$4 ($add). creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:93$3 ($add). creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:89$1 ($add). merging $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:89$1 into $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:118$51. merging $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:94$4 into $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:141$60. creating $alu model for $macc $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:93$3. creating $alu model for $macc $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:126$57. creating $macc cell for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:118$51: $auto$alumacc.cc:382:replace_macc$408 creating $macc cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:141$60: $auto$alumacc.cc:382:replace_macc$409 creating $alu model for $le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:184$65 ($le): new $alu creating $alu model for $le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:183$63 ($le): new $alu creating $alu cell for $le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:183$63: $auto$alumacc.cc:512:replace_alu$412 creating $alu cell for $le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:184$65: $auto$alumacc.cc:512:replace_alu$423 creating $alu cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:126$57: $auto$alumacc.cc:512:replace_alu$434 creating $alu cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/src/tommath_mul_e8_m17_round_even_p2.v:93$3: $auto$alumacc.cc:512:replace_alu$437 created 4 $alu and 2 $macc cells. 3.25. Executing OPT pass (performing simple optimizations). 3.25.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_mul_e8_m17_round_even_p2. Optimizing module FpxxMul. 3.25.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_mul_e8_m17_round_even_p2'. Computing hashes of 6 cells of `\top_tommath_mul_e8_m17_round_even_p2'. Finding duplicate cells in `\top_tommath_mul_e8_m17_round_even_p2'. Finding identical cells in module `\FpxxMul'. Computing hashes of 72 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Removed a total of 0 cells. 3.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_mul_e8_m17_round_even_p2.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \FpxxMul.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_mul_e8_m17_round_even_p2. Optimizing cells in module \FpxxMul. Performed a total of 0 changes. 3.25.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_mul_e8_m17_round_even_p2'. Computing hashes of 6 cells of `\top_tommath_mul_e8_m17_round_even_p2'. Finding duplicate cells in `\top_tommath_mul_e8_m17_round_even_p2'. Finding identical cells in module `\FpxxMul'. Computing hashes of 72 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Removed a total of 0 cells. 3.25.6. Executing OPT_DFF pass (perform DFF optimizations). 3.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. Removed 2 unused cells and 17 unused wires. 3.25.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_mul_e8_m17_round_even_p2. Optimizing module FpxxMul. 3.25.9. Rerunning OPT passes. (Maybe there is more to do..) 3.25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_mul_e8_m17_round_even_p2.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \FpxxMul.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_mul_e8_m17_round_even_p2. Optimizing cells in module \FpxxMul. Performed a total of 0 changes. 3.25.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_mul_e8_m17_round_even_p2'. Computing hashes of 6 cells of `\top_tommath_mul_e8_m17_round_even_p2'. Finding duplicate cells in `\top_tommath_mul_e8_m17_round_even_p2'. Finding identical cells in module `\FpxxMul'. Computing hashes of 69 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Removed a total of 0 cells. 3.25.13. Executing OPT_DFF pass (perform DFF optimizations). 3.25.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. 3.25.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_mul_e8_m17_round_even_p2. Optimizing module FpxxMul. 3.25.16. Finished fast OPT passes. (There is nothing left to do.) 3.26. Executing MEMORY pass. 3.26.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 3.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 3.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 3.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 3.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 3.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. 3.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 3.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 3.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. 3.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). 3.27. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. 3.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). 3.29. Executing TECHMAP pass (map to technology primitives). 3.29.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 3.29.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v' to AST representation. Generating RTLIL representation for module `$__DP16KD_'. Generating RTLIL representation for module `$__PDPW16KD_'. Successfully finished Verilog frontend. 3.29.3. Continuing TECHMAP pass. No more expansions possible. 3.30. Executing OPT pass (performing simple optimizations). 3.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_mul_e8_m17_round_even_p2. Optimizing module FpxxMul. 3.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_mul_e8_m17_round_even_p2'. Computing hashes of 6 cells of `\top_tommath_mul_e8_m17_round_even_p2'. Finding duplicate cells in `\top_tommath_mul_e8_m17_round_even_p2'. Finding identical cells in module `\FpxxMul'. Computing hashes of 77 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Removed a total of 0 cells. 3.30.3. Executing OPT_DFF pass (perform DFF optimizations). 3.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. Removed 8 unused cells and 8 unused wires. 3.30.5. Finished fast OPT passes. 3.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 3.32. Executing OPT pass (performing simple optimizations). 3.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_mul_e8_m17_round_even_p2. Optimizing module FpxxMul. 3.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_mul_e8_m17_round_even_p2'. Computing hashes of 6 cells of `\top_tommath_mul_e8_m17_round_even_p2'. Finding duplicate cells in `\top_tommath_mul_e8_m17_round_even_p2'. Finding identical cells in module `\FpxxMul'. Computing hashes of 69 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Removed a total of 0 cells. 3.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_mul_e8_m17_round_even_p2.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \FpxxMul.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_mul_e8_m17_round_even_p2. Optimizing cells in module \FpxxMul. Performed a total of 0 changes. 3.32.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_mul_e8_m17_round_even_p2'. Computing hashes of 6 cells of `\top_tommath_mul_e8_m17_round_even_p2'. Finding duplicate cells in `\top_tommath_mul_e8_m17_round_even_p2'. Finding identical cells in module `\FpxxMul'. Computing hashes of 69 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Removed a total of 0 cells. 3.32.6. Executing OPT_DFF pass (perform DFF optimizations). 3.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. 3.32.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_mul_e8_m17_round_even_p2. Optimizing module FpxxMul. 3.32.9. Finished fast OPT passes. (There is nothing left to do.) 3.33. Executing TECHMAP pass (map to technology primitives). 3.33.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 3.33.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. Generating RTLIL representation for module `\_80_ccu2c_alu'. Successfully finished Verilog frontend. 3.33.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $not. Using template $paramod$constmap:79a805d20c43b9e16d7c0dfdc6321678e28f9621$paramod$dc07ff74567e35dae47ab35a494a74afb95459eb\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr. Using template $paramod$5149e1e231cbdcfb7362de2a8603e2def0b11576\_80_ccu2c_alu for cells of type $alu. Using template $paramod$4a5474979e92ac299b9d7366adf0780f6b2e4f28\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $xor. Using template $paramod$0cf90cc92a8a726f7480da3c1dd521ff92701be4\_90_alu for cells of type $alu. Using extmapper maccmap for cells of type $macc_v2. add \n2_n1_exp_mul (10 bits, signed) add { 1'0 \_zz_n2_mant_mul_rounded [17] } (2 bits, signed) add { 1'0 \n2_n1_mant_mul [35] } (2 bits, signed) packed 1 (1) bits / 1 words into adder tree add \n1_n0_a_exp (8 bits, unsigned) add \n1_n0_b_exp (8 bits, unsigned) add 10'1110000001 (10 bits, unsigned) Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $logic_or. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $adff. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000001010 for cells of type $fa. Using template $paramod$484d51534650924b7ed4c69e46eed3a56904771f\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $sdff. No more expansions possible. 3.34. Executing OPT pass (performing simple optimizations). 3.34.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_mul_e8_m17_round_even_p2. Optimizing module FpxxMul. 3.34.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_mul_e8_m17_round_even_p2'. Computing hashes of 81 cells of `\top_tommath_mul_e8_m17_round_even_p2'. Finding duplicate cells in `\top_tommath_mul_e8_m17_round_even_p2'. Finding identical cells in module `\FpxxMul'. Computing hashes of 587 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Computing hashes of 548 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Computing hashes of 539 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Computing hashes of 535 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Computing hashes of 533 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Computing hashes of 531 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Computing hashes of 529 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Removed a total of 58 cells. 3.34.3. Executing OPT_DFF pass (perform DFF optimizations). 3.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. Removed 72 unused cells and 281 unused wires. 3.34.5. Finished fast OPT passes. 3.35. Executing ABC pass (technology mapping using ABC). 3.35.1. Summary of detected clock domains: 3 cells in clk=\clk, en={ }, arst={ }, srst=\rst 78 cells in clk=\clk, en={ }, arst={ }, srst={ } 3.35.2. Extracting gate netlist of module `\top_tommath_mul_e8_m17_round_even_p2' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by \rst 3.35.3. Extracting gate netlist of module `\top_tommath_mul_e8_m17_round_even_p2' to `/input.blif'.. Found matching posedge clock domain: \clk 3.35.3.1. Executed ABC. Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 2 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.3.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 4 ABC RESULTS: DFF cells: 2 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 2 ABC RESULTS: output signals: 2 Removing temp directory. 3.35.3.1. Executed ABC. Extracted 78 gates and 156 wires to a netlist network with 78 inputs and 78 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 78 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.3.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 156 ABC RESULTS: DFF cells: 78 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 78 ABC RESULTS: output signals: 78 Removing temp directory. 3.35.4. Summary of detected clock domains: 2 cells in clk=\clk, en={ }, arst=\reset, srst={ } 455 cells in clk=\clk, en={ }, arst={ }, srst={ } 3.35.5. Extracting gate netlist of module `\FpxxMul' to `/input.blif'.. Found matching posedge clock domain: \clk, asynchronously reset by \reset 3.35.6. Extracting gate netlist of module `\FpxxMul' to `/input.blif'.. Found matching posedge clock domain: \clk 3.35.6.1. Executed ABC. Extracted 2 gates and 3 wires to a netlist network with 1 inputs and 1 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.6.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 3 ABC RESULTS: DFF cells: 2 ABC RESULTS: internal signals: 1 ABC RESULTS: input signals: 1 ABC RESULTS: output signals: 1 Removing temp directory. 3.35.6.1. Executed ABC. Extracted 425 gates and 571 wires to a netlist network with 144 inputs and 106 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 104 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: Abc_NtkRetimeInitialValues(): The problem is unsatisfiable. DC latch values are used. ABC: + strash ABC: + &get -n ABC: Warning: 85 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.6.2. Re-integrating ABC results. ABC RESULTS: AND cells: 81 ABC RESULTS: ANDNOT cells: 4 ABC RESULTS: BUF cells: 126 ABC RESULTS: DFF cells: 85 ABC RESULTS: MUX cells: 51 ABC RESULTS: NAND cells: 19 ABC RESULTS: NOR cells: 40 ABC RESULTS: OR cells: 30 ABC RESULTS: ORNOT cells: 1 ABC RESULTS: XNOR cells: 2 ABC RESULTS: XOR cells: 7 ABC RESULTS: internal signals: 321 ABC RESULTS: input signals: 144 ABC RESULTS: output signals: 106 Removing temp directory. Removing global temp directory. 3.36. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. Removed 0 unused cells and 786 unused wires. 3.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 3.38. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_mul_e8_m17_round_even_p2'. Computing hashes of 81 cells of `\top_tommath_mul_e8_m17_round_even_p2'. Finding duplicate cells in `\top_tommath_mul_e8_m17_round_even_p2'. Finding identical cells in module `\FpxxMul'. Computing hashes of 352 cells of `\FpxxMul'. Finding duplicate cells in `\FpxxMul'. Removed a total of 0 cells. 3.39. Executing TECHMAP pass (map to technology primitives). 3.39.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 3.39.2. Continuing TECHMAP pass. Using template $_DFF_PP0_ for cells of type $_DFF_PP0_. Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. No more expansions possible. 3.40. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_mul_e8_m17_round_even_p2. Optimizing module FpxxMul. 3.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). 3.42. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in top_tommath_mul_e8_m17_round_even_p2. Handling GSR in FpxxMul. 3.43. Executing ATTRMVCP pass (move or copy attributes). 3.44. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_mul_e8_m17_round_even_p2.. Finding unused cells or wires in module \FpxxMul.. Removed 0 unused cells and 672 unused wires. 3.45. Executing ABC pass (technology mapping using ABC). 3.45.1. Extracting gate netlist of module `\top_tommath_mul_e8_m17_round_even_p2' to `/input.blif'.. 3.45.1.1. Executed ABC. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 3.45.2. Extracting gate netlist of module `\FpxxMul' to `/input.blif'.. 3.45.2.1. Executed ABC. Extracted 235 gates and 391 wires to a netlist network with 156 inputs and 65 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.45.2.2. Re-integrating ABC results. ABC RESULTS: AND cells: 81 ABC RESULTS: ANDNOT cells: 4 ABC RESULTS: MUX cells: 51 ABC RESULTS: NAND cells: 19 ABC RESULTS: NOR cells: 40 ABC RESULTS: OR cells: 30 ABC RESULTS: ORNOT cells: 1 ABC RESULTS: XNOR cells: 2 ABC RESULTS: XOR cells: 7 ABC RESULTS: internal signals: 170 ABC RESULTS: input signals: 156 ABC RESULTS: output signals: 65 Removing temp directory. Removing global temp directory. 3.46. Executing TECHMAP pass (map to technology primitives). 3.46.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v' to AST representation. Generating RTLIL representation for module `$_DLATCH_N_'. Generating RTLIL representation for module `$_DLATCH_P_'. Successfully finished Verilog frontend. 3.46.2. Continuing TECHMAP pass. No more expansions possible. 3.47. Executing ABC pass (technology mapping using ABC). 3.47.1. Summary of detected clock domains: 81 cells in clk={ }, en={ }, arst={ }, srst={ } 3.47.2. Extracting gate netlist of module `\top_tommath_mul_e8_m17_round_even_p2' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 3.47.2.1. Executed ABC. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 3.47.3. Summary of detected clock domains: 352 cells in clk={ }, en={ }, arst={ }, srst={ } 3.47.4. Extracting gate netlist of module `\FpxxMul' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 3.47.4.1. Executed ABC. Extracted 235 gates and 391 wires to a netlist network with 156 inputs and 65 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_lut /lutdefs.txt ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + dress /input.blif ABC: Total number of equiv classes = 101. ABC: Participating nodes from both networks = 200. ABC: Participating nodes from the first network = 100. ( 85.47 % of nodes) ABC: Participating nodes from the second network = 100. ( 85.47 % of nodes) ABC: Node pairs (any polarity) = 100. ( 85.47 % of names can be moved) ABC: Node pairs (same polarity) = 81. ( 69.23 % of names can be moved) ABC: Total runtime = 0.05 sec ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.47.4.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 116 ABC RESULTS: internal signals: 170 ABC RESULTS: input signals: 156 ABC RESULTS: output signals: 65 Removing temp directory. Removing global temp directory. Removed 0 unused cells and 782 unused wires. 3.48. Executing TECHMAP pass (map to technology primitives). 3.48.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `$lut'. Successfully finished Verilog frontend. 3.48.2. Continuing TECHMAP pass. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$e4adb5a40bce606100fc00f292ff9d4f2f55953f$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912$lut for cells of type $lut. Using template $paramod$d4fae2c0d9ad2966369cd4e39b81c71bcd1327c9$lut for cells of type $lut. Using template $paramod$6d23198eb2b8f79a41c7626605a61009695893b1$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$e0bde73e598487237493c8a43ca52c95a3727354$lut for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut. Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut. Using template $paramod$d55d0bbee3cfd88a848a494f2602eefcabae2c14$lut for cells of type $lut. Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$fb5ee0bdef1c4e74aaf1fd8efae98b46a2f5e564$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. No more expansions possible. 3.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in top_tommath_mul_e8_m17_round_even_p2. Optimizing LUTs in FpxxMul. Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$2999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$2980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$2982.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$2999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$2986.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$2989.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$2990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$2993.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$2996.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$2997.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$2999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3024.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3028.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3032.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3040.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3048.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3050.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$2953$auto$blifparse.cc:557:parse_blif$3064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Removed 0 unused cells and 250 unused wires. 3.50. Executing AUTONAME pass. Renamed 80 objects in module top_tommath_mul_e8_m17_round_even_p2 (4 iterations). Renamed 431 objects in module FpxxMul (81 iterations). 3.51. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `top_tommath_mul_e8_m17_round_even_p2'. Setting top module to top_tommath_mul_e8_m17_round_even_p2. 3.51.1. Analyzing design hierarchy.. Top module: \top_tommath_mul_e8_m17_round_even_p2 Used module: \FpxxMul 3.51.2. Analyzing design hierarchy.. Top module: \top_tommath_mul_e8_m17_round_even_p2 Used module: \FpxxMul Removed 0 unused modules. 3.52. Printing statistics. === top_tommath_mul_e8_m17_round_even_p2 === +----------Local Count, excluding submodules. | 17 wires 215 wire bits 17 public wires 215 public wire bits 7 ports 82 port bits 81 submodules 1 FpxxMul 80 TRELLIS_FF === FpxxMul === +----------Local Count, excluding submodules. | 193 wires 985 wire bits 193 public wires 985 public wire bits 13 ports 82 port bits 1 cells 1 MULT18X18D 286 submodules 29 CCU2C 1 L6MUX21 143 LUT4 26 PFUMX 87 TRELLIS_FF === design hierarchy === +----------Count including submodules. | 1 top_tommath_mul_e8_m17_round_even_p2 1 FpxxMul +----------Count including submodules. | 210 wires 1200 wire bits 210 public wires 1200 public wire bits 20 ports 164 port bits - memories - memory bits - processes 1 cells 1 MULT18X18D 81 submodules 1 FpxxMul 80 TRELLIS_FF 3.53. Executing CHECK pass (checking for obvious problems). Checking module top_tommath_mul_e8_m17_round_even_p2... Checking module FpxxMul... Found and reported 0 problems. 3.54. Executing JSON backend. End of script. Logfile hash: 832d3d0d03, time: 0.86s, user: 0.50s, system: 0.05s, MEM: 37.04 MB peak Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3) Time spent: 43% 3x abc (0 sec), 31% 17x read_verilog (0 sec), ... $ yosys -s /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_mul_e8_m17_round_even_p2/yosys.ys [exit code 0]