Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved. Sat May 23 22:27:48 2026 Command Line: /usr/local/diamond/3.14/ispfpga/bin/lin64/synthesis -f /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/zkf_mul_w8_m18_base/lse.synproj INFO - synthesis: Lattice Synthesis Engine Launched. Synthesis options: The -a option is ECP5U. The -s option is 6. The -t option is CABGA381. The -d option is LFE5U-12F. Using package CABGA381. Using performance grade 6. ########################################################## ### Lattice Family : ECP5U ### Device : LFE5U-12F ### Package : CABGA381 ### Speed : 6 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Timing Top-level module name = top_zkf_mul_w8_m18_base. Target frequency = 100.000000 MHz. Maximum fanout = 1000. Timing path count = 10 BRAM utilization = 100.000000 % DSP usage = true (default) DSP utilization = 100 % (default) fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = auto Use Carry Chain = true carry_chain_length = 0 Use IO Insertion = TRUE Use IO Reg = FALSE Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = no ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p /usr/local/diamond/3.14/ispfpga/sa5p00/data (searchpath added) -p /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/zkf_mul_w8_m18_base (searchpath added) Verilog design file = /mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v Verilog design file = /mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v Verilog design file = /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/zkf_mul_w8_m18_base/src/top_zkf_mul_w8_m18_base.v NGO file = /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/zkf_mul_w8_m18_base/top_zkf_mul_w8_m18_base.ngo -sdc option: SDC file input is /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/zkf_mul_w8_m18_base/constraints.sdc. -lpf option: Output file option is not used. -vh2008 Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file /usr/local/diamond/3.14/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5u.v. VERI-1482 Compile design. Compile Design Begin Analyzing Verilog file /mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v. VERI-1482 Analyzing Verilog file /mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v. VERI-1482 Analyzing Verilog file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/zkf_mul_w8_m18_base/src/top_zkf_mul_w8_m18_base.v. VERI-1482 Analyzing Verilog file /usr/local/diamond/3.14/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5u.v. VERI-1482 Top module name (Verilog): top_zkf_mul_w8_m18_base INFO - synthesis: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/zkf_mul_w8_m18_base/src/top_zkf_mul_w8_m18_base.v(4): compiling module top_zkf_mul_w8_m18_base. VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v(18): compiling module zkf_mul(WEXP=8). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v(21): compiling module _zkf_pack(WEXP=8). VERI-1018 Last elaborated design is top_zkf_mul_w8_m18_base() Loading NGL library '/usr/local/diamond/3.14/ispfpga/sa5p00/data/sa5plib.ngl'... Loading NGL library '/usr/local/diamond/3.14/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library '/usr/local/diamond/3.14/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library '/usr/local/diamond/3.14/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'sa5p25.nph' in environment: /usr/local/diamond/3.14/ispfpga. Package Status: Final Version 1.44. Top-level module name = top_zkf_mul_w8_m18_base. WARNING - synthesis: Bit 17 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 16 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 15 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 14 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 13 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 12 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 11 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 10 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 9 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 8 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 7 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 6 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 5 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 4 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 3 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 2 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 1 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 0 of Register \u_dut/s1_mag_e2 is stuck at Zero WARNING - synthesis: Bit 17 of Register \u_dut/s1_mag_e1 is stuck at Zero WARNING - synthesis: Bit 16 of Register \u_dut/s1_mag_e1 is stuck at Zero WARNING - synthesis: Bit 15 of Register \u_dut/s1_mag_e1 is stuck at Zero WARNING - synthesis: Bit 14 of Register \u_dut/s1_mag_e1 is stuck at Zero WARNING - synthesis: Bit 13 of Register \u_dut/s1_mag_e1 is stuck at Zero WARNING - synthesis: Bit 12 of Register \u_dut/s1_mag_e1 is stuck at Zero WARNING - synthesis: Bit 11 of Register \u_dut/s1_mag_e1 is stuck at Zero WARNING - synthesis: Bit 10 of Register \u_dut/s1_mag_e1 is stuck at Zero WARNING - synthesis: Bit 9 of Register \u_dut/s1_mag_e1 is stuck at Zero WARNING - synthesis: Bit 8 of Register \u_dut/s1_mag_e1 is stuck at Zero WARNING - synthesis: Bit 7 of Register \u_dut/s1_mag_e1 is stuck at Zero WARNING - synthesis: Bit 6 of Register \u_dut/s1_mag_e1 is stuck at Zero WARNING - synthesis: Bit 5 of Register \u_dut/s1_mag_e1 is stuck at Zero WARNING - synthesis: Bit 4 of Register \u_dut/s1_mag_e1 is stuck at Zero WARNING - synthesis: Bit 3 of Register \u_dut/s1_mag_e1 is stuck at Zero WARNING - synthesis: Bit 2 of Register \u_dut/s1_mag_e1 is stuck at Zero WARNING - synthesis: Bit 1 of Register \u_dut/s1_mag_e1 is stuck at Zero WARNING - synthesis: Bit 0 of Register \u_dut/s1_mag_e1 is stuck at Zero ######## Missing driver on net n620. Patching with GND. ######## Missing driver on net n619. Patching with GND. ######## Missing driver on net n618. Patching with GND. ######## GSR will not be inferred in an NGO flow, unless force_gsr=yes. WARNING - synthesis: No .lpf file will be written because the -lpf option is not used or is set to zero. Results of NGD DRC are available in top_zkf_mul_w8_m18_base_drc.log. WARNING - synthesis: DRC checking was skipped because the -ngo option was used. Writing NGD file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/zkf_mul_w8_m18_base/top_zkf_mul_w8_m18_base.ngo. ################### Begin Area Report (top_zkf_mul_w8_m18_base)###################### Number of register bits => 94 of 12687 (0 % ) CCU2C => 30 FD1S3AX => 65 FD1S3IX => 29 GSR => 1 IB => 55 LUT4 => 77 MULT18X18D => 1 OB => 27 PFUMX => 1 ################### End Area Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 1 Net : clk_c, loads : 95 Clock Enable Nets Number of Clock Enables: 0 Top 0 highest fanout Clock Enables: Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : u_dut/s1_exp_adjust_0, loads : 21 Net : u_dut/u_pack/n659, loads : 15 Net : u_dut/u_pack/n1115, loads : 15 Net : u_dut/u_pack/infinity, loads : 9 Net : u_dut/u_pack/result_min_normal_N_99, loads : 9 Net : exp_unbiased_in_9_N_51_1, loads : 7 Net : exp_unbiased_in_9_N_51_3, loads : 6 Net : exp_unbiased_in_9_N_51_2, loads : 6 Net : exp_unbiased_in_9_N_51_4, loads : 5 Net : rst_c, loads : 4 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 10.000000 | | | -waveform { 0.000000 5.000000 } -name | | | clk [ get_ports { clk } ] | 100.000 MHz| 66.569 MHz| 12 * | | | -------------------------------------------------------------------------------- 1 constraints not met. Peak Memory Usage: 215.285 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 1.214 secs -------------------------------------------------------------- $ /usr/local/diamond/3.14/ispfpga/bin/lin64/synthesis -f /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/zkf_mul_w8_m18_base/lse.synproj [exit code 0]