Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2025.2.1 (lin64) Build 6403652 Thu Mar 19 13:47:00 MDT 2026
| Date         : Sat May 23 22:42:15 2026
| Host         : deep-thought running 64-bit Manjaro Linux
| Command      : report_timing_summary -file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/zkf_add_w8_m36_base/timing_summary.rpt -max_paths 10 -nworst 10
| Design       : top_zkf_add_w8_m36_base
| Device       : 7s50-csga324
| Speed File   : -1  PRODUCTION 1.23 2018-06-13
| Design State : Routed
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (90)
6. checking no_output_delay (45)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (90)
-------------------------------
 There are 90 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (45)
--------------------------------
 There are 45 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.497        0.000                      0                  408        0.157        0.000                      0                  408        2.353        0.000                       0                   464  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock  Waveform(ns)         Period(ns)      Frequency(MHz)
-----  ------------         ----------      --------------
clk    {0.000 3.333}        6.667           149.993         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
clk                 0.497        0.000                      0                  408        0.157        0.000                      0                  408        2.353        0.000                       0                   464  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  clk
  To Clock:  clk

Setup :            0  Failing Endpoints,  Worst Slack        0.497ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.157ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.353ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.497ns  (required time - arrival time)
  Source:                 u_dut/s2_raw_result_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.562ns  (logic 1.182ns (21.253%)  route 4.380ns (78.747%))
  Logic Levels:           4  (LUT4=2 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.973     0.973    u_dut/clk
    SLICE_X5Y74          FDRE                                         r  u_dut/s2_raw_result_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y74          FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/s2_raw_result_reg[9]/Q
                         net (fo=8, routed)           1.119     2.548    u_dut/u_sub_norm/Q[9]
    SLICE_X7Y77          LUT4 (Prop_lut4_I0_O)        0.124     2.672 r  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5/O
                         net (fo=1, routed)           0.566     3.238    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5_n_0
    SLICE_X6Y78          LUT4 (Prop_lut4_I2_O)        0.124     3.362 r  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2/O
                         net (fo=18, routed)          0.900     4.263    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2_n_0
    SLICE_X8Y79          LUT5 (Prop_lut5_I2_O)        0.150     4.413 f  u_dut/u_sub_norm/g_data[2].g_split.data_r[3]_i_4/O
                         net (fo=28, routed)          0.971     5.384    u_dut/u_sub_norm/g_data[2].g_split.data_r[3]_i_4_n_0
    SLICE_X15Y78         LUT6 (Prop_lut6_I4_O)        0.328     5.712 r  u_dut/u_sub_norm/g_data[2].g_split.data_r[3]_i_1/O
                         net (fo=13, routed)          0.823     6.535    u_dut/u_sub_norm/g_data[2].g_split.data_r[3]_i_1_n_0
    SLICE_X12Y73         FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[1]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=463, unset)          0.924     7.591    u_dut/u_sub_norm/clk
    SLICE_X12Y73         FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[1]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X12Y73         FDRE (Setup_fdre_C_R)       -0.524     7.032    u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[1]
  -------------------------------------------------------------------
                         required time                          7.032    
                         arrival time                          -6.535    
  -------------------------------------------------------------------
                         slack                                  0.497    

Slack (MET) :             0.497ns  (required time - arrival time)
  Source:                 u_dut/s2_raw_result_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.562ns  (logic 1.182ns (21.253%)  route 4.380ns (78.747%))
  Logic Levels:           4  (LUT4=2 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.973     0.973    u_dut/clk
    SLICE_X5Y74          FDRE                                         r  u_dut/s2_raw_result_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y74          FDRE (Prop_fdre_C_Q)         0.456     1.429 f  u_dut/s2_raw_result_reg[9]/Q
                         net (fo=8, routed)           1.119     2.548    u_dut/u_sub_norm/Q[9]
    SLICE_X7Y77          LUT4 (Prop_lut4_I0_O)        0.124     2.672 f  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5/O
                         net (fo=1, routed)           0.566     3.238    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5_n_0
    SLICE_X6Y78          LUT4 (Prop_lut4_I2_O)        0.124     3.362 f  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2/O
                         net (fo=18, routed)          0.900     4.263    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2_n_0
    SLICE_X8Y79          LUT5 (Prop_lut5_I2_O)        0.150     4.413 r  u_dut/u_sub_norm/g_data[2].g_split.data_r[3]_i_4/O
                         net (fo=28, routed)          0.971     5.384    u_dut/u_sub_norm/g_data[2].g_split.data_r[3]_i_4_n_0
    SLICE_X15Y78         LUT6 (Prop_lut6_I4_O)        0.328     5.712 f  u_dut/u_sub_norm/g_data[2].g_split.data_r[3]_i_1/O
                         net (fo=13, routed)          0.823     6.535    u_dut/u_sub_norm/g_data[2].g_split.data_r[3]_i_1_n_0
    SLICE_X12Y73         FDRE                                         f  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[1]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=463, unset)          0.924     7.591    u_dut/u_sub_norm/clk
    SLICE_X12Y73         FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[1]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X12Y73         FDRE (Setup_fdre_C_R)       -0.524     7.032    u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[1]
  -------------------------------------------------------------------
                         required time                          7.032    
                         arrival time                          -6.535    
  -------------------------------------------------------------------
                         slack                                  0.497    

Slack (MET) :             0.497ns  (required time - arrival time)
  Source:                 u_dut/s2_raw_result_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.562ns  (logic 1.182ns (21.253%)  route 4.380ns (78.747%))
  Logic Levels:           4  (LUT4=2 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.973     0.973    u_dut/clk
    SLICE_X5Y74          FDRE                                         r  u_dut/s2_raw_result_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y74          FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/s2_raw_result_reg[9]/Q
                         net (fo=8, routed)           1.119     2.548    u_dut/u_sub_norm/Q[9]
    SLICE_X7Y77          LUT4 (Prop_lut4_I0_O)        0.124     2.672 r  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5/O
                         net (fo=1, routed)           0.566     3.238    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5_n_0
    SLICE_X6Y78          LUT4 (Prop_lut4_I2_O)        0.124     3.362 r  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2/O
                         net (fo=18, routed)          0.900     4.263    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2_n_0
    SLICE_X8Y79          LUT5 (Prop_lut5_I2_O)        0.150     4.413 f  u_dut/u_sub_norm/g_data[2].g_split.data_r[3]_i_4/O
                         net (fo=28, routed)          0.971     5.384    u_dut/u_sub_norm/g_data[2].g_split.data_r[3]_i_4_n_0
    SLICE_X15Y78         LUT6 (Prop_lut6_I4_O)        0.328     5.712 r  u_dut/u_sub_norm/g_data[2].g_split.data_r[3]_i_1/O
                         net (fo=13, routed)          0.823     6.535    u_dut/u_sub_norm/g_data[2].g_split.data_r[3]_i_1_n_0
    SLICE_X12Y73         FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=463, unset)          0.924     7.591    u_dut/u_sub_norm/clk
    SLICE_X12Y73         FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[2]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X12Y73         FDRE (Setup_fdre_C_R)       -0.524     7.032    u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[2]
  -------------------------------------------------------------------
                         required time                          7.032    
                         arrival time                          -6.535    
  -------------------------------------------------------------------
                         slack                                  0.497    

Slack (MET) :             0.497ns  (required time - arrival time)
  Source:                 u_dut/s2_raw_result_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.562ns  (logic 1.182ns (21.253%)  route 4.380ns (78.747%))
  Logic Levels:           4  (LUT4=2 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.973     0.973    u_dut/clk
    SLICE_X5Y74          FDRE                                         r  u_dut/s2_raw_result_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y74          FDRE (Prop_fdre_C_Q)         0.456     1.429 f  u_dut/s2_raw_result_reg[9]/Q
                         net (fo=8, routed)           1.119     2.548    u_dut/u_sub_norm/Q[9]
    SLICE_X7Y77          LUT4 (Prop_lut4_I0_O)        0.124     2.672 f  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5/O
                         net (fo=1, routed)           0.566     3.238    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5_n_0
    SLICE_X6Y78          LUT4 (Prop_lut4_I2_O)        0.124     3.362 f  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2/O
                         net (fo=18, routed)          0.900     4.263    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2_n_0
    SLICE_X8Y79          LUT5 (Prop_lut5_I2_O)        0.150     4.413 r  u_dut/u_sub_norm/g_data[2].g_split.data_r[3]_i_4/O
                         net (fo=28, routed)          0.971     5.384    u_dut/u_sub_norm/g_data[2].g_split.data_r[3]_i_4_n_0
    SLICE_X15Y78         LUT6 (Prop_lut6_I4_O)        0.328     5.712 f  u_dut/u_sub_norm/g_data[2].g_split.data_r[3]_i_1/O
                         net (fo=13, routed)          0.823     6.535    u_dut/u_sub_norm/g_data[2].g_split.data_r[3]_i_1_n_0
    SLICE_X12Y73         FDRE                                         f  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=463, unset)          0.924     7.591    u_dut/u_sub_norm/clk
    SLICE_X12Y73         FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[2]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X12Y73         FDRE (Setup_fdre_C_R)       -0.524     7.032    u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[2]
  -------------------------------------------------------------------
                         required time                          7.032    
                         arrival time                          -6.535    
  -------------------------------------------------------------------
                         slack                                  0.497    

Slack (MET) :             0.506ns  (required time - arrival time)
  Source:                 u_dut/s2_raw_result_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[11]/R
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.553ns  (logic 1.308ns (23.557%)  route 4.245ns (76.443%))
  Logic Levels:           5  (LUT2=1 LUT4=2 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.973     0.973    u_dut/clk
    SLICE_X5Y74          FDRE                                         r  u_dut/s2_raw_result_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y74          FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/s2_raw_result_reg[9]/Q
                         net (fo=8, routed)           1.119     2.548    u_dut/u_sub_norm/Q[9]
    SLICE_X7Y77          LUT4 (Prop_lut4_I0_O)        0.124     2.672 r  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5/O
                         net (fo=1, routed)           0.566     3.238    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5_n_0
    SLICE_X6Y78          LUT4 (Prop_lut4_I2_O)        0.124     3.362 r  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2/O
                         net (fo=18, routed)          0.863     4.225    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2_n_0
    SLICE_X9Y77          LUT5 (Prop_lut5_I0_O)        0.153     4.378 f  u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_8/O
                         net (fo=3, routed)           0.568     4.946    u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_8_n_0
    SLICE_X9Y78          LUT6 (Prop_lut6_I5_O)        0.327     5.273 r  u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_1/O
                         net (fo=38, routed)          0.577     5.850    u_dut/u_sub_norm/dig_pre_2[1]
    SLICE_X8Y78          LUT2 (Prop_lut2_I1_O)        0.124     5.974 r  u_dut/u_sub_norm/g_data[2].g_split.data_r[11]_i_1/O
                         net (fo=4, routed)           0.551     6.526    u_dut/u_sub_norm/g_data[2].g_split.data_r[11]_i_1_n_0
    SLICE_X8Y77          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[11]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=463, unset)          0.924     7.591    u_dut/u_sub_norm/clk
    SLICE_X8Y77          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[11]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X8Y77          FDRE (Setup_fdre_C_R)       -0.524     7.032    u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[11]
  -------------------------------------------------------------------
                         required time                          7.032    
                         arrival time                          -6.526    
  -------------------------------------------------------------------
                         slack                                  0.506    

Slack (MET) :             0.506ns  (required time - arrival time)
  Source:                 u_dut/s2_raw_result_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[11]/R
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.553ns  (logic 1.308ns (23.557%)  route 4.245ns (76.443%))
  Logic Levels:           5  (LUT2=1 LUT4=2 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.973     0.973    u_dut/clk
    SLICE_X5Y74          FDRE                                         r  u_dut/s2_raw_result_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y74          FDRE (Prop_fdre_C_Q)         0.456     1.429 f  u_dut/s2_raw_result_reg[9]/Q
                         net (fo=8, routed)           1.119     2.548    u_dut/u_sub_norm/Q[9]
    SLICE_X7Y77          LUT4 (Prop_lut4_I0_O)        0.124     2.672 f  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5/O
                         net (fo=1, routed)           0.566     3.238    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5_n_0
    SLICE_X6Y78          LUT4 (Prop_lut4_I2_O)        0.124     3.362 f  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2/O
                         net (fo=18, routed)          0.863     4.225    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2_n_0
    SLICE_X9Y77          LUT5 (Prop_lut5_I0_O)        0.153     4.378 r  u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_8/O
                         net (fo=3, routed)           0.568     4.946    u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_8_n_0
    SLICE_X9Y78          LUT6 (Prop_lut6_I5_O)        0.327     5.273 f  u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_1/O
                         net (fo=38, routed)          0.577     5.850    u_dut/u_sub_norm/dig_pre_2[1]
    SLICE_X8Y78          LUT2 (Prop_lut2_I1_O)        0.124     5.974 f  u_dut/u_sub_norm/g_data[2].g_split.data_r[11]_i_1/O
                         net (fo=4, routed)           0.551     6.526    u_dut/u_sub_norm/g_data[2].g_split.data_r[11]_i_1_n_0
    SLICE_X8Y77          FDRE                                         f  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[11]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=463, unset)          0.924     7.591    u_dut/u_sub_norm/clk
    SLICE_X8Y77          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[11]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X8Y77          FDRE (Setup_fdre_C_R)       -0.524     7.032    u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[11]
  -------------------------------------------------------------------
                         required time                          7.032    
                         arrival time                          -6.526    
  -------------------------------------------------------------------
                         slack                                  0.506    

Slack (MET) :             0.506ns  (required time - arrival time)
  Source:                 u_dut/s2_raw_result_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[8]/R
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.553ns  (logic 1.308ns (23.557%)  route 4.245ns (76.443%))
  Logic Levels:           5  (LUT2=1 LUT4=2 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.973     0.973    u_dut/clk
    SLICE_X5Y74          FDRE                                         r  u_dut/s2_raw_result_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y74          FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/s2_raw_result_reg[9]/Q
                         net (fo=8, routed)           1.119     2.548    u_dut/u_sub_norm/Q[9]
    SLICE_X7Y77          LUT4 (Prop_lut4_I0_O)        0.124     2.672 r  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5/O
                         net (fo=1, routed)           0.566     3.238    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5_n_0
    SLICE_X6Y78          LUT4 (Prop_lut4_I2_O)        0.124     3.362 r  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2/O
                         net (fo=18, routed)          0.863     4.225    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2_n_0
    SLICE_X9Y77          LUT5 (Prop_lut5_I0_O)        0.153     4.378 f  u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_8/O
                         net (fo=3, routed)           0.568     4.946    u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_8_n_0
    SLICE_X9Y78          LUT6 (Prop_lut6_I5_O)        0.327     5.273 r  u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_1/O
                         net (fo=38, routed)          0.577     5.850    u_dut/u_sub_norm/dig_pre_2[1]
    SLICE_X8Y78          LUT2 (Prop_lut2_I1_O)        0.124     5.974 r  u_dut/u_sub_norm/g_data[2].g_split.data_r[11]_i_1/O
                         net (fo=4, routed)           0.551     6.526    u_dut/u_sub_norm/g_data[2].g_split.data_r[11]_i_1_n_0
    SLICE_X8Y77          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[8]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=463, unset)          0.924     7.591    u_dut/u_sub_norm/clk
    SLICE_X8Y77          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[8]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X8Y77          FDRE (Setup_fdre_C_R)       -0.524     7.032    u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[8]
  -------------------------------------------------------------------
                         required time                          7.032    
                         arrival time                          -6.526    
  -------------------------------------------------------------------
                         slack                                  0.506    

Slack (MET) :             0.506ns  (required time - arrival time)
  Source:                 u_dut/s2_raw_result_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[8]/R
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.553ns  (logic 1.308ns (23.557%)  route 4.245ns (76.443%))
  Logic Levels:           5  (LUT2=1 LUT4=2 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.973     0.973    u_dut/clk
    SLICE_X5Y74          FDRE                                         r  u_dut/s2_raw_result_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y74          FDRE (Prop_fdre_C_Q)         0.456     1.429 f  u_dut/s2_raw_result_reg[9]/Q
                         net (fo=8, routed)           1.119     2.548    u_dut/u_sub_norm/Q[9]
    SLICE_X7Y77          LUT4 (Prop_lut4_I0_O)        0.124     2.672 f  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5/O
                         net (fo=1, routed)           0.566     3.238    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5_n_0
    SLICE_X6Y78          LUT4 (Prop_lut4_I2_O)        0.124     3.362 f  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2/O
                         net (fo=18, routed)          0.863     4.225    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2_n_0
    SLICE_X9Y77          LUT5 (Prop_lut5_I0_O)        0.153     4.378 r  u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_8/O
                         net (fo=3, routed)           0.568     4.946    u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_8_n_0
    SLICE_X9Y78          LUT6 (Prop_lut6_I5_O)        0.327     5.273 f  u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_1/O
                         net (fo=38, routed)          0.577     5.850    u_dut/u_sub_norm/dig_pre_2[1]
    SLICE_X8Y78          LUT2 (Prop_lut2_I1_O)        0.124     5.974 f  u_dut/u_sub_norm/g_data[2].g_split.data_r[11]_i_1/O
                         net (fo=4, routed)           0.551     6.526    u_dut/u_sub_norm/g_data[2].g_split.data_r[11]_i_1_n_0
    SLICE_X8Y77          FDRE                                         f  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[8]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=463, unset)          0.924     7.591    u_dut/u_sub_norm/clk
    SLICE_X8Y77          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[8]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X8Y77          FDRE (Setup_fdre_C_R)       -0.524     7.032    u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[8]
  -------------------------------------------------------------------
                         required time                          7.032    
                         arrival time                          -6.526    
  -------------------------------------------------------------------
                         slack                                  0.506    

Slack (MET) :             0.520ns  (required time - arrival time)
  Source:                 u_dut/s2_raw_result_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[11]/R
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.539ns  (logic 1.304ns (23.544%)  route 4.235ns (76.456%))
  Logic Levels:           5  (LUT2=1 LUT4=2 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.973     0.973    u_dut/clk
    SLICE_X5Y74          FDRE                                         r  u_dut/s2_raw_result_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y74          FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/s2_raw_result_reg[9]/Q
                         net (fo=8, routed)           1.119     2.548    u_dut/u_sub_norm/Q[9]
    SLICE_X7Y77          LUT4 (Prop_lut4_I0_O)        0.124     2.672 r  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5/O
                         net (fo=1, routed)           0.566     3.238    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5_n_0
    SLICE_X6Y78          LUT4 (Prop_lut4_I2_O)        0.124     3.362 r  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2/O
                         net (fo=18, routed)          0.969     4.331    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2_n_0
    SLICE_X9Y78          LUT5 (Prop_lut5_I0_O)        0.150     4.481 f  u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_7/O
                         net (fo=3, routed)           0.452     4.933    u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_7_n_0
    SLICE_X9Y78          LUT6 (Prop_lut6_I4_O)        0.326     5.259 r  u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_1/O
                         net (fo=38, routed)          0.577     5.836    u_dut/u_sub_norm/dig_pre_2[1]
    SLICE_X8Y78          LUT2 (Prop_lut2_I1_O)        0.124     5.960 r  u_dut/u_sub_norm/g_data[2].g_split.data_r[11]_i_1/O
                         net (fo=4, routed)           0.551     6.512    u_dut/u_sub_norm/g_data[2].g_split.data_r[11]_i_1_n_0
    SLICE_X8Y77          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[11]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=463, unset)          0.924     7.591    u_dut/u_sub_norm/clk
    SLICE_X8Y77          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[11]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X8Y77          FDRE (Setup_fdre_C_R)       -0.524     7.032    u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[11]
  -------------------------------------------------------------------
                         required time                          7.032    
                         arrival time                          -6.512    
  -------------------------------------------------------------------
                         slack                                  0.520    

Slack (MET) :             0.520ns  (required time - arrival time)
  Source:                 u_dut/s2_raw_result_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[11]/R
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.539ns  (logic 1.304ns (23.544%)  route 4.235ns (76.456%))
  Logic Levels:           5  (LUT2=1 LUT4=2 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.973     0.973    u_dut/clk
    SLICE_X5Y74          FDRE                                         r  u_dut/s2_raw_result_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y74          FDRE (Prop_fdre_C_Q)         0.456     1.429 f  u_dut/s2_raw_result_reg[9]/Q
                         net (fo=8, routed)           1.119     2.548    u_dut/u_sub_norm/Q[9]
    SLICE_X7Y77          LUT4 (Prop_lut4_I0_O)        0.124     2.672 f  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5/O
                         net (fo=1, routed)           0.566     3.238    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_5_n_0
    SLICE_X6Y78          LUT4 (Prop_lut4_I2_O)        0.124     3.362 f  u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2/O
                         net (fo=18, routed)          0.969     4.331    u_dut/u_sub_norm/g_count[2].g_count_delay.dig_r[0]_i_2_n_0
    SLICE_X9Y78          LUT5 (Prop_lut5_I0_O)        0.150     4.481 r  u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_7/O
                         net (fo=3, routed)           0.452     4.933    u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_7_n_0
    SLICE_X9Y78          LUT6 (Prop_lut6_I4_O)        0.326     5.259 f  u_dut/u_sub_norm/g_data[2].g_split.data_r[7]_i_1/O
                         net (fo=38, routed)          0.577     5.836    u_dut/u_sub_norm/dig_pre_2[1]
    SLICE_X8Y78          LUT2 (Prop_lut2_I1_O)        0.124     5.960 f  u_dut/u_sub_norm/g_data[2].g_split.data_r[11]_i_1/O
                         net (fo=4, routed)           0.551     6.512    u_dut/u_sub_norm/g_data[2].g_split.data_r[11]_i_1_n_0
    SLICE_X8Y77          FDRE                                         f  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[11]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=463, unset)          0.924     7.591    u_dut/u_sub_norm/clk
    SLICE_X8Y77          FDRE                                         r  u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[11]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X8Y77          FDRE (Setup_fdre_C_R)       -0.524     7.032    u_dut/u_sub_norm/g_data[2].g_split.data_r_reg[11]
  -------------------------------------------------------------------
                         required time                          7.032    
                         arrival time                          -6.512    
  -------------------------------------------------------------------
                         slack                                  0.520    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.157ns  (arrival time - required time)
  Source:                 u_dut/s0_large_sig_exp_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_large_ext_exp_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.254ns  (logic 0.141ns (55.533%)  route 0.113ns (44.467%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.410     0.410    u_dut/clk
    SLICE_X3Y76          FDRE                                         r  u_dut/s0_large_sig_exp_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y76          FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/s0_large_sig_exp_reg[17]/Q
                         net (fo=1, routed)           0.113     0.664    u_dut/s0_large_sig_exp[17]
    SLICE_X5Y76          FDRE                                         r  u_dut/s1_large_ext_exp_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.432     0.432    u_dut/clk
    SLICE_X5Y76          FDRE                                         r  u_dut/s1_large_ext_exp_reg[20]/C
                         clock pessimism              0.000     0.432    
    SLICE_X5Y76          FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/s1_large_ext_exp_reg[20]
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.664    
  -------------------------------------------------------------------
                         slack                                  0.157    

Slack (MET) :             0.157ns  (arrival time - required time)
  Source:                 u_dut/s0_large_sig_exp_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_large_ext_exp_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.254ns  (logic 0.141ns (55.533%)  route 0.113ns (44.467%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.410     0.410    u_dut/clk
    SLICE_X3Y76          FDRE                                         r  u_dut/s0_large_sig_exp_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y76          FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/s0_large_sig_exp_reg[17]/Q
                         net (fo=1, routed)           0.113     0.664    u_dut/s0_large_sig_exp[17]
    SLICE_X5Y76          FDRE                                         f  u_dut/s1_large_ext_exp_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.432     0.432    u_dut/clk
    SLICE_X5Y76          FDRE                                         r  u_dut/s1_large_ext_exp_reg[20]/C
                         clock pessimism              0.000     0.432    
    SLICE_X5Y76          FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/s1_large_ext_exp_reg[20]
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.664    
  -------------------------------------------------------------------
                         slack                                  0.157    

Slack (MET) :             0.157ns  (arrival time - required time)
  Source:                 u_dut/s0_large_sig_exp_reg[26]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_large_ext_exp_reg[29]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.254ns  (logic 0.141ns (55.533%)  route 0.113ns (44.467%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.410     0.410    u_dut/clk
    SLICE_X3Y78          FDRE                                         r  u_dut/s0_large_sig_exp_reg[26]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y78          FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/s0_large_sig_exp_reg[26]/Q
                         net (fo=1, routed)           0.113     0.664    u_dut/s0_large_sig_exp[26]
    SLICE_X5Y78          FDRE                                         r  u_dut/s1_large_ext_exp_reg[29]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.432     0.432    u_dut/clk
    SLICE_X5Y78          FDRE                                         r  u_dut/s1_large_ext_exp_reg[29]/C
                         clock pessimism              0.000     0.432    
    SLICE_X5Y78          FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/s1_large_ext_exp_reg[29]
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.664    
  -------------------------------------------------------------------
                         slack                                  0.157    

Slack (MET) :             0.157ns  (arrival time - required time)
  Source:                 u_dut/s0_large_sig_exp_reg[26]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_large_ext_exp_reg[29]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.254ns  (logic 0.141ns (55.533%)  route 0.113ns (44.467%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.410     0.410    u_dut/clk
    SLICE_X3Y78          FDRE                                         r  u_dut/s0_large_sig_exp_reg[26]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y78          FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/s0_large_sig_exp_reg[26]/Q
                         net (fo=1, routed)           0.113     0.664    u_dut/s0_large_sig_exp[26]
    SLICE_X5Y78          FDRE                                         f  u_dut/s1_large_ext_exp_reg[29]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.432     0.432    u_dut/clk
    SLICE_X5Y78          FDRE                                         r  u_dut/s1_large_ext_exp_reg[29]/C
                         clock pessimism              0.000     0.432    
    SLICE_X5Y78          FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/s1_large_ext_exp_reg[29]
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.664    
  -------------------------------------------------------------------
                         slack                                  0.157    

Slack (MET) :             0.157ns  (arrival time - required time)
  Source:                 u_dut/s0_large_sig_exp_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_large_ext_exp_reg[19]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.254ns  (logic 0.141ns (55.518%)  route 0.113ns (44.482%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.410     0.410    u_dut/clk
    SLICE_X3Y76          FDRE                                         r  u_dut/s0_large_sig_exp_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y76          FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/s0_large_sig_exp_reg[16]/Q
                         net (fo=1, routed)           0.113     0.664    u_dut/s0_large_sig_exp[16]
    SLICE_X5Y75          FDRE                                         r  u_dut/s1_large_ext_exp_reg[19]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.432     0.432    u_dut/clk
    SLICE_X5Y75          FDRE                                         r  u_dut/s1_large_ext_exp_reg[19]/C
                         clock pessimism              0.000     0.432    
    SLICE_X5Y75          FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/s1_large_ext_exp_reg[19]
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.664    
  -------------------------------------------------------------------
                         slack                                  0.157    

Slack (MET) :             0.157ns  (arrival time - required time)
  Source:                 u_dut/s0_large_sig_exp_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_large_ext_exp_reg[19]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.254ns  (logic 0.141ns (55.518%)  route 0.113ns (44.482%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.410     0.410    u_dut/clk
    SLICE_X3Y76          FDRE                                         r  u_dut/s0_large_sig_exp_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y76          FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/s0_large_sig_exp_reg[16]/Q
                         net (fo=1, routed)           0.113     0.664    u_dut/s0_large_sig_exp[16]
    SLICE_X5Y75          FDRE                                         f  u_dut/s1_large_ext_exp_reg[19]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.432     0.432    u_dut/clk
    SLICE_X5Y75          FDRE                                         r  u_dut/s1_large_ext_exp_reg[19]/C
                         clock pessimism              0.000     0.432    
    SLICE_X5Y75          FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/s1_large_ext_exp_reg[19]
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.664    
  -------------------------------------------------------------------
                         slack                                  0.157    

Slack (MET) :             0.157ns  (arrival time - required time)
  Source:                 u_dut/s0_large_sig_exp_reg[33]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_large_ext_exp_reg[36]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.251ns  (logic 0.141ns (56.174%)  route 0.110ns (43.826%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.410     0.410    u_dut/clk
    SLICE_X3Y80          FDRE                                         r  u_dut/s0_large_sig_exp_reg[33]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y80          FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/s0_large_sig_exp_reg[33]/Q
                         net (fo=1, routed)           0.110     0.661    u_dut/s0_large_sig_exp[33]
    SLICE_X3Y80          FDRE                                         r  u_dut/s1_large_ext_exp_reg[36]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.432     0.432    u_dut/clk
    SLICE_X3Y80          FDRE                                         r  u_dut/s1_large_ext_exp_reg[36]/C
                         clock pessimism              0.000     0.432    
    SLICE_X3Y80          FDRE (Hold_fdre_C_D)         0.072     0.504    u_dut/s1_large_ext_exp_reg[36]
  -------------------------------------------------------------------
                         required time                         -0.504    
                         arrival time                           0.661    
  -------------------------------------------------------------------
                         slack                                  0.157    

Slack (MET) :             0.157ns  (arrival time - required time)
  Source:                 u_dut/s0_large_sig_exp_reg[33]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_large_ext_exp_reg[36]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.251ns  (logic 0.141ns (56.174%)  route 0.110ns (43.826%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.410     0.410    u_dut/clk
    SLICE_X3Y80          FDRE                                         r  u_dut/s0_large_sig_exp_reg[33]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y80          FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/s0_large_sig_exp_reg[33]/Q
                         net (fo=1, routed)           0.110     0.661    u_dut/s0_large_sig_exp[33]
    SLICE_X3Y80          FDRE                                         f  u_dut/s1_large_ext_exp_reg[36]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.432     0.432    u_dut/clk
    SLICE_X3Y80          FDRE                                         r  u_dut/s1_large_ext_exp_reg[36]/C
                         clock pessimism              0.000     0.432    
    SLICE_X3Y80          FDRE (Hold_fdre_C_D)         0.072     0.504    u_dut/s1_large_ext_exp_reg[36]
  -------------------------------------------------------------------
                         required time                         -0.504    
                         arrival time                           0.661    
  -------------------------------------------------------------------
                         slack                                  0.157    

Slack (MET) :             0.160ns  (arrival time - required time)
  Source:                 u_dut/s0_large_sig_exp_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_large_ext_exp_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.257ns  (logic 0.141ns (54.953%)  route 0.116ns (45.047%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.410     0.410    u_dut/clk
    SLICE_X4Y73          FDRE                                         r  u_dut/s0_large_sig_exp_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X4Y73          FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/s0_large_sig_exp_reg[6]/Q
                         net (fo=1, routed)           0.116     0.667    u_dut/s0_large_sig_exp[6]
    SLICE_X5Y74          FDRE                                         r  u_dut/s1_large_ext_exp_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.432     0.432    u_dut/clk
    SLICE_X5Y74          FDRE                                         r  u_dut/s1_large_ext_exp_reg[9]/C
                         clock pessimism              0.000     0.432    
    SLICE_X5Y74          FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/s1_large_ext_exp_reg[9]
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.667    
  -------------------------------------------------------------------
                         slack                                  0.160    

Slack (MET) :             0.160ns  (arrival time - required time)
  Source:                 u_dut/s0_large_sig_exp_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_large_ext_exp_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.257ns  (logic 0.141ns (54.953%)  route 0.116ns (45.047%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.410     0.410    u_dut/clk
    SLICE_X4Y73          FDRE                                         r  u_dut/s0_large_sig_exp_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X4Y73          FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/s0_large_sig_exp_reg[6]/Q
                         net (fo=1, routed)           0.116     0.667    u_dut/s0_large_sig_exp[6]
    SLICE_X5Y74          FDRE                                         f  u_dut/s1_large_ext_exp_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=463, unset)          0.432     0.432    u_dut/clk
    SLICE_X5Y74          FDRE                                         r  u_dut/s1_large_ext_exp_reg[9]/C
                         clock pessimism              0.000     0.432    
    SLICE_X5Y74          FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/s1_large_ext_exp_reg[9]
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.667    
  -------------------------------------------------------------------
                         slack                                  0.160    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.667
Sources:            { clk }

Check Type        Corner  Lib Pin     Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location     Pin
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X2Y72  a_r_reg[0]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X2Y73  a_r_reg[10]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X2Y74  a_r_reg[11]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X2Y75  a_r_reg[12]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X3Y75  a_r_reg[13]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X3Y74  a_r_reg[14]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X2Y75  a_r_reg[15]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X3Y76  a_r_reg[16]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X3Y76  a_r_reg[17]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X2Y74  a_r_reg[18]/C
Low Pulse Width   Slow    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y84  u_dut/s1_exp_biased_reg[0]_srl2/CLK
Low Pulse Width   Fast    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y84  u_dut/s1_exp_biased_reg[0]_srl2/CLK
Low Pulse Width   Slow    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y84  u_dut/s1_exp_biased_reg[1]_srl2/CLK
Low Pulse Width   Fast    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y84  u_dut/s1_exp_biased_reg[1]_srl2/CLK
Low Pulse Width   Slow    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y84  u_dut/s1_exp_biased_reg[2]_srl2/CLK
Low Pulse Width   Fast    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y84  u_dut/s1_exp_biased_reg[2]_srl2/CLK
Low Pulse Width   Slow    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y84  u_dut/s1_exp_biased_reg[3]_srl2/CLK
Low Pulse Width   Fast    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y84  u_dut/s1_exp_biased_reg[3]_srl2/CLK
Low Pulse Width   Slow    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y84  u_dut/s1_exp_biased_reg[4]_srl2/CLK
Low Pulse Width   Fast    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y84  u_dut/s1_exp_biased_reg[4]_srl2/CLK
High Pulse Width  Slow    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y84  u_dut/s1_exp_biased_reg[0]_srl2/CLK
High Pulse Width  Fast    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y84  u_dut/s1_exp_biased_reg[0]_srl2/CLK
High Pulse Width  Slow    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y84  u_dut/s1_exp_biased_reg[1]_srl2/CLK
High Pulse Width  Fast    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y84  u_dut/s1_exp_biased_reg[1]_srl2/CLK
High Pulse Width  Slow    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y84  u_dut/s1_exp_biased_reg[2]_srl2/CLK
High Pulse Width  Fast    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y84  u_dut/s1_exp_biased_reg[2]_srl2/CLK
High Pulse Width  Slow    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y84  u_dut/s1_exp_biased_reg[3]_srl2/CLK
High Pulse Width  Fast    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y84  u_dut/s1_exp_biased_reg[3]_srl2/CLK
High Pulse Width  Slow    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X6Y84  u_dut/s1_exp_biased_reg[4]_srl2/CLK
High Pulse Width  Fast    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X6Y84  u_dut/s1_exp_biased_reg[4]_srl2/CLK



