/----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2026  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3)

-- Executing script file `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/yosys.ys' --

1. Executing Verilog-2005 frontend: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v
Parsing SystemVerilog input from `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v' to AST representation.
Generating RTLIL representation for module `\FpxxAdd'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/top_tommath_add_e8_m17_round_even_sticky_p4.v
Parsing SystemVerilog input from `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/top_tommath_add_e8_m17_round_even_sticky_p4.v' to AST representation.
Generating RTLIL representation for module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Successfully finished Verilog frontend.

3. Executing SYNTH_LATTICE pass.

3.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v
Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\VLO'.
Generating RTLIL representation for module `\VHI'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\DP16KD'.
Replacing existing blackbox module `\FD1P3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
Generating RTLIL representation for module `\FD1P3AX'.
Replacing existing blackbox module `\FD1P3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
Generating RTLIL representation for module `\FD1P3AY'.
Replacing existing blackbox module `\FD1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
Generating RTLIL representation for module `\FD1P3BX'.
Replacing existing blackbox module `\FD1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
Generating RTLIL representation for module `\FD1P3DX'.
Replacing existing blackbox module `\FD1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
Generating RTLIL representation for module `\FD1P3IX'.
Replacing existing blackbox module `\FD1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
Generating RTLIL representation for module `\FD1P3JX'.
Replacing existing blackbox module `\FD1S3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
Generating RTLIL representation for module `\FD1S3AX'.
Replacing existing blackbox module `\FD1S3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
Generating RTLIL representation for module `\FD1S3AY'.
Replacing existing blackbox module `\FD1S3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
Generating RTLIL representation for module `\FD1S3BX'.
Replacing existing blackbox module `\FD1S3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
Generating RTLIL representation for module `\FD1S3DX'.
Replacing existing blackbox module `\FD1S3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
Generating RTLIL representation for module `\FD1S3IX'.
Replacing existing blackbox module `\FD1S3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
Generating RTLIL representation for module `\FD1S3JX'.
Replacing existing blackbox module `\IFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
Generating RTLIL representation for module `\IFS1P3BX'.
Replacing existing blackbox module `\IFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
Generating RTLIL representation for module `\IFS1P3DX'.
Replacing existing blackbox module `\IFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
Generating RTLIL representation for module `\IFS1P3IX'.
Replacing existing blackbox module `\IFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
Generating RTLIL representation for module `\IFS1P3JX'.
Replacing existing blackbox module `\OFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
Generating RTLIL representation for module `\OFS1P3BX'.
Replacing existing blackbox module `\OFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
Generating RTLIL representation for module `\OFS1P3DX'.
Replacing existing blackbox module `\OFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
Generating RTLIL representation for module `\OFS1P3IX'.
Replacing existing blackbox module `\OFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
Generating RTLIL representation for module `\OFS1P3JX'.
Replacing existing blackbox module `\IB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:2.1-2.157.
Generating RTLIL representation for module `\IB'.
Replacing existing blackbox module `\IBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:3.1-3.157.
Generating RTLIL representation for module `\IBPU'.
Replacing existing blackbox module `\IBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:4.1-4.157.
Generating RTLIL representation for module `\IBPD'.
Replacing existing blackbox module `\OB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:5.1-5.157.
Generating RTLIL representation for module `\OB'.
Replacing existing blackbox module `\OBZ' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:6.1-6.164.
Generating RTLIL representation for module `\OBZ'.
Replacing existing blackbox module `\OBZPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:7.1-7.164.
Generating RTLIL representation for module `\OBZPU'.
Replacing existing blackbox module `\OBZPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:8.1-8.164.
Generating RTLIL representation for module `\OBZPD'.
Replacing existing blackbox module `\OBCO' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:9.1-9.90.
Generating RTLIL representation for module `\OBCO'.
Replacing existing blackbox module `\BB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:10.1-10.179.
Generating RTLIL representation for module `\BB'.
Replacing existing blackbox module `\BBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:11.1-11.179.
Generating RTLIL representation for module `\BBPU'.
Replacing existing blackbox module `\BBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:12.1-12.179.
Generating RTLIL representation for module `\BBPD'.
Replacing existing blackbox module `\ILVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:13.1-13.139.
Generating RTLIL representation for module `\ILVDS'.
Replacing existing blackbox module `\OLVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:14.1-14.146.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

3.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v
Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DCUA'.
Successfully finished Verilog frontend.

3.3. Executing HIERARCHY pass (managing design hierarchy).

3.3.1. Analyzing design hierarchy..
Top module:  \top_tommath_add_e8_m17_round_even_sticky_p4
Used module:     \FpxxAdd

3.3.2. Analyzing design hierarchy..
Top module:  \top_tommath_add_e8_m17_round_even_sticky_p4
Used module:     \FpxxAdd
Removed 0 unused modules.

3.4. Executing PROC pass (convert processes to netlists).

3.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/top_tommath_add_e8_m17_round_even_sticky_p4.v:43$129 in module top_tommath_add_e8_m17_round_even_sticky_p4.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:917$127 in module FpxxAdd.
Marked 2 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:886$120 in module FpxxAdd.
Marked 2 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:874$115 in module FpxxAdd.
Marked 2 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:862$114 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:851$110 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:843$108 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:829$102 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:820$99 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:812$97 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:798$96 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:782$95 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:766$94 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:750$93 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:734$92 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:716$91 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:700$90 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:684$89 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:668$88 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:652$87 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:635$86 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:619$85 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:603$84 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:585$83 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:569$82 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:553$81 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:537$80 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:520$79 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:504$78 in module FpxxAdd.
Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:488$77 in module FpxxAdd.
Marked 2 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:465$73 in module FpxxAdd.
Marked 2 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:453$71 in module FpxxAdd.
Marked 2 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:441$70 in module FpxxAdd.
Removed a total of 0 dead cases.

3.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 6 redundant assignments.
Promoted 67 assignments to connections.

3.4.4. Executing PROC_INIT pass (extract init attributes).

3.4.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \reset in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:917$127'.

3.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~38 debug messages>

3.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\top_tommath_add_e8_m17_round_even_sticky_p4.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/top_tommath_add_e8_m17_round_even_sticky_p4.v:43$129'.
     1/2: $0\out_valid_r[0:0]
     2/2: $0\in_valid_r[0:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:917$127'.
     1/4: $0\n4_valid[0:0]
     2/4: $0\n3_valid[0:0]
     3/4: $0\n2_valid[0:0]
     4/4: $0\n1_valid[0:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:886$120'.
     1/3: $2\n5_mant_final[16:0]
     2/3: $1\n5_mant_final[16:0] [16]
     3/3: $1\n5_mant_final[16:0] [15:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:874$115'.
     1/2: $2\n5_exp_final[7:0]
     2/2: $1\n5_exp_final[7:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:862$114'.
     1/2: $2\n5_sign_final[0:0]
     2/2: $1\n5_sign_final[0:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:851$110'.
     1/1: $1\_zz_n5_mant_rounded[18:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:843$108'.
     1/1: $1\_zz_n5_mant_rounded_1[18:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:829$102'.
     1/1: $1\n4__exp_add_adj[7:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:820$99'.
     1/2: $1\n4__mant_add_adj[20:0] [20:1]
     2/2: $1\n4__mant_add_adj[20:0] [0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:812$97'.
     1/1: $1\n4__lz[4:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:798$96'.
     1/1: $1\_zz_n4__lz[5:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:782$95'.
     1/1: $1\_zz_switch_Misc_l241_47[3:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:766$94'.
     1/1: $1\_zz_switch_Misc_l241_45[2:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:750$93'.
     1/1: $1\_zz_switch_Misc_l241_43[1:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:734$92'.
     1/1: $1\_zz_switch_Misc_l241_41[1:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:716$91'.
     1/1: $1\_zz_switch_Misc_l241_37[4:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:700$90'.
     1/1: $1\_zz_switch_Misc_l241_35[3:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:684$89'.
     1/1: $1\_zz_switch_Misc_l241_33[2:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:668$88'.
     1/1: $1\_zz_switch_Misc_l241_31[1:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:652$87'.
     1/1: $1\_zz_switch_Misc_l241_29[1:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:635$86'.
     1/1: $1\_zz_switch_Misc_l241_26[2:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:619$85'.
     1/1: $1\_zz_switch_Misc_l241_24[1:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:603$84'.
     1/1: $1\_zz_switch_Misc_l241_22[1:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:585$83'.
     1/1: $1\_zz_switch_Misc_l241_18[3:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:569$82'.
     1/1: $1\_zz_switch_Misc_l241_16[2:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:553$81'.
     1/1: $1\_zz_switch_Misc_l241_14[1:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:537$80'.
     1/1: $1\_zz_switch_Misc_l241_12[1:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:520$79'.
     1/1: $1\_zz_switch_Misc_l241_9[2:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:504$78'.
     1/1: $1\_zz_switch_Misc_l241_7[1:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:488$77'.
     1/1: $1\_zz_switch_Misc_l241_5[1:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:465$73'.
     1/2: $2\n2__mant_b_opt_inv[22:0]
     2/2: $1\n2__mant_b_opt_inv[22:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:453$71'.
     1/2: $2\n2__mant_a_opt_inv[22:0]
     2/2: $1\n2__mant_a_opt_inv[22:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:441$70'.
     1/2: $2\n2__sign_add[0:0]
     2/2: $1\n2__sign_add[0:0]
Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:431$60'.

3.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\FpxxAdd.\n5_mant_final' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:886$120'.
No latch inferred for signal `\FpxxAdd.\n5_exp_final' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:874$115'.
No latch inferred for signal `\FpxxAdd.\n5_sign_final' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:862$114'.
No latch inferred for signal `\FpxxAdd.\_zz_n5_mant_rounded' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:851$110'.
No latch inferred for signal `\FpxxAdd.\_zz_n5_mant_rounded_1' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:843$108'.
No latch inferred for signal `\FpxxAdd.\n4__exp_add_adj' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:829$102'.
No latch inferred for signal `\FpxxAdd.\n4__mant_add_adj' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:820$99'.
No latch inferred for signal `\FpxxAdd.\n4__lz' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:812$97'.
No latch inferred for signal `\FpxxAdd.\_zz_n4__lz' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:798$96'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_47' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:782$95'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_45' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:766$94'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_43' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:750$93'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_41' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:734$92'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_37' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:716$91'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_35' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:700$90'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_33' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:684$89'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_31' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:668$88'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_29' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:652$87'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_26' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:635$86'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_24' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:619$85'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_22' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:603$84'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_18' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:585$83'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_16' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:569$82'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_14' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:553$81'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_12' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:537$80'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_9' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:520$79'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_7' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:504$78'.
No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_5' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:488$77'.
No latch inferred for signal `\FpxxAdd.\n2__mant_b_opt_inv' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:465$73'.
No latch inferred for signal `\FpxxAdd.\n2__mant_a_opt_inv' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:453$71'.
No latch inferred for signal `\FpxxAdd.\n2__sign_add' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:441$70'.
No latch inferred for signal `\FpxxAdd.\n1__mant_b_shift' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:431$60'.

3.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\top_tommath_add_e8_m17_round_even_sticky_p4.\a_r' using process `\top_tommath_add_e8_m17_round_even_sticky_p4.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/top_tommath_add_e8_m17_round_even_sticky_p4.v:43$129'.
  created $dff cell `$procdff$515' with positive edge clock.
Creating register for signal `\top_tommath_add_e8_m17_round_even_sticky_p4.\b_r' using process `\top_tommath_add_e8_m17_round_even_sticky_p4.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/top_tommath_add_e8_m17_round_even_sticky_p4.v:43$129'.
  created $dff cell `$procdff$516' with positive edge clock.
Creating register for signal `\top_tommath_add_e8_m17_round_even_sticky_p4.\in_valid_r' using process `\top_tommath_add_e8_m17_round_even_sticky_p4.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/top_tommath_add_e8_m17_round_even_sticky_p4.v:43$129'.
  created $dff cell `$procdff$517' with positive edge clock.
Creating register for signal `\top_tommath_add_e8_m17_round_even_sticky_p4.\y_r' using process `\top_tommath_add_e8_m17_round_even_sticky_p4.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/top_tommath_add_e8_m17_round_even_sticky_p4.v:43$129'.
  created $dff cell `$procdff$518' with positive edge clock.
Creating register for signal `\top_tommath_add_e8_m17_round_even_sticky_p4.\out_valid_r' using process `\top_tommath_add_e8_m17_round_even_sticky_p4.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/top_tommath_add_e8_m17_round_even_sticky_p4.v:43$129'.
  created $dff cell `$procdff$519' with positive edge clock.
Creating register for signal `\FpxxAdd.\n4_n2_sign_add' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$520' with positive edge clock.
Creating register for signal `\FpxxAdd.\n4_n0_is_inf' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$521' with positive edge clock.
Creating register for signal `\FpxxAdd.\n4_n0_is_nan' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$522' with positive edge clock.
Creating register for signal `\FpxxAdd.\n3_n2_sign_add' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$523' with positive edge clock.
Creating register for signal `\FpxxAdd.\n3_n0_exp_add' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$524' with positive edge clock.
Creating register for signal `\FpxxAdd.\n3_n0_is_inf' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$525' with positive edge clock.
Creating register for signal `\FpxxAdd.\n3_n0_is_nan' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$526' with positive edge clock.
Creating register for signal `\FpxxAdd.\n3_n0_is_zero' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$527' with positive edge clock.
Creating register for signal `\FpxxAdd.\n2_n0_exp_add' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$528' with positive edge clock.
Creating register for signal `\FpxxAdd.\n2_n0_is_inf' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$529' with positive edge clock.
Creating register for signal `\FpxxAdd.\n2_n0_is_nan' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$530' with positive edge clock.
Creating register for signal `\FpxxAdd.\n2_n0_is_zero' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$531' with positive edge clock.
Creating register for signal `\FpxxAdd.\n1_n0_exp_add' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$532' with positive edge clock.
Creating register for signal `\FpxxAdd.\n1_n0_sign_b_swap' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$533' with positive edge clock.
Creating register for signal `\FpxxAdd.\n1_n0_sign_a_swap' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$534' with positive edge clock.
Creating register for signal `\FpxxAdd.\n1_n0_is_inf' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$535' with positive edge clock.
Creating register for signal `\FpxxAdd.\n1_n0_is_nan' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$536' with positive edge clock.
Creating register for signal `\FpxxAdd.\n1_n0_is_zero' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$537' with positive edge clock.
Creating register for signal `\FpxxAdd.\n4_n0_exp_add' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$538' with positive edge clock.
Creating register for signal `\FpxxAdd.\n4_n3_mant_add' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$539' with positive edge clock.
Creating register for signal `\FpxxAdd.\n4_n0_is_zero' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$540' with positive edge clock.
Creating register for signal `\FpxxAdd.\n3_n2_mant_b_opt_inv' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$541' with positive edge clock.
Creating register for signal `\FpxxAdd.\n3_n2_mant_a_opt_inv' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$542' with positive edge clock.
Creating register for signal `\FpxxAdd.\n2_n1_mant_b_adj' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$543' with positive edge clock.
Creating register for signal `\FpxxAdd.\n2_n1_mant_a_adj' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$544' with positive edge clock.
Creating register for signal `\FpxxAdd.\n2_n0_sign_b_swap' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$545' with positive edge clock.
Creating register for signal `\FpxxAdd.\n2_n0_sign_a_swap' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$546' with positive edge clock.
Creating register for signal `\FpxxAdd.\n1_n0_exp_diff_ovfl' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$547' with positive edge clock.
Creating register for signal `\FpxxAdd.\n1_n0_exp_diff' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$548' with positive edge clock.
Creating register for signal `\FpxxAdd.\n1_n0_mant_b_swap' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$549' with positive edge clock.
Creating register for signal `\FpxxAdd.\n1_n0_mant_a_swap' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
  created $dff cell `$procdff$550' with positive edge clock.
Creating register for signal `\FpxxAdd.\n4_valid' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:917$127'.
  created $adff cell `$procdff$553' with positive edge clock and positive level reset.
Creating register for signal `\FpxxAdd.\n3_valid' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:917$127'.
  created $adff cell `$procdff$556' with positive edge clock and positive level reset.
Creating register for signal `\FpxxAdd.\n2_valid' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:917$127'.
  created $adff cell `$procdff$559' with positive edge clock and positive level reset.
Creating register for signal `\FpxxAdd.\n1_valid' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:917$127'.
  created $adff cell `$procdff$562' with positive edge clock and positive level reset.

3.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\top_tommath_add_e8_m17_round_even_sticky_p4.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/top_tommath_add_e8_m17_round_even_sticky_p4.v:43$129'.
Removing empty process `top_tommath_add_e8_m17_round_even_sticky_p4.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/top_tommath_add_e8_m17_round_even_sticky_p4.v:43$129'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:931$128'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:917$127'.
Found and cleaned up 2 empty switches in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:886$120'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:886$120'.
Found and cleaned up 2 empty switches in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:874$115'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:874$115'.
Found and cleaned up 2 empty switches in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:862$114'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:862$114'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:851$110'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:851$110'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:843$108'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:843$108'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:829$102'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:829$102'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:820$99'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:820$99'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:812$97'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:812$97'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:798$96'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:798$96'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:782$95'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:782$95'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:766$94'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:766$94'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:750$93'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:750$93'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:734$92'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:734$92'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:716$91'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:716$91'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:700$90'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:700$90'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:684$89'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:684$89'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:668$88'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:668$88'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:652$87'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:652$87'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:635$86'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:635$86'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:619$85'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:619$85'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:603$84'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:603$84'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:585$83'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:585$83'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:569$82'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:569$82'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:553$81'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:553$81'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:537$80'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:537$80'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:520$79'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:520$79'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:504$78'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:504$78'.
Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:488$77'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:488$77'.
Found and cleaned up 2 empty switches in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:465$73'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:465$73'.
Found and cleaned up 2 empty switches in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:453$71'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:453$71'.
Found and cleaned up 2 empty switches in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:441$70'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:441$70'.
Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:431$60'.
Cleaned up 38 empty switches.

3.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.
<suppressed ~17 debug messages>

3.5. Executing CHECK pass (checking for obvious problems).
Checking module top_tommath_add_e8_m17_round_even_sticky_p4...
Checking module FpxxAdd...
Found and reported 0 problems.

3.6. Executing FLATTEN pass (flatten design).
Keeping top_tommath_add_e8_m17_round_even_sticky_p4.u_dut (found keep_hierarchy attribute).

3.7. Executing TRIBUF pass.

3.8. Executing DEMINOUT pass (demote inout ports to input or output).

3.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.

3.10. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..
Removed 1 unused cells and 222 unused wires.
<suppressed ~4 debug messages>

3.11. Executing CHECK pass (checking for obvious problems).
Checking module top_tommath_add_e8_m17_round_even_sticky_p4...
Checking module FpxxAdd...
Found and reported 0 problems.

3.12. Executing OPT pass (performing simple optimizations).

3.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.
<suppressed ~4 debug messages>

3.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 8 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 202 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Computing hashes of 195 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
<suppressed ~21 debug messages>
Removed a total of 7 cells.

3.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top_tommath_add_e8_m17_round_even_sticky_p4..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \FpxxAdd..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $procmux$400: \n4_n3_mant_add [21:2] -> { 1'1 \n4_n3_mant_add [20:2] }
      Replacing known input bits on port A of cell $procmux$394: { 1'0 \n5_mant_renormed [20:3] } -> { 1'0 \n5_mant_renormed [20:4] 1'0 }
      Replacing known input bits on port A of cell $ternary$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:321$9: \_zz_n1__mant_b_shift_2 -> { 1'0 \_zz_n1__mant_b_shift_2 [4:0] }
  Analyzing evaluation results.
    dead port 1/2 on $mux $procmux$510.
    dead port 1/2 on $mux $procmux$501.
    dead port 1/2 on $mux $procmux$492.
    dead port 2/3 on $pmux $procmux$413.
    dead port 2/3 on $pmux $procmux$409.
    dead port 1/2 on $mux $procmux$385.
    dead port 1/2 on $mux $procmux$377.
    dead port 1/2 on $mux $procmux$365.
Removed 8 multiplexer ports.
<suppressed ~118 debug messages>

3.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top_tommath_add_e8_m17_round_even_sticky_p4.
  Optimizing cells in module \FpxxAdd.
Performed a total of 0 changes.

3.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 8 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 189 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Removed a total of 0 cells.

3.12.6. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $procdff$544 ($dff) from module FpxxAdd.
Setting constant 0-bit at position 1 on $procdff$544 ($dff) from module FpxxAdd.
Setting constant 0-bit at position 2 on $procdff$544 ($dff) from module FpxxAdd.
Setting constant 0-bit at position 21 on $procdff$544 ($dff) from module FpxxAdd.

3.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..
Removed 0 unused cells and 17 unused wires.
<suppressed ~1 debug messages>

3.12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.

3.12.9. Rerunning OPT passes. (Maybe there is more to do..)

3.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top_tommath_add_e8_m17_round_even_sticky_p4..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \FpxxAdd..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~110 debug messages>

3.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top_tommath_add_e8_m17_round_even_sticky_p4.
  Optimizing cells in module \FpxxAdd.
Performed a total of 0 changes.

3.12.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 8 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 189 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Removed a total of 0 cells.

3.12.13. Executing OPT_DFF pass (perform DFF optimizations).

3.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..

3.12.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.

3.12.16. Finished fast OPT passes. (There is nothing left to do.)

3.13. Executing FSM pass (extract and optimize FSM).

3.13.1. Executing FSM_DETECT pass (finding FSMs in design).

3.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).

3.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).

3.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..

3.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).

3.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

3.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

3.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

3.14. Executing OPT pass (performing simple optimizations).

3.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.

3.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 8 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 189 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Removed a total of 0 cells.

3.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top_tommath_add_e8_m17_round_even_sticky_p4..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \FpxxAdd..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~110 debug messages>

3.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top_tommath_add_e8_m17_round_even_sticky_p4.
  Optimizing cells in module \FpxxAdd.
Performed a total of 0 changes.

3.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 8 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 189 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Removed a total of 0 cells.

3.14.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $procdff$517 ($dff) from module top_tommath_add_e8_m17_round_even_sticky_p4 (D = \in_valid_i, Q = \in_valid_r, rval = 1'0).
Adding SRST signal on $procdff$519 ($dff) from module top_tommath_add_e8_m17_round_even_sticky_p4 (D = \dut_valid, Q = \out_valid_r, rval = 1'0).
Adding SRST signal on $procdff$541 ($dff) from module FpxxAdd (D = $2\n2__mant_b_opt_inv[22:0] [0], Q = \n3_n2_mant_b_opt_inv [0], rval = 1'0).
Adding SRST signal on $procdff$542 ($dff) from module FpxxAdd (D = $2\n2__mant_a_opt_inv[22:0] [0], Q = \n3_n2_mant_a_opt_inv [0], rval = 1'0).
Adding SRST signal on $procdff$542 ($dff) from module FpxxAdd (D = { $not$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:460$72_Y [21] $not$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:460$72_Y [2:0] }, Q = { \n3_n2_mant_a_opt_inv [22] \n3_n2_mant_a_opt_inv [3:1] }, rval = 4'0000).
Adding SRST signal on $procdff$543 ($dff) from module FpxxAdd (D = { \_zz_n1__mant_b_shift_3 [20:1] \n1__mant_b_shift [0] }, Q = \n2_n1_mant_b_adj [20:0], rval = 21'000000000000000000000).

3.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..
Removed 2 unused cells and 2 unused wires.
<suppressed ~3 debug messages>

3.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.

3.14.9. Rerunning OPT passes. (Maybe there is more to do..)

3.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top_tommath_add_e8_m17_round_even_sticky_p4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \FpxxAdd..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~108 debug messages>

3.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top_tommath_add_e8_m17_round_even_sticky_p4.
  Optimizing cells in module \FpxxAdd.
Performed a total of 0 changes.

3.14.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 6 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 194 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Removed a total of 0 cells.

3.14.13. Executing OPT_DFF pass (perform DFF optimizations).

3.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..

3.14.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.

3.14.16. Finished fast OPT passes. (There is nothing left to do.)

3.15. Executing WREDUCE pass (reducing word size of cells).
Removed top 4 bits (of 9) from mux cell FpxxAdd.$ternary$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:309$1 ($mux).
Removed top 3 bits (of 6) from port B of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:314$5 ($sub).
Converting cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:314$5 ($sub) from signed to unsigned.
Removed top 1 bits (of 6) from port A of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:314$5 ($sub).
Removed top 1 bits (of 3) from port B of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:314$5 ($sub).
Removed top 31 bits (of 32) from port B of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:316$6 ($sub).
Removed top 14 bits (of 32) from port Y of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:316$6 ($sub).
Removed top 14 bits (of 32) from port A of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:316$6 ($sub).
Removed top 31 bits (of 32) from port A of cell FpxxAdd.$sshl$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:318$7 ($sshl).
Removed top 14 bits (of 32) from port Y of cell FpxxAdd.$sshl$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:318$7 ($sshl).
Removed top 5 bits (of 6) from port B of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:319$8 ($add).
Removed top 1 bits (of 6) from port Y of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:319$8 ($add).
Removed top 1 bits (of 6) from port A of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:319$8 ($add).
Removed top 1 bits (of 6) from mux cell FpxxAdd.$ternary$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:321$9 ($mux).
Removed top 1 bits (of 6) from port Y of cell FpxxAdd.$not$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:322$10 ($not).
Removed top 1 bits (of 6) from port A of cell FpxxAdd.$not$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:322$10 ($not).
Removed top 1 bits (of 20) from port A of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:392$12 ($add).
Removed top 19 bits (of 20) from port B of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:392$12 ($add).
Removed top 3 bits (of 9) from port B of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:393$13 ($sub).
Converting cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:393$13 ($sub) from signed to unsigned.
Removed top 1 bits (of 9) from port A of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:393$13 ($sub).
Removed top 1 bits (of 6) from port B of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:393$13 ($sub).
Converting cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:420$49 ($sub) from signed to unsigned.
Removed top 1 bits (of 9) from port A of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:420$49 ($sub).
Removed top 1 bits (of 9) from port B of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:420$49 ($sub).
Removed top 8 bits (of 9) from port A of cell FpxxAdd.$le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:422$51 ($le).
Removed top 3 bits (of 9) from port A of cell FpxxAdd.$lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:426$55 ($lt).
Removed top 3 bits (of 8) from port A of cell FpxxAdd.$lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:426$56 ($lt).
Removed top 4 bits (of 6) from port B of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:436$63 ($add).
Removed top 5 bits (of 6) from port B of cell FpxxAdd.$lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:437$64 ($lt).
Removed cell FpxxAdd.$ternary$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:439$68 ($mux).
Removed top 1 bits (of 22) from port A of cell FpxxAdd.$not$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:460$72 ($not).
Removed top 1 bits (of 22) from port B of cell FpxxAdd.$le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:477$75 ($le).
Removed top 7 bits (of 8) from port B of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:831$103 ($add).
Removed top 1 bits (of 19) from port A of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:845$109 ($add).
Removed top 18 bits (of 19) from port B of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:845$109 ($add).
Removed top 7 bits (of 9) from port B of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:860$112 ($add).
Removed top 3 bits (of 8) from port B of cell FpxxAdd.$eq$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:861$113 ($eq).
Removed top 1 bits (of 6) from mux cell FpxxAdd.$procmux$409 ($mux).
Removed top 1 bits (of 4) from mux cell FpxxAdd.$procmux$413 ($mux).
Removed top 1 bits (of 23) from mux cell FpxxAdd.$procmux$504 ($mux).
Removed top 1 bits (of 23) from mux cell FpxxAdd.$procmux$498 ($mux).
Removed top 1 bits (of 23) from wire FpxxAdd.$2\n2__mant_a_opt_inv[22:0].
Removed top 2 bits (of 5) from wire FpxxAdd._zz_switch_Misc_l241_48.
Removed top 1 bits (of 4) from wire FpxxAdd._zz_switch_Misc_l241_47.
Removed top 1 bits (of 23) from wire FpxxAdd.n2__mant_a_opt_inv.
Removed top 1 bits (of 22) from wire FpxxAdd.n1__mant_b_shift.
Removed top 1 bits (of 22) from wire FpxxAdd.n2_n1_mant_a_adj.
Removed top 1 bits (of 23) from wire FpxxAdd.n2_mant_a_opt_inv.
Removed top 1 bits (of 2) from wire FpxxAdd._zz_n5_exp_add_m_lz_6.
Removed top 8 bits (of 9) from wire FpxxAdd._zz_n5_exp_add_m_lz_5.
Removed top 1 bits (of 4) from wire FpxxAdd._zz__zz_n4__lz_1.
Removed top 1 bits (of 6) from wire FpxxAdd._zz_n1__mant_b_shift_11.
Removed top 1 bits (of 6) from wire FpxxAdd._zz_n1__mant_b_shift_10.
Removed top 14 bits (of 32) from wire FpxxAdd._zz_n1__mant_b_shift_7.

3.16. Executing PEEPOPT pass (run peephole optimizers).

3.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..
Removed 0 unused cells and 13 unused wires.
<suppressed ~1 debug messages>

3.18. Executing SHARE pass (SAT-based resource sharing).

3.19. Executing TECHMAP pass (map to technology primitives).

3.19.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

3.19.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~166 debug messages>

3.20. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.

3.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..

3.22. Executing TECHMAP pass (map to technology primitives).

3.22.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

3.22.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

3.23. Executing TECHMAP pass (map to technology primitives).

3.23.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v
Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
Generating RTLIL representation for module `$__MUL18X18'.
Successfully finished Verilog frontend.

3.23.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>

3.24. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top_tommath_add_e8_m17_round_even_sticky_p4:
  created 0 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module FpxxAdd:
  creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:860$112 ($add).
  creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:845$109 ($add).
  creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:831$103 ($add).
  creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:436$63 ($add).
  creating $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:421$50 ($sub).
  creating $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:420$49 ($sub).
  creating $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:393$13 ($sub).
  creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:392$12 ($add).
  creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:325$11 ($add).
  creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:319$8 ($add).
  creating $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:316$6 ($sub).
  creating $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:314$5 ($sub).
  merging $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:314$5 into $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:436$63.
  merging $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:393$13 into $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:860$112.
  creating $alu model for $macc $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:319$8.
  creating $alu model for $macc $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:325$11.
  creating $alu model for $macc $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:392$12.
  creating $alu model for $macc $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:316$6.
  creating $alu model for $macc $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:420$49.
  creating $alu model for $macc $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:421$50.
  creating $alu model for $macc $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:831$103.
  creating $alu model for $macc $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:845$109.
  creating $macc cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:436$63: $auto$alumacc.cc:382:replace_macc$589
  creating $macc cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:860$112: $auto$alumacc.cc:382:replace_macc$590
  creating $alu model for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:881$116 ($lt): new $alu
  creating $alu model for $le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:477$75 ($le): new $alu
  creating $alu model for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:437$64 ($lt): new $alu
  creating $alu model for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:426$56 ($lt): new $alu
  creating $alu model for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:426$55 ($lt): new $alu
  creating $alu model for $le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:422$51 ($le): new $alu
  creating $alu cell for $le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:422$51: $auto$alumacc.cc:512:replace_alu$597
  creating $alu cell for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:426$55: $auto$alumacc.cc:512:replace_alu$608
  creating $alu cell for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:426$56: $auto$alumacc.cc:512:replace_alu$615
  creating $alu cell for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:437$64: $auto$alumacc.cc:512:replace_alu$620
  creating $alu cell for $le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:477$75: $auto$alumacc.cc:512:replace_alu$627
  creating $alu cell for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:881$116: $auto$alumacc.cc:512:replace_alu$636
  creating $alu cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:845$109: $auto$alumacc.cc:512:replace_alu$641
  creating $alu cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:831$103: $auto$alumacc.cc:512:replace_alu$644
  creating $alu cell for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:421$50: $auto$alumacc.cc:512:replace_alu$647
  creating $alu cell for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:420$49: $auto$alumacc.cc:512:replace_alu$650
  creating $alu cell for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:316$6: $auto$alumacc.cc:512:replace_alu$653
  creating $alu cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:392$12: $auto$alumacc.cc:512:replace_alu$656
  creating $alu cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:325$11: $auto$alumacc.cc:512:replace_alu$659
  creating $alu cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:319$8: $auto$alumacc.cc:512:replace_alu$662
  created 14 $alu and 2 $macc cells.

3.25. Executing OPT pass (performing simple optimizations).

3.25.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.
<suppressed ~3 debug messages>

3.25.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 6 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 205 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Removed a total of 0 cells.

3.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top_tommath_add_e8_m17_round_even_sticky_p4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \FpxxAdd..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~106 debug messages>

3.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top_tommath_add_e8_m17_round_even_sticky_p4.
  Optimizing cells in module \FpxxAdd.
    New input vector for $reduce_or cell $auto$opt_dff.cc:277:combine_resets$571: { \when_FpxxAdd_l89 $auto$rtlil.cc:3255:Not$631 $auto$rtlil.cc:3258:ReduceAnd$633 }
  Optimizing cells in module \FpxxAdd.
Performed a total of 1 changes.

3.25.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 6 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 205 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Removed a total of 0 cells.

3.25.6. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$574 ($dff) from module FpxxAdd.

3.25.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..
Removed 3 unused cells and 14 unused wires.
<suppressed ~7 debug messages>

3.25.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.

3.25.9. Rerunning OPT passes. (Maybe there is more to do..)

3.25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top_tommath_add_e8_m17_round_even_sticky_p4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \FpxxAdd..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port A of cell $ternary$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:437$65: \_zz_n1__mant_b_shift -> { 1'0 \_zz_n1__mant_b_shift [4:0] }
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~106 debug messages>

3.25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top_tommath_add_e8_m17_round_even_sticky_p4.
  Optimizing cells in module \FpxxAdd.
Performed a total of 0 changes.

3.25.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 6 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 200 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Removed a total of 0 cells.

3.25.13. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:337:slice$567 ($dff) from module FpxxAdd (D = $not$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:470$74_Y [21], Q = \n3_n2_mant_b_opt_inv [22], rval = 1'0).

3.25.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..

3.25.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.

3.25.16. Rerunning OPT passes. (Maybe there is more to do..)

3.25.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top_tommath_add_e8_m17_round_even_sticky_p4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \FpxxAdd..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~106 debug messages>

3.25.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top_tommath_add_e8_m17_round_even_sticky_p4.
  Optimizing cells in module \FpxxAdd.
Performed a total of 0 changes.

3.25.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 6 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 203 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Removed a total of 0 cells.

3.25.20. Executing OPT_DFF pass (perform DFF optimizations).

3.25.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..

3.25.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.

3.25.23. Finished fast OPT passes. (There is nothing left to do.)

3.26. Executing MEMORY pass.

3.26.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

3.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

3.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).

3.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

3.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).

3.26.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..

3.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

3.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

3.26.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..

3.26.10. Executing MEMORY_COLLECT pass (generating $mem cells).

3.27. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..

3.28. Executing MEMORY_LIBMAP pass (mapping memories to cells).

3.29. Executing TECHMAP pass (map to technology primitives).

3.29.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v
Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

3.29.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v
Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
Generating RTLIL representation for module `$__DP16KD_'.
Generating RTLIL representation for module `$__PDPW16KD_'.
Successfully finished Verilog frontend.

3.29.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

3.30. Executing OPT pass (performing simple optimizations).

3.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.
<suppressed ~27 debug messages>

3.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 6 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 206 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Removed a total of 0 cells.

3.30.3. Executing OPT_DFF pass (perform DFF optimizations).

3.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..
Removed 0 unused cells and 7 unused wires.
<suppressed ~1 debug messages>

3.30.5. Finished fast OPT passes.

3.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

3.32. Executing OPT pass (performing simple optimizations).

3.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.

3.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 6 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 206 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Removed a total of 0 cells.

3.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top_tommath_add_e8_m17_round_even_sticky_p4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \FpxxAdd..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~106 debug messages>

3.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top_tommath_add_e8_m17_round_even_sticky_p4.
  Optimizing cells in module \FpxxAdd.
    Consolidated identical input bits for $mux cell $procmux$498:
      Old ports: A={ $auto$opt_expr.cc:206:group_cell_inputs$809 4'1111 }, B={ \n2_n1_mant_a_adj [20:3] 4'0001 }, Y=$2\n2__mant_a_opt_inv[22:0]
      New ports: A={ $auto$opt_expr.cc:206:group_cell_inputs$809 1'1 }, B={ \n2_n1_mant_a_adj [20:3] 1'0 }, Y={ $2\n2__mant_a_opt_inv[22:0] [21:4] $2\n2__mant_a_opt_inv[22:0] [1] }
      New connections: { $2\n2__mant_a_opt_inv[22:0] [3:2] $2\n2__mant_a_opt_inv[22:0] [0] } = { $2\n2__mant_a_opt_inv[22:0] [1] $2\n2__mant_a_opt_inv[22:0] [1] 1'1 }
    Consolidated identical input bits for $mux cell $procmux$489:
      Old ports: A={ 1'0 \n2_n1_mant_b_adj [20:0] 1'1 }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$813 1'1 }, Y=$2\n2__mant_b_opt_inv[22:0]
      New ports: A={ 1'0 \n2_n1_mant_b_adj [20:0] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$813 }, Y=$2\n2__mant_b_opt_inv[22:0] [22:1]
      New connections: $2\n2__mant_b_opt_inv[22:0] [0] = 1'1
    Consolidated identical input bits for $mux cell $ternary$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:437$65:
      Old ports: A={ 1'0 \_zz_n1__mant_b_shift [4:0] }, B=6'000000, Y=\_zz_n1__mant_b_shift_1
      New ports: A=\_zz_n1__mant_b_shift [4:0], B=5'00000, Y=\_zz_n1__mant_b_shift_1 [4:0]
      New connections: \_zz_n1__mant_b_shift_1 [5] = 1'0
  Optimizing cells in module \FpxxAdd.
    Consolidated identical input bits for $mux cell $procmux$504:
      Old ports: A=$2\n2__mant_a_opt_inv[22:0], B={ \n2_n1_mant_a_adj [20:3] 4'0000 }, Y=\n2__mant_a_opt_inv
      New ports: A={ $2\n2__mant_a_opt_inv[22:0] [21:4] $2\n2__mant_a_opt_inv[22:0] [1] 1'1 }, B={ \n2_n1_mant_a_adj [20:3] 2'00 }, Y={ \n2__mant_a_opt_inv [21:4] \n2__mant_a_opt_inv [1:0] }
      New connections: \n2__mant_a_opt_inv [3:2] = { \n2__mant_a_opt_inv [1] \n2__mant_a_opt_inv [1] }
  Optimizing cells in module \FpxxAdd.
Performed a total of 4 changes.

3.32.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 6 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 206 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Computing hashes of 205 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

3.32.6. Executing OPT_DFF pass (perform DFF optimizations).

3.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..

3.32.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.
<suppressed ~5 debug messages>

3.32.9. Rerunning OPT passes. (Maybe there is more to do..)

3.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top_tommath_add_e8_m17_round_even_sticky_p4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \FpxxAdd..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~100 debug messages>

3.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top_tommath_add_e8_m17_round_even_sticky_p4.
  Optimizing cells in module \FpxxAdd.
Performed a total of 0 changes.

3.32.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 6 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 202 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Removed a total of 0 cells.

3.32.13. Executing OPT_DFF pass (perform DFF optimizations).

3.32.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..
Removed 1 unused cells and 4 unused wires.
<suppressed ~4 debug messages>

3.32.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.

3.32.16. Rerunning OPT passes. (Maybe there is more to do..)

3.32.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top_tommath_add_e8_m17_round_even_sticky_p4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \FpxxAdd..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~100 debug messages>

3.32.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top_tommath_add_e8_m17_round_even_sticky_p4.
  Optimizing cells in module \FpxxAdd.
Performed a total of 0 changes.

3.32.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 6 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 200 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Removed a total of 0 cells.

3.32.20. Executing OPT_DFF pass (perform DFF optimizations).

3.32.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..

3.32.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.

3.32.23. Finished fast OPT passes. (There is nothing left to do.)

3.33. Executing TECHMAP pass (map to technology primitives).

3.33.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.

3.33.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v
Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
Generating RTLIL representation for module `\_80_ccu2c_alu'.
Successfully finished Verilog frontend.

3.33.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $sdff.
Using template $paramod$448756c9a9dfaa49080ce4b90c6cc182883e181f\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$constmap:47ad3f30f11abef50a599afceddf818b1cd3de7f$paramod$e160bf36051cb740cdd81c25dc8561b771f912c6\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshl.
Using template $paramod$19d71cf4a78a3e7142dac3f236c406c8947b8115\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$constmap:41715883e656ec5e9b82df45c08cea6977e34c9f$paramod$34fe39aefe07ddaf670239b44fc1e61d9f12c3b0\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshl.
Using template $paramod$bc4de955eaa5a15b4733e1ebbba1279919eb6e1a\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$4ccbe221165818e15f326ddee3d1183c7924e12f\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$5149e1e231cbdcfb7362de2a8603e2def0b11576\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$b18e16801adf491a64caa0542270798e5d4ac6b6\_80_ccu2c_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_and.
Using template $paramod$f252d71e91501157ef4fbf06e08bbe0b6195ef1a\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$cc48387a3f2cae79a81035f3d5a9b4758cb77854\_80_ccu2c_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$b566a1c74c98c77ef2d871a6dafea3b87badd8b1\_80_ccu2c_alu for cells of type $alu.
Using template $paramod$003256218b736a5f72fe70a6e5006b2214b99da4\_80_ccu2c_alu for cells of type $alu.
Using extmapper maccmap for cells of type $macc_v2.
  add \n5_n4_exp_add_adj (8 bits, unsigned)
  add { 1'0 \_zz_n5_mant_rounded [18] } (2 bits, signed)
  sub \n5_n4_lz (5 bits, unsigned)
  packed 1 (1) bits / 1 words into adder tree
  add \n1_n0_exp_diff (5 bits, unsigned)
  add 6'111110 (6 bits, unsigned)
Using template $paramod$constmap:de125f76800eb36e56139929eaff353f45ddb25e$paramod$dc7c9b278aea38f32948308ec2005774b6918247\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $logic_or.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $pmux.
Using extmapper simplemap for cells of type $adff.
Using template $paramod$00298f3f8094950cb9a5ff2fda48d0d8bde8806c\_80_ccu2c_alu for cells of type $alu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000001001 for cells of type $fa.
Using template $paramod$d2fa05d38998afabc6d4f34471305d0af4b8b2df\_80_ccu2c_alu for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using extmapper simplemap for cells of type $or.
No more expansions possible.
<suppressed ~1865 debug messages>

3.34. Executing OPT pass (performing simple optimizations).

3.34.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.
<suppressed ~827 debug messages>

3.34.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 81 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 1778 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Computing hashes of 1688 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Computing hashes of 1677 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Computing hashes of 1673 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Computing hashes of 1671 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Computing hashes of 1669 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Computing hashes of 1667 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
<suppressed ~333 debug messages>
Removed a total of 111 cells.

3.34.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:337:slice$1889 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:312$3.$10\buffer[20:0] [20], Q = \n2_n1_mant_b_adj [20], rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$1874 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:312$3.$10\buffer[20:0] [5], Q = \n2_n1_mant_b_adj [5], rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$1875 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:312$3.$10\buffer[20:0] [6], Q = \n2_n1_mant_b_adj [6], rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$1876 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:312$3.$10\buffer[20:0] [7], Q = \n2_n1_mant_b_adj [7], rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$1877 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:312$3.$10\buffer[20:0] [8], Q = \n2_n1_mant_b_adj [8], rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$1878 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:312$3.$10\buffer[20:0] [9], Q = \n2_n1_mant_b_adj [9], rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$1879 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:312$3.$10\buffer[20:0] [10], Q = \n2_n1_mant_b_adj [10], rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$1880 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:312$3.$10\buffer[20:0] [11], Q = \n2_n1_mant_b_adj [11], rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$1881 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:312$3.$10\buffer[20:0] [12], Q = \n2_n1_mant_b_adj [12], rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$1882 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:312$3.$11\buffer[20:0] [5], Q = \n2_n1_mant_b_adj [13], rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$1883 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:312$3.$11\buffer[20:0] [6], Q = \n2_n1_mant_b_adj [14], rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$1884 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:312$3.$11\buffer[20:0] [7], Q = \n2_n1_mant_b_adj [15], rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$1885 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:312$3.$10\buffer[20:0] [16], Q = \n2_n1_mant_b_adj [16], rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$1886 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:312$3.$10\buffer[20:0] [17], Q = \n2_n1_mant_b_adj [17], rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$1887 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:312$3.$10\buffer[20:0] [18], Q = \n2_n1_mant_b_adj [18], rval = 1'0).
Adding SRST signal on $auto$ff.cc:337:slice$1888 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:312$3.$10\buffer[20:0] [19], Q = \n2_n1_mant_b_adj [19], rval = 1'0).

3.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..
Removed 348 unused cells and 972 unused wires.
<suppressed ~360 debug messages>

3.34.5. Rerunning OPT passes. (Removed registers in this run.)

3.34.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.

3.34.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 81 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 1338 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Computing hashes of 1324 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Computing hashes of 1322 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
<suppressed ~48 debug messages>
Removed a total of 16 cells.

3.34.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:337:slice$5066 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/src/tommath_add_e8_m17_round_even_sticky_p4.v:312$3.$11\buffer[20:0] [8], Q = \n2_n1_mant_b_adj [16], rval = 1'0).

3.34.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..
Removed 1 unused cells and 17 unused wires.
<suppressed ~2 debug messages>

3.34.10. Rerunning OPT passes. (Removed registers in this run.)

3.34.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.

3.34.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 81 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 1322 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Removed a total of 0 cells.

3.34.13. Executing OPT_DFF pass (perform DFF optimizations).

3.34.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..

3.34.15. Finished fast OPT passes.

3.35. Executing ABC pass (technology mapping using ABC).

3.35.1. Summary of detected clock domains:
  3 cells in clk=\clk, en={ }, arst={ }, srst=\rst
  78 cells in clk=\clk, en={ }, arst={ }, srst={ }

3.35.2. Extracting gate netlist of module `\top_tommath_add_e8_m17_round_even_sticky_p4' to `<abc-temp-dir>/input.blif'..
Found matching posedge clock domain: \clk, synchronously reset by \rst

3.35.3. Extracting gate netlist of module `\top_tommath_add_e8_m17_round_even_sticky_p4' to `<abc-temp-dir>/input.blif'..
Found matching posedge clock domain: \clk

3.35.3.1. Executed ABC.
Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 2 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: + strash 
ABC: + &get -n 
ABC: + &fraig -x 
ABC: + &put 
ABC: + scorr 
ABC: + dc2 
ABC: + dretime 
ABC: + retime -o -D 1 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf -D 1 
ABC: + &put 
ABC: + write_blif <abc-temp-dir>/output.blif 
ABC: 
ABC: YOSYS_ABC_DONE 

3.35.3.2. Re-integrating ABC results.
ABC RESULTS:               BUF cells:        4
ABC RESULTS:               DFF cells:        2
ABC RESULTS:        internal signals:        0
ABC RESULTS:           input signals:        2
ABC RESULTS:          output signals:        2
Removing temp directory.

3.35.3.1. Executed ABC.
Extracted 78 gates and 156 wires to a netlist network with 78 inputs and 78 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: + strash 
ABC: + &get -n 
ABC: Warning: 78 registers in this network have don't-care init values.
ABC: The don't-care are assumed to be 0. The result may not verify.
ABC: Use command "print_latch" to see the init values of registers.
ABC: Use command "zero" to convert or "init" to change the values.
ABC: + &fraig -x 
ABC: + &put 
ABC: + scorr 
ABC: + dc2 
ABC: + dretime 
ABC: + retime -o -D 1 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf -D 1 
ABC: + &put 
ABC: + write_blif <abc-temp-dir>/output.blif 
ABC: 
ABC: YOSYS_ABC_DONE 

3.35.3.2. Re-integrating ABC results.
ABC RESULTS:               BUF cells:      156
ABC RESULTS:               DFF cells:       78
ABC RESULTS:        internal signals:        0
ABC RESULTS:           input signals:       78
ABC RESULTS:          output signals:       78
Removing temp directory.

3.35.4. Summary of detected clock domains:
  4 cells in clk=\clk, en={ }, arst=\reset, srst={ }
  3 cells in clk=\clk, en={ }, arst={ }, srst=$auto$opt_dff.cc:275:combine_resets$670
  3 cells in clk=\clk, en={ }, arst={ }, srst=\when_FpxxAdd_l89
  35 cells in clk=\clk, en={ }, arst={ }, srst=\n1_n0_exp_diff_ovfl
  14 cells in clk=\clk, en={ }, arst={ }, srst=$auto$opt_dff.cc:275:combine_resets$5046
  4 cells in clk=\clk, en={ }, arst={ }, srst=$auto$opt_dff.cc:275:combine_resets$5087
  55 cells in clk=\clk, en={ }, arst={ }, srst=$auto$opt_dff.cc:275:combine_resets$5001
  2 cells in clk=\clk, en={ }, arst={ }, srst=$auto$opt_dff.cc:275:combine_resets$570
  1202 cells in clk=\clk, en={ }, arst={ }, srst={ }

3.35.5. Extracting gate netlist of module `\FpxxAdd' to `<abc-temp-dir>/input.blif'..
Found matching posedge clock domain: \clk, asynchronously reset by \reset

3.35.6. Extracting gate netlist of module `\FpxxAdd' to `<abc-temp-dir>/input.blif'..
Found matching posedge clock domain: \clk, synchronously reset by $auto$opt_dff.cc:275:combine_resets$670

3.35.7. Extracting gate netlist of module `\FpxxAdd' to `<abc-temp-dir>/input.blif'..
Found matching posedge clock domain: \clk, synchronously reset by \when_FpxxAdd_l89

3.35.8. Extracting gate netlist of module `\FpxxAdd' to `<abc-temp-dir>/input.blif'..
Found matching posedge clock domain: \clk, synchronously reset by \n1_n0_exp_diff_ovfl

3.35.9. Extracting gate netlist of module `\FpxxAdd' to `<abc-temp-dir>/input.blif'..
Found matching posedge clock domain: \clk, synchronously reset by $auto$opt_dff.cc:275:combine_resets$5046

3.35.10. Extracting gate netlist of module `\FpxxAdd' to `<abc-temp-dir>/input.blif'..
Found matching posedge clock domain: \clk, synchronously reset by $auto$opt_dff.cc:275:combine_resets$5087

3.35.11. Extracting gate netlist of module `\FpxxAdd' to `<abc-temp-dir>/input.blif'..
Found matching posedge clock domain: \clk, synchronously reset by $auto$opt_dff.cc:275:combine_resets$5001

3.35.12. Extracting gate netlist of module `\FpxxAdd' to `<abc-temp-dir>/input.blif'..
Found matching posedge clock domain: \clk, synchronously reset by $auto$opt_dff.cc:275:combine_resets$570

3.35.13. Extracting gate netlist of module `\FpxxAdd' to `<abc-temp-dir>/input.blif'..
Found matching posedge clock domain: \clk

3.35.13.1. Executed ABC.
Extracted 4 gates and 5 wires to a netlist network with 1 inputs and 1 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: + strash 
ABC: + &get -n 
ABC: + &fraig -x 
ABC: + &put 
ABC: + scorr 
ABC: + dc2 
ABC: + dretime 
ABC: + retime -o -D 1 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf -D 1 
ABC: + &put 
ABC: + write_blif <abc-temp-dir>/output.blif 
ABC: 
ABC: YOSYS_ABC_DONE 

3.35.13.2. Re-integrating ABC results.
ABC RESULTS:               BUF cells:        5
ABC RESULTS:               DFF cells:        4
ABC RESULTS:        internal signals:        3
ABC RESULTS:           input signals:        1
ABC RESULTS:          output signals:        1
Removing temp directory.

3.35.13.1. Executed ABC.
Extracted 3 gates and 6 wires to a netlist network with 2 inputs and 2 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: + strash 
ABC: + &get -n 
ABC: + &fraig -x 
ABC: + &put 
ABC: + scorr 
ABC: + dc2 
ABC: + dretime 
ABC: + retime -o -D 1 
ABC: Abc_NtkRetimeInitialValues(): The problem is unsatisfiable. DC latch values are used.
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf -D 1 
ABC: + &put 
ABC: + write_blif <abc-temp-dir>/output.blif 
ABC: 
ABC: YOSYS_ABC_DONE 

3.35.13.2. Re-integrating ABC results.
ABC RESULTS:               ONE cells:        1
ABC RESULTS:             ORNOT cells:        1
ABC RESULTS:        internal signals:        2
ABC RESULTS:           input signals:        2
ABC RESULTS:          output signals:        2
Removing temp directory.

3.35.13.1. Executed ABC.
Extracted 2 gates and 4 wires to a netlist network with 1 inputs and 2 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: + strash 
ABC: + &get -n 
ABC: + &fraig -x 
ABC: + &put 
ABC: + scorr 
ABC: + dc2 
ABC: + dretime 
ABC: + retime -o -D 1 
ABC: Abc_NtkRetimeInitialValues(): The problem is unsatisfiable. DC latch values are used.
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf -D 1 
ABC: + &put 
ABC: + write_blif <abc-temp-dir>/output.blif 
ABC: 
ABC: YOSYS_ABC_DONE 

3.35.13.2. Re-integrating ABC results.
ABC RESULTS:               NOT cells:        1
ABC RESULTS:               ONE cells:        1
ABC RESULTS:        internal signals:        1
ABC RESULTS:           input signals:        1
ABC RESULTS:          output signals:        2
Removing temp directory.

3.35.13.1. Executed ABC.
Extracted 34 gates and 59 wires to a netlist network with 25 inputs and 15 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: + strash 
ABC: + &get -n 
ABC: + &fraig -x 
ABC: + &put 
ABC: + scorr 
ABC: + dc2 
ABC: + dretime 
ABC: + retime -o -D 1 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf -D 1 
ABC: + &put 
ABC: + write_blif <abc-temp-dir>/output.blif 
ABC: 
ABC: YOSYS_ABC_DONE 

3.35.13.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:        4
ABC RESULTS:            ANDNOT cells:        2
ABC RESULTS:               BUF cells:        8
ABC RESULTS:               DFF cells:        6
ABC RESULTS:              NAND cells:        2
ABC RESULTS:               NOR cells:        9
ABC RESULTS:               NOT cells:        3
ABC RESULTS:              XNOR cells:        1
ABC RESULTS:               XOR cells:        6
ABC RESULTS:        internal signals:       19
ABC RESULTS:           input signals:       25
ABC RESULTS:          output signals:       15
Removing temp directory.

3.35.13.1. Executed ABC.
Extracted 12 gates and 19 wires to a netlist network with 7 inputs and 9 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: + strash 
ABC: + &get -n 
ABC: + &fraig -x 
ABC: + &put 
ABC: + scorr 
ABC: + dc2 
ABC: + dretime 
ABC: + retime -o -D 1 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf -D 1 
ABC: + &put 
ABC: + write_blif <abc-temp-dir>/output.blif 
ABC: 
ABC: YOSYS_ABC_DONE 

3.35.13.2. Re-integrating ABC results.
ABC RESULTS:               BUF cells:        6
ABC RESULTS:               DFF cells:        3
ABC RESULTS:               XOR cells:        6
ABC RESULTS:        internal signals:        3
ABC RESULTS:           input signals:        7
ABC RESULTS:          output signals:        9
Removing temp directory.

3.35.13.1. Executed ABC.
Extracted 4 gates and 7 wires to a netlist network with 3 inputs and 3 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: + strash 
ABC: + &get -n 
ABC: + &fraig -x 
ABC: + &put 
ABC: + scorr 
ABC: + dc2 
ABC: + dretime 
ABC: + retime -o -D 1 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf -D 1 
ABC: + &put 
ABC: + write_blif <abc-temp-dir>/output.blif 
ABC: 
ABC: YOSYS_ABC_DONE 

3.35.13.2. Re-integrating ABC results.
ABC RESULTS:               BUF cells:        2
ABC RESULTS:               DFF cells:        1
ABC RESULTS:               XOR cells:        2
ABC RESULTS:        internal signals:        1
ABC RESULTS:           input signals:        3
ABC RESULTS:          output signals:        3
Removing temp directory.

3.35.13.1. Executed ABC.
Extracted 49 gates and 76 wires to a netlist network with 26 inputs and 37 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: + strash 
ABC: + &get -n 
ABC: + &fraig -x 
ABC: + &put 
ABC: + scorr 
ABC: + dc2 
ABC: + dretime 
ABC: + retime -o -D 1 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf -D 1 
ABC: + &put 
ABC: + write_blif <abc-temp-dir>/output.blif 
ABC: 
ABC: YOSYS_ABC_DONE 

3.35.13.2. Re-integrating ABC results.
ABC RESULTS:            ANDNOT cells:        2
ABC RESULTS:               BUF cells:       23
ABC RESULTS:               DFF cells:       12
ABC RESULTS:               XOR cells:       24
ABC RESULTS:        internal signals:       13
ABC RESULTS:           input signals:       26
ABC RESULTS:          output signals:       37
Removing temp directory.

3.35.13.1. Executed ABC.
Extracted 2 gates and 5 wires to a netlist network with 2 inputs and 2 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: empty
ABC: abc 10> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: + strash 
ABC: + &get -n 
ABC: + &fraig -x 
ABC: + &put 
ABC: + scorr 
ABC: + dc2 
ABC: + dretime 
ABC: + retime -o -D 1 
ABC: Abc_NtkRetimeInitialValues(): The problem is unsatisfiable. DC latch values are used.
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf -D 1 
ABC: + &put 
ABC: + write_blif <abc-temp-dir>/output.blif 
ABC: 
ABC: YOSYS_ABC_DONE 

3.35.13.2. Re-integrating ABC results.
ABC RESULTS:               ONE cells:        1
ABC RESULTS:                OR cells:        1
ABC RESULTS:        internal signals:        1
ABC RESULTS:           input signals:        2
ABC RESULTS:          output signals:        2
Removing temp directory.

3.35.13.1. Executed ABC.
Extracted 1125 gates and 1363 wires to a netlist network with 236 inputs and 216 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: empty
ABC: abc 19> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: + strash 
ABC: + &get -n 
ABC: Warning: 171 registers in this network have don't-care init values.
ABC: The don't-care are assumed to be 0. The result may not verify.
ABC: Use command "print_latch" to see the init values of registers.
ABC: Use command "zero" to convert or "init" to change the values.
ABC: + &fraig -x 
ABC: + &put 
ABC: + scorr 
ABC: + dc2 
ABC: + dretime 
ABC: + retime -o -D 1 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf -D 1 
ABC: + &put 
ABC: + write_blif <abc-temp-dir>/output.blif 
ABC: 
ABC: YOSYS_ABC_DONE 

3.35.13.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:      204
ABC RESULTS:            ANDNOT cells:       40
ABC RESULTS:               BUF cells:      135
ABC RESULTS:               DFF cells:      183
ABC RESULTS:               MUX cells:      199
ABC RESULTS:              NAND cells:      167
ABC RESULTS:               NOR cells:       56
ABC RESULTS:               NOT cells:       35
ABC RESULTS:                OR cells:       47
ABC RESULTS:             ORNOT cells:       31
ABC RESULTS:              XNOR cells:       26
ABC RESULTS:               XOR cells:        2
ABC RESULTS:        internal signals:      911
ABC RESULTS:           input signals:      236
ABC RESULTS:          output signals:      216
Removing temp directory.
Removing global temp directory.

3.36. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..
Removed 3 unused cells and 1471 unused wires.
<suppressed ~184 debug messages>

3.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

3.38. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Computing hashes of 81 cells of `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding duplicate cells in `\top_tommath_add_e8_m17_round_even_sticky_p4'.
Finding identical cells in module `\FpxxAdd'.
Computing hashes of 1164 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
Computing hashes of 1162 cells of `\FpxxAdd'.
Finding duplicate cells in `\FpxxAdd'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

3.39. Executing TECHMAP pass (map to technology primitives).

3.39.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v
Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$_DFF_N_'.
Generating RTLIL representation for module `$_DFF_P_'.
Generating RTLIL representation for module `$_DFFE_NN_'.
Generating RTLIL representation for module `$_DFFE_PN_'.
Generating RTLIL representation for module `$_DFFE_NP_'.
Generating RTLIL representation for module `$_DFFE_PP_'.
Generating RTLIL representation for module `$_DFF_NP0_'.
Generating RTLIL representation for module `$_DFF_NP1_'.
Generating RTLIL representation for module `$_DFF_PP0_'.
Generating RTLIL representation for module `$_DFF_PP1_'.
Generating RTLIL representation for module `$_SDFF_NP0_'.
Generating RTLIL representation for module `$_SDFF_NP1_'.
Generating RTLIL representation for module `$_SDFF_PP0_'.
Generating RTLIL representation for module `$_SDFF_PP1_'.
Generating RTLIL representation for module `$_DFFE_NP0P_'.
Generating RTLIL representation for module `$_DFFE_NP1P_'.
Generating RTLIL representation for module `$_DFFE_PP0P_'.
Generating RTLIL representation for module `$_DFFE_PP1P_'.
Generating RTLIL representation for module `$_DFFE_NP0N_'.
Generating RTLIL representation for module `$_DFFE_NP1N_'.
Generating RTLIL representation for module `$_DFFE_PP0N_'.
Generating RTLIL representation for module `$_DFFE_PP1N_'.
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
Generating RTLIL representation for module `$_ALDFF_NP_'.
Generating RTLIL representation for module `$_ALDFF_PP_'.
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

3.39.2. Continuing TECHMAP pass.
Using template $_DFF_PP0_ for cells of type $_DFF_PP0_.
Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
No more expansions possible.
<suppressed ~371 debug messages>

3.40. Executing OPT_EXPR pass (perform const folding).
Optimizing module top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing module FpxxAdd.
<suppressed ~107 debug messages>

3.41. Executing SIMPLEMAP pass (map simple cells to gate primitives).

3.42. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in top_tommath_add_e8_m17_round_even_sticky_p4.
Handling GSR in FpxxAdd.

3.43. Executing ATTRMVCP pass (move or copy attributes).

3.44. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top_tommath_add_e8_m17_round_even_sticky_p4..
Finding unused cells or wires in module \FpxxAdd..
Removed 0 unused cells and 1186 unused wires.
<suppressed ~2 debug messages>

3.45. Executing ABC pass (technology mapping using ABC).

3.45.1. Extracting gate netlist of module `\top_tommath_add_e8_m17_round_even_sticky_p4' to `<abc-temp-dir>/input.blif'..

3.45.1.1. Executed ABC.
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

3.45.2. Extracting gate netlist of module `\FpxxAdd' to `<abc-temp-dir>/input.blif'..

3.45.2.1. Executed ABC.
Extracted 866 gates and 1151 wires to a netlist network with 285 inputs and 227 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: + strash 
ABC: + &get -n 
ABC: + &fraig -x 
ABC: + &put 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf 
ABC: + &put 
ABC: + write_blif <abc-temp-dir>/output.blif 
ABC: 
ABC: YOSYS_ABC_DONE 

3.45.2.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:      205
ABC RESULTS:            ANDNOT cells:       46
ABC RESULTS:               MUX cells:      177
ABC RESULTS:              NAND cells:      192
ABC RESULTS:               NOR cells:       58
ABC RESULTS:               NOT cells:       16
ABC RESULTS:                OR cells:       43
ABC RESULTS:             ORNOT cells:       48
ABC RESULTS:              XNOR cells:       55
ABC RESULTS:               XOR cells:        3
ABC RESULTS:        internal signals:      639
ABC RESULTS:           input signals:      285
ABC RESULTS:          output signals:      227
Removing temp directory.
Removing global temp directory.

3.46. Executing TECHMAP pass (map to technology primitives).

3.46.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v
Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v' to AST representation.
Generating RTLIL representation for module `$_DLATCH_N_'.
Generating RTLIL representation for module `$_DLATCH_P_'.
Successfully finished Verilog frontend.

3.46.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

3.47. Executing ABC pass (technology mapping using ABC).

3.47.1. Summary of detected clock domains:
  81 cells in clk={ }, en={ }, arst={ }, srst={ }

3.47.2. Extracting gate netlist of module `\top_tommath_add_e8_m17_round_even_sticky_p4' to `<abc-temp-dir>/input.blif'..
No matching clock domain found. Not extracting any FF cells.

3.47.2.1. Executed ABC.
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

3.47.3. Summary of detected clock domains:
  1139 cells in clk={ }, en={ }, arst={ }, srst={ }

3.47.4. Extracting gate netlist of module `\FpxxAdd' to `<abc-temp-dir>/input.blif'..
No matching clock domain found. Not extracting any FF cells.

3.47.4.1. Executed ABC.
Extracted 843 gates and 1128 wires to a netlist network with 285 inputs and 227 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
ABC: + strash 
ABC: + &get -n 
ABC: + &fraig -x 
ABC: + &put 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + strash 
ABC: + dch -f 
ABC: + if 
ABC: + mfs2 
ABC: + dress <abc-temp-dir>/input.blif 
ABC: Total number of equiv classes                =     394.
ABC: Participating nodes from both networks       =     802.
ABC: Participating nodes from the first network   =     396. (  88.39 % of nodes)
ABC: Participating nodes from the second network  =     406. (  90.62 % of nodes)
ABC: Node pairs (any polarity)                    =     396. (  88.39 % of names can be moved)
ABC: Node pairs (same polarity)                   =     294. (  65.62 % of names can be moved)
ABC: Total runtime =     0.11 sec
ABC: + write_blif <abc-temp-dir>/output.blif 
ABC: 
ABC: YOSYS_ABC_DONE 

3.47.4.2. Re-integrating ABC results.
ABC RESULTS:              $lut cells:      447
ABC RESULTS:        internal signals:      616
ABC RESULTS:           input signals:      285
ABC RESULTS:          output signals:      227
Removing temp directory.
Removing global temp directory.
Removed 0 unused cells and 2223 unused wires.

3.48. Executing TECHMAP pass (map to technology primitives).

3.48.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v
Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$_DFF_N_'.
Generating RTLIL representation for module `$_DFF_P_'.
Generating RTLIL representation for module `$_DFFE_NN_'.
Generating RTLIL representation for module `$_DFFE_PN_'.
Generating RTLIL representation for module `$_DFFE_NP_'.
Generating RTLIL representation for module `$_DFFE_PP_'.
Generating RTLIL representation for module `$_DFF_NP0_'.
Generating RTLIL representation for module `$_DFF_NP1_'.
Generating RTLIL representation for module `$_DFF_PP0_'.
Generating RTLIL representation for module `$_DFF_PP1_'.
Generating RTLIL representation for module `$_SDFF_NP0_'.
Generating RTLIL representation for module `$_SDFF_NP1_'.
Generating RTLIL representation for module `$_SDFF_PP0_'.
Generating RTLIL representation for module `$_SDFF_PP1_'.
Generating RTLIL representation for module `$_DFFE_NP0P_'.
Generating RTLIL representation for module `$_DFFE_NP1P_'.
Generating RTLIL representation for module `$_DFFE_PP0P_'.
Generating RTLIL representation for module `$_DFFE_PP1P_'.
Generating RTLIL representation for module `$_DFFE_NP0N_'.
Generating RTLIL representation for module `$_DFFE_NP1N_'.
Generating RTLIL representation for module `$_DFFE_PP0N_'.
Generating RTLIL representation for module `$_DFFE_PP1N_'.
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
Generating RTLIL representation for module `$_ALDFF_NP_'.
Generating RTLIL representation for module `$_ALDFF_PP_'.
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `$lut'.
Successfully finished Verilog frontend.

3.48.2. Continuing TECHMAP pass.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut.
Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$d94f7d3127937b5dc7a66ea8cc409d7cf91bc488$lut for cells of type $lut.
Using template $paramod$2ae22ed255cc0f3746c71b5da2407ee38a2a66e6$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869$lut for cells of type $lut.
Using template $paramod$45d617c2ce0041e27b541f62b0fc3c3ce441a616$lut for cells of type $lut.
Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod$cb2734975eea7fbf36668a682c72265154a67ce0$lut for cells of type $lut.
Using template $paramod$00e63dd609c2ed072fb94a4f508e2ee20d7d9830$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$6a34cd5b50e324824168b4186d0b04ba5e83b039$lut for cells of type $lut.
Using template $paramod$4aaf6434b027bbf943d2a203e1697ba4b20c1592$lut for cells of type $lut.
Using template $paramod$ae480213635cbd149c458b162b9a16424bded9da$lut for cells of type $lut.
Using template $paramod$21d9488390cda9e1c5cef96c0e87e897a91a44eb$lut for cells of type $lut.
Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b$lut for cells of type $lut.
Using template $paramod$33c1b38a495cb5b629be9643a1b749c5a8d8a8da$lut for cells of type $lut.
Using template $paramod$3ecf9ddef4604dcf386e9244fca9c73d93eaac60$lut for cells of type $lut.
Using template $paramod$494cbca903b9af44b925758232af52ad14c00140$lut for cells of type $lut.
Using template $paramod$a3c3ff4d0bfa3d933b46139212848b6f705d5198$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$dcde03cc1c7f1d985d817f7697c86534c1fedbcd$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$f5790de0c17edb73ec439ce6cb5da54f74c45697$lut for cells of type $lut.
Using template $paramod$040791c04ea86e31acd675021d95f3dbcc5a17ea$lut for cells of type $lut.
Using template $paramod$c7d224180c69c0d5fbef7598cd9ab1e40bba59d7$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa$lut for cells of type $lut.
Using template $paramod$3ef319efded008eed5f930491a82ee1762b3c0df$lut for cells of type $lut.
Using template $paramod$868876e6fbf32fc8a062709fbe4f313e5420f9a8$lut for cells of type $lut.
Using template $paramod$2d07b55acd6c8b0377ed0524bca7bf0f1681bbf8$lut for cells of type $lut.
Using template $paramod$56d36648044d0bf0f892c2050a60c21ad090a3b1$lut for cells of type $lut.
Using template $paramod$8eb41c7dd3e946d2e3b66574f23f2c980395454e$lut for cells of type $lut.
Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5$lut for cells of type $lut.
Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc$lut for cells of type $lut.
Using template $paramod$2d3ba667e1bb663616320ee027494ac84a318704$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$703a13a751e631ef123f38f7d2125aeabec0f94c$lut for cells of type $lut.
Using template $paramod$33a01f71ce1120f8d5dbc904e37771e37d5e6f4e$lut for cells of type $lut.
Using template $paramod$ad823946862e656cf7f96d606b18b8f972dc6d6c$lut for cells of type $lut.
Using template $paramod$8b367233aef4cc96995cd878ca7655b761db5ed6$lut for cells of type $lut.
Using template $paramod$f54c0ffd7b041ca43eac7710ab19c0666d826c22$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut.
Using template $paramod$4cb97eaba15319fdf6775bbff4edef1b5c8ce027$lut for cells of type $lut.
Using template $paramod$048d4aa2263b685fba6c6b0d38f6224df0dc3042$lut for cells of type $lut.
Using template $paramod$5784398f160420a838da015761d082a51332b3d2$lut for cells of type $lut.
Using template $paramod$9e53946c1c9323fd7abb74ec362c0cc9c01b25aa$lut for cells of type $lut.
Using template $paramod$ef32d4a33c35abee3271e9c59575dc791623f6b6$lut for cells of type $lut.
Using template $paramod$441de597d9318495d3225f370c9f7379b3b0fd0d$lut for cells of type $lut.
Using template $paramod$b062bca4221cf547385aa6b9bdf170b591219686$lut for cells of type $lut.
Using template $paramod$2fa475e5e4e6bc866e9aa610ab74b31c628f9d0d$lut for cells of type $lut.
Using template $paramod$0a94662b0161fc067fc2a1123fd5ac94da2ec1db$lut for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut.
Using template $paramod$cd05f04889088c47a0a5abae8c2d644fd314805e$lut for cells of type $lut.
Using template $paramod$7424b4bd8d948b45c3db420599cabcb9b1729eaa$lut for cells of type $lut.
Using template $paramod$b31cd0e69b6f4e3a36b96408b8aaf6629fc3d5d8$lut for cells of type $lut.
Using template $paramod$05f19d9c2311a3d1ab38ece311a1bb9f96c62043$lut for cells of type $lut.
Using template $paramod$ad3a97108c9f4d10f8acfa309b668b9455d3d733$lut for cells of type $lut.
Using template $paramod$478e33feeac3aa53ff57d491aada044b8aedceae$lut for cells of type $lut.
Using template $paramod$cbfd30b70b4f0ac8dd1d3ed758215fbf49783a3b$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut.
Using template $paramod$d0bf26260eea0e8530fb2e72eb38c60e28a47da8$lut for cells of type $lut.
Using template $paramod$979b7ee0d33f001d0cf3a713a590cc783b5c6182$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110001 for cells of type $lut.
Using template $paramod$7295da7c5b19f528a428229f2570e0a23ad372af$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut.
Using template $paramod$e0bde73e598487237493c8a43ca52c95a3727354$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$fb939c0165b0eb5dc8874aa07ff2a57753ef6f8c$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111000 for cells of type $lut.
Using template $paramod$e5f53fb2cb3e702c9422ebddd3ba952e5a8f3401$lut for cells of type $lut.
Using template $paramod$70ebb6cf5bc7d63c5c1a98ccefefa2af79e8f2a9$lut for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab$lut for cells of type $lut.
Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149$lut for cells of type $lut.
Using template $paramod$fedcddf7a4357754b8c2c1b3c873f3560b924a39$lut for cells of type $lut.
Using template $paramod$a710625e9e626ef5063a9eaeb20113d01f3592de$lut for cells of type $lut.
Using template $paramod$09d4dcde5ebe7306b113e229069d4b2b669e3287$lut for cells of type $lut.
Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8$lut for cells of type $lut.
Using template $paramod$5e6b43f92b6e5bf7fc47a9f66a1719a629e8c4a0$lut for cells of type $lut.
Using template $paramod$90807fd4acba8ea439ebbb3de49fd32db59910a6$lut for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c$lut for cells of type $lut.
Using template $paramod$46a139bc0e112d55fcaa3dd38c97433fb112b933$lut for cells of type $lut.
Using template $paramod$82a829e63f420d967ac0993f25cc70667cca902d$lut for cells of type $lut.
Using template $paramod$7c9db00ac3840ff315c6e2d674c34f83bb8d42d0$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$cd6c4b4da6d8737b72fd2dc8f5d83d8967445809$lut for cells of type $lut.
Using template $paramod$8aa914641d9da3ceaab54a09681d988e5887c82c$lut for cells of type $lut.
Using template $paramod$1a580bf99ef24e3f59ea678f1d8e4f67701445ca$lut for cells of type $lut.
Using template $paramod$089b66fb1cf2e65d67b18581358c9b7375b1c522$lut for cells of type $lut.
Using template $paramod$b297295e19b03521716155b85537bbe86d6a9ae6$lut for cells of type $lut.
Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec$lut for cells of type $lut.
Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730$lut for cells of type $lut.
Using template $paramod$05eb3bcef4871b65562c7d6f1033e7d4cf294d29$lut for cells of type $lut.
Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072$lut for cells of type $lut.
Using template $paramod$fb5ee0bdef1c4e74aaf1fd8efae98b46a2f5e564$lut for cells of type $lut.
Using template $paramod$16773ebb5e5d8dbce266b8a86bb4af4574d61ffd$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775$lut for cells of type $lut.
Using template $paramod$a15fd389a2f54cb7b94707b25934d226e68d9e2e$lut for cells of type $lut.
No more expansions possible.
<suppressed ~2092 debug messages>

3.49. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top_tommath_add_e8_m17_round_even_sticky_p4.
Optimizing LUTs in FpxxAdd.
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7783.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8051.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8077.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7961.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7965.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8060.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8061.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7950.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7950.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7756.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7769.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7782.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7824.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7813.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7958.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8004.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8175.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8019.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8019.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8037.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8040.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8049.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8112.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7949.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8129.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7959.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8050.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$7950.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8163.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8180.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$7742$auto$blifparse.cc:557:parse_blif$8180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Removed 0 unused cells and 1018 unused wires.

3.50. Executing AUTONAME pass.
Renamed 80 objects in module top_tommath_add_e8_m17_round_even_sticky_p4 (4 iterations).
Renamed 2848 objects in module FpxxAdd (338 iterations).
<suppressed ~2928 debug messages>

3.51. Executing HIERARCHY pass (managing design hierarchy).
Attribute `top' found on module `top_tommath_add_e8_m17_round_even_sticky_p4'. Setting top module to top_tommath_add_e8_m17_round_even_sticky_p4.

3.51.1. Analyzing design hierarchy..
Top module:  \top_tommath_add_e8_m17_round_even_sticky_p4
Used module:     \FpxxAdd

3.51.2. Analyzing design hierarchy..
Top module:  \top_tommath_add_e8_m17_round_even_sticky_p4
Used module:     \FpxxAdd
Removed 0 unused modules.

3.52. Printing statistics.

=== top_tommath_add_e8_m17_round_even_sticky_p4 ===

        +----------Local Count, excluding submodules.
        | 
       17 wires
      215 wire bits
       17 public wires
      215 public wire bits
        7 ports
       82 port bits
       81 submodules
        1   FpxxAdd
       80   TRELLIS_FF

=== FpxxAdd ===

        +----------Local Count, excluding submodules.
        | 
     1346 wires
     3221 wire bits
     1346 public wires
     3221 public wire bits
       13 ports
       82 port bits
     1599 submodules
       87   CCU2C
      155   L6MUX21
      875   LUT4
      273   PFUMX
      209   TRELLIS_FF

=== design hierarchy ===

        +----------Count including submodules.
        | 
        - top_tommath_add_e8_m17_round_even_sticky_p4

        +----------Count including submodules.
        | 
     1363 wires
     3436 wire bits
     1363 public wires
     3436 public wire bits
       20 ports
      164 port bits
        - memories
        - memory bits
        - processes
        - cells
       81 submodules
        1   FpxxAdd
       80   TRELLIS_FF

3.53. Executing CHECK pass (checking for obvious problems).
Checking module top_tommath_add_e8_m17_round_even_sticky_p4...
Checking module FpxxAdd...
Found and reported 0 problems.

3.54. Executing JSON backend.

End of script. Logfile hash: 944ec23fa4, time: 3.03s, user: 1.99s, system: 0.10s, MEM: 69.71 MB peak
Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3)
Time spent: 41% 3x abc (1 sec), 12% 17x read_verilog (0 sec), ...
$ yosys -s /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m17_round_even_sticky_p4/yosys.ys


[exit code 0]