****** Vivado v2025.2.1 (64-bit) **** SW Build 6403652 on Thu Mar 19 13:47:00 MDT 2026 **** IP Build 6403511 on Thu Mar 19 12:41:45 MDT 2026 **** SharedData Build 6403650 on Thu Mar 19 14:02:13 MDT 2026 **** Start of session at: Sat May 23 22:38:16 2026 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved. source /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/zkf_div_w8_m36_base/vivado.tcl -notrace read_xdc: Time (s): cpu = 00:00:14 ; elapsed = 00:00:25 . Memory (MB): peak = 1552.922 ; gain = 51.840 ; free physical = 3359 ; free virtual = 15018 Command: synth_design -top top_zkf_div_w8_m36_base -part xc7s50csga324-1 -mode out_of_context -flatten_hierarchy rebuilt Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7s50' INFO: [Device 21-403] Loading part xc7s50csga324-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 1 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 152378 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 2194.297 ; gain = 484.156 ; free physical = 270 ; free virtual = 5676 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'top_zkf_div_w8_m36_base' [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/zkf_div_w8_m36_base/src/top_zkf_div_w8_m36_base.v:3] INFO: [Synth 8-6157] synthesizing module 'zkf_div' [/mnt/storage/zubax/kulibin2/float/hdl/zkf_div.v:16] Parameter WEXP bound to: 8 - type: integer Parameter WMAN bound to: 36 - type: integer Parameter STAGE_INPUT bound to: 0 - type: integer Parameter STAGE_OUTPUT bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module '_zkf_pipe' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pipe.v:5] Parameter W bound to: 88 - type: integer Parameter N bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_pipe' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pipe.v:5] INFO: [Synth 8-6157] synthesizing module '_zkf_div_core' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:13] Parameter WEXP bound to: 8 - type: integer Parameter WMAN bound to: 36 - type: integer INFO: [Synth 8-6157] synthesizing module '_zkf_div_radix4_step' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:263] Parameter WMAN bound to: 36 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_radix4_step' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:263] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized0' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 3 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized0' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized1' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 5 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized1' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized2' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 7 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized2' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized3' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 9 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized3' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized4' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 11 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized4' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized5' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 13 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized5' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized6' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 15 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized6' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized7' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 17 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized7' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized8' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 19 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized8' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized9' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 21 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized9' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized10' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 23 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized10' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized11' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 25 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized11' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized12' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 27 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized12' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized13' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 29 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized13' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized14' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 31 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized14' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized15' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 33 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized15' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized16' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 35 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized16' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6157] synthesizing module '_zkf_div_raw_stage__parameterized17' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] Parameter WIN bound to: 37 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_div_raw_stage__parameterized17' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:250] INFO: [Synth 8-6155] done synthesizing module '_zkf_div_core' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:13] INFO: [Synth 8-6157] synthesizing module '_zkf_pack' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:21] Parameter WEXP bound to: 8 - type: integer Parameter WMAN bound to: 36 - type: integer Parameter STAGE_OUTPUT bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_pack' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:21] INFO: [Synth 8-6157] synthesizing module '_zkf_pack_delay' [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:138] Parameter W bound to: 1 - type: integer Parameter STAGE_OUTPUT bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module '_zkf_pack_delay' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:138] INFO: [Synth 8-6155] done synthesizing module 'zkf_div' (0#1) [/mnt/storage/zubax/kulibin2/float/hdl/zkf_div.v:16] INFO: [Synth 8-6155] done synthesizing module 'top_zkf_div_w8_m36_base' (0#1) [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/zkf_div_w8_m36_base/src/top_zkf_div_w8_m36_base.v:3] WARNING: [Synth 8-6014] Unused sequential element g_stage[19].r_den_reg[19] was removed. [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:154] WARNING: [Synth 8-6014] Unused sequential element g_stage[19].r_den3_reg[19] was removed. [/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:155] WARNING: [Synth 8-7129] Port clk in module _zkf_pack_delay is either unconnected or has no load WARNING: [Synth 8-7129] Port rst in module _zkf_pack_delay is either unconnected or has no load WARNING: [Synth 8-7129] Port clk in module _zkf_pack is either unconnected or has no load WARNING: [Synth 8-7129] Port clk in module _zkf_pipe is either unconnected or has no load WARNING: [Synth 8-7129] Port rst in module _zkf_pipe is either unconnected or has no load --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 2293.266 ; gain = 583.125 ; free physical = 339 ; free virtual = 5080 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 2308.109 ; gain = 597.969 ; free physical = 317 ; free virtual = 5058 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 2308.109 ; gain = 597.969 ; free physical = 317 ; free virtual = 5058 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2308.109 ; gain = 0.000 ; free physical = 301 ; free virtual = 5043 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/zkf_div_w8_m36_base/constraints.xdc] Finished Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/zkf_div_w8_m36_base/constraints.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2371.828 ; gain = 0.000 ; free physical = 324 ; free virtual = 4938 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2371.863 ; gain = 0.000 ; free physical = 324 ; free virtual = 4938 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:42 . Memory (MB): peak = 2371.863 ; gain = 661.723 ; free physical = 357 ; free virtual = 4865 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7s50csga324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:42 . Memory (MB): peak = 2379.832 ; gain = 669.691 ; free physical = 357 ; free virtual = 4865 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:42 . Memory (MB): peak = 2379.832 ; gain = 669.691 ; free physical = 357 ; free virtual = 4865 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:23 ; elapsed = 00:00:43 . Memory (MB): peak = 2379.832 ; gain = 669.691 ; free physical = 309 ; free virtual = 4823 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 44 Bit Adders := 1 3 Input 39 Bit Adders := 57 2 Input 38 Bit Adders := 1 2 Input 11 Bit Adders := 1 3 Input 10 Bit Adders := 1 3 Input 9 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 44 Bit Registers := 3 39 Bit Registers := 1 38 Bit Registers := 19 37 Bit Registers := 1 36 Bit Registers := 41 35 Bit Registers := 1 33 Bit Registers := 1 31 Bit Registers := 1 29 Bit Registers := 1 27 Bit Registers := 1 25 Bit Registers := 1 23 Bit Registers := 1 21 Bit Registers := 1 19 Bit Registers := 1 17 Bit Registers := 1 15 Bit Registers := 1 13 Bit Registers := 1 11 Bit Registers := 1 10 Bit Registers := 1 9 Bit Registers := 21 7 Bit Registers := 1 5 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 112 +---Muxes : 2 Input 36 Bit Muxes := 58 2 Input 8 Bit Muxes := 3 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 3 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 120 (col length:60) BRAMs: 150 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:59 . Memory (MB): peak = 2379.832 ; gain = 669.691 ; free physical = 270 ; free virtual = 4121 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:42 ; elapsed = 00:01:19 . Memory (MB): peak = 2439.832 ; gain = 729.691 ; free physical = 379 ; free virtual = 2412 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:43 ; elapsed = 00:01:22 . Memory (MB): peak = 2454.848 ; gain = 744.707 ; free physical = 392 ; free virtual = 2329 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:46 ; elapsed = 00:01:26 . Memory (MB): peak = 2470.863 ; gain = 760.723 ; free physical = 592 ; free virtual = 2576 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:52 ; elapsed = 00:01:38 . Memory (MB): peak = 2638.676 ; gain = 928.535 ; free physical = 798 ; free virtual = 2845 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:52 ; elapsed = 00:01:38 . Memory (MB): peak = 2638.676 ; gain = 928.535 ; free physical = 797 ; free virtual = 2844 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:53 ; elapsed = 00:01:39 . Memory (MB): peak = 2638.676 ; gain = 928.535 ; free physical = 798 ; free virtual = 2846 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:53 ; elapsed = 00:01:39 . Memory (MB): peak = 2638.676 ; gain = 928.535 ; free physical = 798 ; free virtual = 2846 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:53 ; elapsed = 00:01:39 . Memory (MB): peak = 2638.676 ; gain = 928.535 ; free physical = 798 ; free virtual = 2846 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:53 ; elapsed = 00:01:39 . Memory (MB): peak = 2638.676 ; gain = 928.535 ; free physical = 798 ; free virtual = 2846 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+-------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+-------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[38] | 20 | 10 | NO | YES | YES | 0 | 10 | |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[37] | 19 | 2 | NO | NO | YES | 0 | 2 | |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[35] | 18 | 2 | NO | NO | YES | 0 | 2 | |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[33] | 17 | 2 | NO | NO | YES | 2 | 0 | |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[31] | 16 | 2 | NO | NO | YES | 2 | 0 | |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[29] | 15 | 2 | NO | NO | YES | 2 | 0 | |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[27] | 14 | 2 | NO | NO | YES | 2 | 0 | |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[25] | 13 | 2 | NO | NO | YES | 2 | 0 | |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[23] | 12 | 2 | NO | NO | YES | 2 | 0 | |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[21] | 11 | 2 | NO | NO | YES | 2 | 0 | |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[19] | 10 | 2 | NO | NO | YES | 2 | 0 | |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[17] | 9 | 2 | NO | NO | YES | 2 | 0 | |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[15] | 8 | 2 | NO | NO | YES | 2 | 0 | |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[13] | 7 | 2 | NO | NO | YES | 2 | 0 | |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[11] | 6 | 2 | NO | NO | YES | 2 | 0 | |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[9] | 5 | 2 | NO | NO | YES | 2 | 0 | |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[7] | 4 | 2 | NO | NO | YES | 2 | 0 | |zkf_div | u_core/g_stage[19].u_raw/raw_next_reg[5] | 3 | 2 | NO | NO | YES | 2 | 0 | |zkf_div | u_core/sign_reg | 21 | 1 | NO | NO | YES | 0 | 1 | |zkf_div | u_core/force_zero_reg | 21 | 1 | NO | NO | YES | 0 | 1 | |zkf_div | u_core/force_inf_reg | 21 | 1 | NO | NO | YES | 0 | 1 | |zkf_div | u_core/div0_reg | 21 | 1 | NO | NO | YES | 0 | 1 | +------------+-------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |CARRY4 | 608| |2 |LUT1 | 157| |3 |LUT2 | 2043| |4 |LUT3 | 752| |5 |LUT4 | 41| |6 |LUT5 | 675| |7 |LUT6 | 35| |8 |SRL16E | 30| |9 |SRLC32E | 18| |10 |FDRE | 2376| +------+--------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:53 ; elapsed = 00:01:39 . Memory (MB): peak = 2638.676 ; gain = 928.535 ; free physical = 824 ; free virtual = 2872 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:50 ; elapsed = 00:01:34 . Memory (MB): peak = 2638.676 ; gain = 864.781 ; free physical = 816 ; free virtual = 2864 Synthesis Optimization Complete : Time (s): cpu = 00:00:53 ; elapsed = 00:01:39 . Memory (MB): peak = 2638.684 ; gain = 928.535 ; free physical = 816 ; free virtual = 2864 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2638.684 ; gain = 0.000 ; free physical = 972 ; free virtual = 3021 INFO: [Netlist 29-17] Analyzing 608 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/zkf_div_w8_m36_base/constraints.xdc] Finished Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/zkf_div_w8_m36_base/constraints.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2638.684 ; gain = 0.000 ; free physical = 841 ; free virtual = 2932 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Synth Design complete | Checksum: 666a3dfb INFO: [Common 17-83] Releasing license: Synthesis 66 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:05 ; elapsed = 00:01:56 . Memory (MB): peak = 2638.711 ; gain = 1085.789 ; free physical = 803 ; free virtual = 2924 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1675.171; main = 1575.374; forked = 259.204 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3540.918; main = 2638.680; forked = 1085.566 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7s50' Running DRC as a precondition to command opt_design Starting DRC Task WARNING: [DRC 23-814] Not all possible (connectivity based) DRCs may have been run because this design is seen as Out of Context. INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.86 . Memory (MB): peak = 2638.711 ; gain = 0.000 ; free physical = 774 ; free virtual = 2900 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 14b6f98c4 Time (s): cpu = 00:00:08 ; elapsed = 00:00:15 . Memory (MB): peak = 2638.711 ; gain = 0.000 ; free physical = 577 ; free virtual = 2751 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 14b6f98c4 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2672.676 ; gain = 0.000 ; free physical = 259 ; free virtual = 2511 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 14b6f98c4 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2672.676 ; gain = 0.000 ; free physical = 259 ; free virtual = 2511 Phase 1 Initialization | Checksum: 14b6f98c4 Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2672.676 ; gain = 0.000 ; free physical = 259 ; free virtual = 2511 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Detect if minReqCache needed Phase 2.1 Detect if minReqCache needed | Checksum: 14b6f98c4 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2672.676 ; gain = 0.000 ; free physical = 259 ; free virtual = 2511 Phase 2.2 Timer Update Phase 2.2 Timer Update | Checksum: 14b6f98c4 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2672.676 ; gain = 0.000 ; free physical = 259 ; free virtual = 2511 Phase 2 Timer Update And Timing Data Collection | Checksum: 14b6f98c4 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2672.676 ; gain = 0.000 ; free physical = 259 ; free virtual = 2511 Phase 3 Retarget INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 INFO: [Opt 31-1566] Pulled 1 inverters resulting in an inversion of 3 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 235dca290 Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2672.676 ; gain = 0.000 ; free physical = 253 ; free virtual = 2505 Retarget | Checksum: 235dca290 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 1fbd6b7c4 Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2672.676 ; gain = 0.000 ; free physical = 253 ; free virtual = 2504 Constant propagation | Checksum: 1fbd6b7c4 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2672.676 ; gain = 0.000 ; free physical = 256 ; free virtual = 2508 Phase 5 Sweep | Checksum: 19871e57c Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.56 . Memory (MB): peak = 2672.676 ; gain = 0.000 ; free physical = 256 ; free virtual = 2509 Sweep | Checksum: 19871e57c INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Sweep, 270 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 19871e57c Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2704.691 ; gain = 32.016 ; free physical = 256 ; free virtual = 2509 BUFG optimization | Checksum: 19871e57c INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 19871e57c Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.66 . Memory (MB): peak = 2704.691 ; gain = 32.016 ; free physical = 256 ; free virtual = 2509 Shift Register Optimization | Checksum: 19871e57c INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 19871e57c Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.75 . Memory (MB): peak = 2704.691 ; gain = 32.016 ; free physical = 256 ; free virtual = 2509 Post Processing Netlist | Checksum: 19871e57c INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 20a71efe7 Time (s): cpu = 00:00:00.93 ; elapsed = 00:00:01 . Memory (MB): peak = 2704.691 ; gain = 32.016 ; free physical = 256 ; free virtual = 2509 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 256 ; free virtual = 2509 Phase 9.2 Verifying Netlist Connectivity | Checksum: 20a71efe7 Time (s): cpu = 00:00:00.95 ; elapsed = 00:00:01 . Memory (MB): peak = 2704.691 ; gain = 32.016 ; free physical = 256 ; free virtual = 2509 Phase 9 Finalization | Checksum: 20a71efe7 Time (s): cpu = 00:00:00.95 ; elapsed = 00:00:01 . Memory (MB): peak = 2704.691 ; gain = 32.016 ; free physical = 256 ; free virtual = 2509 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 1 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 0 | 270 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 20a71efe7 Time (s): cpu = 00:00:00.95 ; elapsed = 00:00:01 . Memory (MB): peak = 2704.691 ; gain = 32.016 ; free physical = 256 ; free virtual = 2509 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 20a71efe7 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 255 ; free virtual = 2508 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 20a71efe7 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 255 ; free virtual = 2508 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 255 ; free virtual = 2508 INFO: [Common 17-83] Releasing license: Implementation 89 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:27 . Memory (MB): peak = 2704.691 ; gain = 65.980 ; free physical = 255 ; free virtual = 2508 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-83] Releasing license: Implementation WARNING: [DRC 23-814] Not all possible (connectivity based) DRCs may have been run because this design is seen as Out of Context. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Timing 38-35] Done setting XDC timing constraints. Running DRC as a precondition to command place_design WARNING: [DRC 23-814] Not all possible (connectivity based) DRCs may have been run because this design is seen as Out of Context. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 254 ; free virtual = 2545 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 136888cde Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 254 ; free virtual = 2545 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 254 ; free virtual = 2545 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 170964171 Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:02 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 255 ; free virtual = 2548 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 2147484db Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 241 ; free virtual = 2548 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 2147484db Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 241 ; free virtual = 2548 Phase 1 Placer Initialization | Checksum: 2147484db Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 249 ; free virtual = 2557 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1b486be7b Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 259 ; free virtual = 2567 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1f1fd4440 Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 280 ; free virtual = 2589 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 1f1fd4440 Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 280 ; free virtual = 2589 Phase 2.4 Global Place Phase1 Phase 2.4 Global Place Phase1 | Checksum: 18abe3802 Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 314 ; free virtual = 2627 Phase 2.5 Global Place Phase2 Phase 2.5.1 UpdateTiming Before Physical Synthesis Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 18abe3802 Time (s): cpu = 00:00:13 ; elapsed = 00:00:24 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 314 ; free virtual = 2628 Phase 2.5.2 Physical Synthesis In Placer INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 0 net or LUT. Breaked 0 LUT, combined 0 existing LUT and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 314 ; free virtual = 2628 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 0 | 0 | 0 | 4 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.5.2 Physical Synthesis In Placer | Checksum: 18abe3802 Time (s): cpu = 00:00:13 ; elapsed = 00:00:25 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 314 ; free virtual = 2628 Phase 2.5 Global Place Phase2 | Checksum: 17d6d0ef2 Time (s): cpu = 00:00:13 ; elapsed = 00:00:26 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 314 ; free virtual = 2628 Phase 2 Global Placement | Checksum: 17d6d0ef2 Time (s): cpu = 00:00:13 ; elapsed = 00:00:26 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 314 ; free virtual = 2628 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 21ce82802 Time (s): cpu = 00:00:15 ; elapsed = 00:00:29 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 311 ; free virtual = 2628 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 26a9d8a92 Time (s): cpu = 00:00:17 ; elapsed = 00:00:34 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 1629 ; free virtual = 4161 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 2fea700dd Time (s): cpu = 00:00:17 ; elapsed = 00:00:35 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 1623 ; free virtual = 4156 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 309a00b0e Time (s): cpu = 00:00:17 ; elapsed = 00:00:35 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 1623 ; free virtual = 4156 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 21161dae4 Time (s): cpu = 00:00:19 ; elapsed = 00:00:38 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 1592 ; free virtual = 4131 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 27c45016a Time (s): cpu = 00:00:20 ; elapsed = 00:00:39 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 1532 ; free virtual = 4103 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 309ce29cc Time (s): cpu = 00:00:20 ; elapsed = 00:00:39 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 1532 ; free virtual = 4103 Phase 3 Detail Placement | Checksum: 309ce29cc Time (s): cpu = 00:00:20 ; elapsed = 00:00:39 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 1532 ; free virtual = 4103 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1dfaa5ff8 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.470 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 11968195a Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 2780 ; free virtual = 5492 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 27317514e Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 2780 ; free virtual = 5492 Phase 4.1.1.1 BUFG Insertion | Checksum: 1dfaa5ff8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:44 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 2780 ; free virtual = 5492 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=0.527. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 14904b751 Time (s): cpu = 00:00:23 ; elapsed = 00:00:45 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 2787 ; free virtual = 5501 Time (s): cpu = 00:00:23 ; elapsed = 00:00:45 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 2787 ; free virtual = 5501 Phase 4.1 Post Commit Optimization | Checksum: 14904b751 Time (s): cpu = 00:00:23 ; elapsed = 00:00:45 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 2787 ; free virtual = 5501 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 14904b751 Time (s): cpu = 00:00:23 ; elapsed = 00:00:45 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 2787 ; free virtual = 5502 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 1x1| |___________|___________________|___________________| | South| 1x1| 4x4| |___________|___________________|___________________| | East| 1x1| 2x2| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 14904b751 Time (s): cpu = 00:00:23 ; elapsed = 00:00:45 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 2787 ; free virtual = 5502 Phase 4.3 Placer Reporting | Checksum: 14904b751 Time (s): cpu = 00:00:23 ; elapsed = 00:00:45 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 2787 ; free virtual = 5502 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 2787 ; free virtual = 5502 Time (s): cpu = 00:00:23 ; elapsed = 00:00:45 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 2787 ; free virtual = 5502 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21e524b1b Time (s): cpu = 00:00:23 ; elapsed = 00:00:45 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 2787 ; free virtual = 5502 Ending Placer Task | Checksum: 1acea7ffc Time (s): cpu = 00:00:23 ; elapsed = 00:00:45 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 2787 ; free virtual = 5502 114 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:47 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 2787 ; free virtual = 5502 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7s50' Starting Routing Task Phase 1 Build RT Design Checksum: PlaceDB: 2809745e ConstDB: 0 ShapeSum: da4fd868 RouteDB: aa913336 WARNING: [Route 35-197] Clock port "clk" does not have an associated HD.CLK_SRC. Without this constraint, timing analysis may not be accurate and upstream checks cannot be done to ensure correct clock placement. WARNING: [Route 35-198] Port "a_i[42]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[42]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[41]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[41]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[39]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[39]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[42]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[42]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[41]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[41]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[40]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[40]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[39]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[39]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[40]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[40]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[37]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[37]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[36]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[36]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[35]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[35]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[38]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[38]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[38]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[38]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[36]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[36]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[35]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[35]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[37]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[37]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[43]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[43]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[43]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[43]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[33]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[33]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[34]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[34]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[33]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[33]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[29]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[29]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[28]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[28]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[32]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[32]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[30]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[30]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[29]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[29]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[28]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[28]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[31]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[31]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[27]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[27]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[25]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[25]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[32]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[32]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[31]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[31]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[27]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[27]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[26]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[26]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[25]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[25]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[34]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[34]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[26]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[26]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[24]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[24]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[30]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[30]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[23]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[23]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[22]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[22]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[20]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[20]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[24]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[24]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[22]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[22]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[17]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[17]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[23]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[23]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[21]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[21]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[20]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[20]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[19]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[19]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[18]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[18]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[17]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[17]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[16]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[16]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[21]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[21]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[19]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[19]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[18]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[18]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[16]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[16]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[15]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[15]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[13]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[13]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[14]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[14]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[12]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[12]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[11]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[11]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[15]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[15]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[13]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[13]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[8]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[8]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[11]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[11]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[5]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[5]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[6]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[6]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[3]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[3]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[14]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[14]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[12]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[12]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[9]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[9]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[7]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[7]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[5]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[5]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[9]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[9]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[8]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[8]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[7]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[7]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[6]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[6]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[3]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[3]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "rst" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "rst". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "in_valid_i" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "in_valid_i". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Constraints 18-8777] Unable to split tiles. All required files are not available. Post Restoration Checksum: NetGraph: f9fc5d86 | NumContArr: d6a74263 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 355f59523 Time (s): cpu = 00:00:33 ; elapsed = 00:00:58 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 5320 ; free virtual = 8330 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 355f59523 Time (s): cpu = 00:00:33 ; elapsed = 00:00:59 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 5299 ; free virtual = 8310 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 355f59523 Time (s): cpu = 00:00:33 ; elapsed = 00:00:59 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 5293 ; free virtual = 8304 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 2452261d9 Time (s): cpu = 00:00:35 ; elapsed = 00:01:02 . Memory (MB): peak = 2704.691 ; gain = 0.000 ; free physical = 6270 ; free virtual = 9284 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.630 | TNS=0.000 | WHS=0.073 | THS=0.000 | Phase 2.4 Soft Constraint Pins - Fast Budgeting Phase 2.4 Soft Constraint Pins - Fast Budgeting | Checksum: 2208003f6 Time (s): cpu = 00:00:36 ; elapsed = 00:01:04 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 5889 ; free virtual = 8903 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 5700 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 5700 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 2 Router Initialization | Checksum: 2208003f6 Time (s): cpu = 00:00:37 ; elapsed = 00:01:05 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 5624 ; free virtual = 8638 Phase 3 Global Routing Phase 3 Global Routing | Checksum: 2208003f6 Time (s): cpu = 00:00:37 ; elapsed = 00:01:05 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 5617 ; free virtual = 8632 Phase 4 Initial Routing Phase 4.1 Initial Net Routing Pass Phase 4.1 Initial Net Routing Pass | Checksum: 160291ca1 Time (s): cpu = 00:00:38 ; elapsed = 00:01:08 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 5018 ; free virtual = 8033 Phase 4 Initial Routing | Checksum: 160291ca1 Time (s): cpu = 00:00:38 ; elapsed = 00:01:08 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 5016 ; free virtual = 8031 Phase 5 Rip-up And Reroute Phase 5.1 Global Iteration 0 Number of Nodes with overlaps = 878 Number of Nodes with overlaps = 196 Number of Nodes with overlaps = 68 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.495 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 5.1 Global Iteration 0 | Checksum: 22d7a201f Time (s): cpu = 00:00:48 ; elapsed = 00:01:25 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 3315 ; free virtual = 6358 Phase 5 Rip-up And Reroute | Checksum: 22d7a201f Time (s): cpu = 00:00:48 ; elapsed = 00:01:25 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 3315 ; free virtual = 6357 Phase 6 Delay and Skew Optimization Phase 6.1 Delay CleanUp Phase 6.1 Delay CleanUp | Checksum: 22d7a201f Time (s): cpu = 00:00:49 ; elapsed = 00:01:25 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 3315 ; free virtual = 6357 Phase 6.2 Clock Skew Optimization Phase 6.2 Clock Skew Optimization | Checksum: 22d7a201f Time (s): cpu = 00:00:49 ; elapsed = 00:01:25 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 3307 ; free virtual = 6349 Phase 6 Delay and Skew Optimization | Checksum: 22d7a201f Time (s): cpu = 00:00:49 ; elapsed = 00:01:25 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 3307 ; free virtual = 6349 Phase 7 Post Hold Fix Phase 7.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.495 | TNS=0.000 | WHS=0.057 | THS=0.000 | Phase 7.1 Hold Fix Iter | Checksum: 216969992 Time (s): cpu = 00:00:49 ; elapsed = 00:01:25 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 3298 ; free virtual = 6340 Phase 7 Post Hold Fix | Checksum: 216969992 Time (s): cpu = 00:00:49 ; elapsed = 00:01:25 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 3298 ; free virtual = 6340 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 1.53711 % Global Horizontal Routing Utilization = 2.2444 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 8 Route finalize | Checksum: 216969992 Time (s): cpu = 00:00:49 ; elapsed = 00:01:26 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 3297 ; free virtual = 6340 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 216969992 Time (s): cpu = 00:00:49 ; elapsed = 00:01:26 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 3297 ; free virtual = 6339 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 245c7a9fc Time (s): cpu = 00:00:50 ; elapsed = 00:01:28 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 3254 ; free virtual = 6302 Phase 11 Post Process Routing Phase 11 Post Process Routing | Checksum: 245c7a9fc Time (s): cpu = 00:00:50 ; elapsed = 00:01:28 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 3254 ; free virtual = 6302 Phase 12 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=0.495 | TNS=0.000 | WHS=0.057 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 12 Post Router Timing | Checksum: 245c7a9fc Time (s): cpu = 00:00:50 ; elapsed = 00:01:28 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 3254 ; free virtual = 6302 Total Elapsed time in route_design: 88.05 secs Phase 13 Post-Route Event Processing Phase 13 Post-Route Event Processing | Checksum: 13b55b987 Time (s): cpu = 00:00:50 ; elapsed = 00:01:28 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 3253 ; free virtual = 6301 INFO: [Route 35-16] Router Completed Successfully Ending Routing Task | Checksum: 13b55b987 Time (s): cpu = 00:00:50 ; elapsed = 00:01:28 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 3252 ; free virtual = 6300 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 122 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:01:28 . Memory (MB): peak = 2712.754 ; gain = 8.062 ; free physical = 3250 ; free virtual = 6299 INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {REF_NAME =~ DSP*}'. WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {REF_NAME =~ RAMB*}'. INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2712.754 ; gain = 0.000 ; free physical = 2910 ; free virtual = 5972 Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2712.754 ; gain = 0.000 ; free physical = 2909 ; free virtual = 5972 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2712.754 ; gain = 0.000 ; free physical = 2909 ; free virtual = 5972 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2712.754 ; gain = 0.000 ; free physical = 2839 ; free virtual = 5906 Wrote PlaceStorage: Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2712.754 ; gain = 0.000 ; free physical = 2768 ; free virtual = 5838 Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2712.754 ; gain = 0.000 ; free physical = 2764 ; free virtual = 5834 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2712.754 ; gain = 0.000 ; free physical = 2762 ; free virtual = 5834 Write Physdb Complete: Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.91 . Memory (MB): peak = 2712.754 ; gain = 0.000 ; free physical = 2754 ; free virtual = 5826 INFO: [Common 17-1381] The checkpoint '/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/zkf_div_w8_m36_base/post_route.dcp' has been generated. INFO: [Common 17-206] Exiting Vivado at Sat May 23 22:43:39 2026... $ /mnt/storage/xilinx/2025.2.1/Vivado/bin/vivado -mode batch -nojournal -nolog -notrace -source /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/zkf_div_w8_m36_base/vivado.tcl [exit code 0]