Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved. Sat May 23 22:27:48 2026 Command Line: /usr/local/diamond/3.14/ispfpga/bin/lin64/synthesis -f /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/zkf_div_w8_m36_base/lse.synproj Synthesis options: The -a option is ECP5U. The -s option is 6. The -t option is CABGA381. The -d option is LFE5U-12F. Using package CABGA381. Using performance grade 6. ########################################################## ### Lattice Family : ECP5U ### Device : LFE5U-12F ### Package : CABGA381 ### Speed : 6 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Timing Top-level module name = top_zkf_div_w8_m36_base. Target frequency = 100.000000 MHz. Maximum fanout = 1000. Timing path count = 10 BRAM utilization = 100.000000 % DSP usage = true (default) DSP utilization = 100 % (default) fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = auto Use Carry Chain = true carry_chain_length = 0 Use IO Insertion = TRUE Use IO Reg = FALSE Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = no ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p /usr/local/diamond/3.14/ispfpga/sa5p00/data (searchpath added) -p /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/zkf_div_w8_m36_base (searchpath added) Verilog design file = /mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v Verilog design file = /mnt/storage/zubax/kulibin2/float/hdl/_zkf_pipe.v Verilog design file = /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v Verilog design file = /mnt/storage/zubax/kulibin2/float/hdl/zkf_div.v Verilog design file = /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/zkf_div_w8_m36_base/src/top_zkf_div_w8_m36_base.v NGO file = /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/zkf_div_w8_m36_base/top_zkf_div_w8_m36_base.ngo -sdc option: SDC file input is /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/zkf_div_w8_m36_base/constraints.sdc. -lpf option: Output file option is not used. -vh2008 Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file /usr/local/diamond/3.14/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5u.v. VERI-1482 Compile design. Compile Design Begin Analyzing Verilog file /mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v. VERI-1482 Analyzing Verilog file /mnt/storage/zubax/kulibin2/float/hdl/_zkf_pipe.v. VERI-1482 Analyzing Verilog file /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v. VERI-1482 Analyzing Verilog file /mnt/storage/zubax/kulibin2/float/hdl/zkf_div.v. VERI-1482 Analyzing Verilog file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/zkf_div_w8_m36_base/src/top_zkf_div_w8_m36_base.v. VERI-1482 Analyzing Verilog file /usr/local/diamond/3.14/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5u.v. VERI-1482 Top module name (Verilog): top_zkf_div_w8_m36_base INFO - synthesis: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/zkf_div_w8_m36_base/src/top_zkf_div_w8_m36_base.v(4): compiling module top_zkf_div_w8_m36_base. VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/zkf_div.v(16): compiling module zkf_div(WEXP=8,WMAN=36). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_pipe.v(5): compiling module _zkf_pipe(W=88). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(13): compiling module _zkf_div_core(WEXP=8,WMAN=36). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(263): compiling module _zkf_div_radix4_step(WMAN=36). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage. VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=3). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=5). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=7). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=9). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=11). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=13). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=15). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=17). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=19). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=21). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=23). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=25). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=27). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=29). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=31). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=33). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=35). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(250): compiling module _zkf_div_raw_stage(WIN=37). VERI-1018 WARNING - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(140): Register r_den[0][35]_2578 is stuck at One. VDB-5014 WARNING - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v(182): Register r_den[1][35]_2704 is stuck at One. VDB-5014 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v(21): compiling module _zkf_pack(WEXP=8,WMAN=36). VERI-1018 INFO - synthesis: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v(138): compiling module _zkf_pack_delay. VERI-1018 Loading NGL library '/usr/local/diamond/3.14/ispfpga/sa5p00/data/sa5plib.ngl'... Loading NGL library '/usr/local/diamond/3.14/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library '/usr/local/diamond/3.14/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library '/usr/local/diamond/3.14/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'sa5p25.nph' in environment: /usr/local/diamond/3.14/ispfpga. Package Status: Final Version 1.44. Top-level module name = top_zkf_div_w8_m36_base. Duplicate register/latch removal. \u_dut/u_core/r_den[0][0]_2613 is a one-to-one match with \u_dut/u_core/r_den3[0][0]_2651. Duplicate register/latch removal. \u_dut/u_core/r_den[1][0]_2739 is a one-to-one match with \u_dut/u_core/r_den3[1][0]_2777. Duplicate register/latch removal. \u_dut/u_core/r_den[2][0]_2864 is a one-to-one match with \u_dut/u_core/r_den3[2][0]_2902. Duplicate register/latch removal. \u_dut/u_core/r_den[3][0]_2989 is a one-to-one match with \u_dut/u_core/r_den3[3][0]_3027. Duplicate register/latch removal. \u_dut/u_core/r_den[4][0]_3114 is a one-to-one match with \u_dut/u_core/r_den3[4][0]_3152. Duplicate register/latch removal. \u_dut/u_core/r_den[5][0]_3239 is a one-to-one match with \u_dut/u_core/r_den3[5][0]_3277. Duplicate register/latch removal. \u_dut/u_core/r_den[6][0]_3364 is a one-to-one match with \u_dut/u_core/r_den3[6][0]_3402. Duplicate register/latch removal. \u_dut/u_core/r_den[7][0]_3489 is a one-to-one match with \u_dut/u_core/r_den3[7][0]_3527. Duplicate register/latch removal. \u_dut/u_core/r_den[8][0]_3614 is a one-to-one match with \u_dut/u_core/r_den3[8][0]_3652. Duplicate register/latch removal. \u_dut/u_core/r_den[9][0]_3739 is a one-to-one match with \u_dut/u_core/r_den3[9][0]_3777. Duplicate register/latch removal. \u_dut/u_core/r_den[10][0]_3864 is a one-to-one match with \u_dut/u_core/r_den3[10][0]_3902. Duplicate register/latch removal. \u_dut/u_core/r_den[11][0]_3989 is a one-to-one match with \u_dut/u_core/r_den3[11][0]_4027. Duplicate register/latch removal. \u_dut/u_core/r_den[12][0]_4114 is a one-to-one match with \u_dut/u_core/r_den3[12][0]_4152. Duplicate register/latch removal. \u_dut/u_core/r_den[13][0]_4239 is a one-to-one match with \u_dut/u_core/r_den3[13][0]_4277. Duplicate register/latch removal. \u_dut/u_core/r_den[14][0]_4364 is a one-to-one match with \u_dut/u_core/r_den3[14][0]_4402. Duplicate register/latch removal. \u_dut/u_core/r_den[15][0]_4489 is a one-to-one match with \u_dut/u_core/r_den3[15][0]_4527. Duplicate register/latch removal. \u_dut/u_core/r_den[16][0]_4614 is a one-to-one match with \u_dut/u_core/r_den3[16][0]_4652. Duplicate register/latch removal. \u_dut/u_core/r_den[17][0]_4739 is a one-to-one match with \u_dut/u_core/r_den3[17][0]_4777. Duplicate register/latch removal. \u_dut/u_core/r_den[18][0]_4864 is a one-to-one match with \u_dut/u_core/r_den3[18][0]_4902. ######## GSR will not be inferred in an NGO flow, unless force_gsr=yes. WARNING - synthesis: No .lpf file will be written because the -lpf option is not used or is set to zero. Results of NGD DRC are available in top_zkf_div_w8_m36_base_drc.log. WARNING - synthesis: DRC checking was skipped because the -ngo option was used. Writing NGD file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/zkf_div_w8_m36_base/top_zkf_div_w8_m36_base.ngo. ################### Begin Area Report (top_zkf_div_w8_m36_base)###################### Number of register bits => 2977 of 12687 (23 % ) CCU2C => 1219 FD1S3AX => 2889 FD1S3IX => 86 FD1S3JX => 2 GSR => 1 IB => 91 LUT4 => 1705 OB => 46 PFUMX => 646 ################### End Area Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 1 Net : clk_c, loads : 2977 Clock Enable Nets Number of Clock Enables: 0 Top 0 highest fanout Clock Enables: Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : diff3_38, loads : 47 Net : diff3_38_adj_5589, loads : 47 Net : diff3_38_adj_5699, loads : 47 Net : diff3_38_adj_5809, loads : 47 Net : diff3_38_adj_5919, loads : 47 Net : diff3_38_adj_6029, loads : 47 Net : diff3_38_adj_6139, loads : 47 Net : diff3_38_adj_6249, loads : 47 Net : diff3_38_adj_6359, loads : 47 Net : diff3_38_adj_6469, loads : 47 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 10.000000 | | | -waveform { 0.000000 5.000000 } -name | | | clk [ get_ports { clk } ] | 100.000 MHz| 107.216 MHz| 10 | | | -------------------------------------------------------------------------------- All constraints were met. Peak Memory Usage: 261.137 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 18.909 secs --------------------------------------------------------------