Info: Logic utilisation before packing: Info: Total LUT4s: 1506/24288 6% Info: logic LUTs: 1238/24288 5% Info: carry LUTs: 268/24288 1% Info: RAM LUTs: 0/ 3036 0% Info: RAMW LUTs: 0/ 6072 0% Info: Total DFFs: 393/24288 1% Info: Packing IOs.. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 169 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: Checksum: 0x0188d4b8 Info: Device utilisation: Info: TRELLIS_IO: 136/ 197 69% Info: DCCA: 1/ 56 1% Info: DP16KD: 0/ 56 0% Info: MULT18X18D: 0/ 28 0% Info: ALU54B: 0/ 14 0% Info: EHXPLLL: 0/ 2 0% Info: EXTREFB: 0/ 1 0% Info: DCUA: 0/ 1 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 128 0% Info: SIOLOGIC: 0/ 69 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 8 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 393/ 24288 1% Info: TRELLIS_COMB: 1568/ 24288 6% Info: TRELLIS_RAMW: 0/ 3036 0% Info: Placed 0 cells based on constraints. Info: Creating initial analytic placement for 1080 cells, random placement wirelen = 77326. Info: at initial placer iter 0, wirelen = 7651 Info: at initial placer iter 1, wirelen = 6879 Info: at initial placer iter 2, wirelen = 6766 Info: at initial placer iter 3, wirelen = 6733 Info: Running main analytical placer, max placement attempts per cell = 550200. Info: at iteration #1, type ALL: wirelen solved = 6703, spread = 14155, legal = 14353; time = 0.04s Info: at iteration #2, type ALL: wirelen solved = 7154, spread = 15818, legal = 15819; time = 0.04s Info: at iteration #3, type ALL: wirelen solved = 7854, spread = 15356, legal = 15404; time = 0.03s Info: at iteration #4, type ALL: wirelen solved = 8127, spread = 14143, legal = 14246; time = 0.04s Info: at iteration #5, type ALL: wirelen solved = 8284, spread = 14398, legal = 14443; time = 0.04s Info: at iteration #6, type ALL: wirelen solved = 8494, spread = 12111, legal = 12250; time = 0.04s Info: at iteration #7, type ALL: wirelen solved = 8200, spread = 12617, legal = 12788; time = 0.05s Info: at iteration #8, type ALL: wirelen solved = 8366, spread = 12516, legal = 12705; time = 0.05s Info: at iteration #9, type ALL: wirelen solved = 8612, spread = 11834, legal = 12132; time = 0.06s Info: at iteration #10, type ALL: wirelen solved = 8445, spread = 12269, legal = 12429; time = 0.06s Info: at iteration #11, type ALL: wirelen solved = 8804, spread = 11458, legal = 11738; time = 0.06s Info: at iteration #12, type ALL: wirelen solved = 8720, spread = 11741, legal = 11936; time = 0.06s Info: at iteration #13, type ALL: wirelen solved = 8773, spread = 11218, legal = 11508; time = 0.05s Info: at iteration #14, type ALL: wirelen solved = 8711, spread = 11453, legal = 11815; time = 0.06s Info: at iteration #15, type ALL: wirelen solved = 8762, spread = 11375, legal = 11611; time = 0.05s Info: at iteration #16, type ALL: wirelen solved = 8811, spread = 11281, legal = 11622; time = 0.06s Info: at iteration #17, type ALL: wirelen solved = 8906, spread = 11453, legal = 11670; time = 0.05s Info: at iteration #18, type ALL: wirelen solved = 8967, spread = 11309, legal = 11594; time = 0.06s Info: HeAP Placer Time: 1.38s Info: of which solving equations: 0.71s Info: of which spreading cells: 0.14s Info: of which strict legalisation: 0.07s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 802, wirelen = 11508 Info: at iteration #5: temp = 0.000000, timing cost = 824, wirelen = 10613 Info: at iteration #10: temp = 0.000000, timing cost = 825, wirelen = 10389 Info: at iteration #14: temp = 0.000000, timing cost = 778, wirelen = 10362 Info: SA placement time 2.79s Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 54.39 MHz (FAIL at 100.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.54 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 7.57 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ -8385, -7515) |********************* Info: [ -7515, -6645) |************************************* Info: [ -6645, -5775) |********** Info: [ -5775, -4905) |* Info: [ -4905, -4035) |******* Info: [ -4035, -3165) |********** Info: [ -3165, -2295) |**************************************** Info: [ -2295, -1425) |************************************************** Info: [ -1425, -555) |*********************** Info: [ -555, 315) |* Info: [ 315, 1185) |**** Info: [ 1185, 2055) |******** Info: [ 2055, 2925) |******** Info: [ 2925, 3795) |************* Info: [ 3795, 4665) |****************************** Info: [ 4665, 5535) |*********** Info: [ 5535, 6405) |****** Info: [ 6405, 7275) |***** Info: [ 7275, 8145) |******************************** Info: [ 8145, 9015) |**************************** Info: Checksum: 0x75c7d76a Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 4977 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 378 621 | 378 621 | 4375| 0.48 0.48| Info: 2000 | 778 1221 | 400 600 | 3820| 0.36 0.84| Info: 3000 | 1278 1721 | 500 500 | 3454| 0.32 1.16| Info: 4000 | 1696 2303 | 418 582 | 3015| 0.33 1.49| Info: 5000 | 2272 2727 | 576 424 | 2719| 0.32 1.81| Info: 6000 | 2703 3238 | 431 511 | 2229| 0.28 2.09| Info: 7000 | 3194 3622 | 491 384 | 1790| 0.24 2.33| Info: 8000 | 3524 4221 | 330 599 | 1147| 0.23 2.56| Info: 9000 | 3686 4947 | 162 726 | 336| 0.27 2.83| Info: 9336 | 3687 5190 | 1 243 | 0| 0.20 3.03| Info: Routing complete. Info: Router1 time 3.03s Info: Checksum: 0x89efa2e0 Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: type curr total name Info: clk-to-q 0.52 0.52 Source u_dut.n2_n1_mant_b_adj_TRELLIS_FF_Q_32.Q Info: routing 0.94 1.46 Net u_dut.n2_n1_mant_b_adj[35] (7,12) -> (7,11) Info: Sink u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.A Info: Defined in: Info: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:225.23-225.39 Info: logic 0.24 1.70 Source u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.F Info: routing 0.00 1.70 Net u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT (7,11) -> (7,11) Info: Sink u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT_LUT4_Z.F1 Info: Defined in: Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32 Info: logic 0.17 1.86 Source u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT_LUT4_Z.OFX Info: routing 0.00 1.86 Net u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z_L6MUX21_Z_1_D1 (7,11) -> (7,11) Info: Sink u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.FXB Info: Defined in: Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40 Info: logic 0.24 2.11 Source u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT_LUT4_Z.OFX Info: routing 1.08 3.19 Net u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z[2] (7,11) -> (9,10) Info: Sink u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z_LUT4_D.C Info: Defined in: Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.24 3.42 Source u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z_LUT4_D.F Info: routing 0.00 3.42 Net u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z_LUT4_D_Z (9,10) -> (9,10) Info: Sink u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z_PFUMX_C0_BLUT_LUT4_Z.F1 Info: Defined in: Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:141.30-141.32 Info: logic 0.17 3.59 Source u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z_PFUMX_C0_BLUT_LUT4_Z.OFX Info: routing 0.00 3.59 Net u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z_PFUMX_C0_Z (9,10) -> (9,10) Info: Sink u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z_LUT4_D.FXB Info: Defined in: Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:141.38-141.40 Info: logic 0.24 3.83 Source u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z_LUT4_D.OFX Info: routing 0.97 4.80 Net u_dut.n3_n2_mant_b_opt_inv_LUT4_Z_34_D_LUT4_B_Z_L6MUX21_SD_Z[2] (9,10) -> (8,6) Info: Sink u_dut.n3_n2_mant_a_opt_inv_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.A Info: Defined in: Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.24 5.04 Source u_dut.n3_n2_mant_a_opt_inv_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F Info: routing 0.00 5.04 Net u_dut.n3_n2_mant_a_opt_inv_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT (8,6) -> (8,6) Info: Sink u_dut.n3_n2_mant_a_opt_inv_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1 Info: Defined in: Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48 Info: logic 0.17 5.20 Source u_dut.n3_n2_mant_a_opt_inv_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX Info: routing 0.00 5.20 Net u_dut.n3_n2_mant_a_opt_inv_L6MUX21_Z_D1_L6MUX21_Z_D1 (8,6) -> (8,6) Info: Sink u_dut.n3_n2_mant_a_opt_inv_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB Info: Defined in: Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64 Info: logic 0.24 5.45 Source u_dut.n3_n2_mant_a_opt_inv_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX Info: routing 0.00 5.45 Net u_dut.n3_n2_mant_a_opt_inv_L6MUX21_Z_D1 (8,6) -> (8,6) Info: Sink u_dut.n3_n2_mant_a_opt_inv_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB Info: Defined in: Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72 Info: logic 0.24 5.69 Source u_dut.n3_n2_mant_a_opt_inv_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: routing 0.89 6.58 Net u_dut.n2__mant_a_opt_inv[1] (8,6) -> (8,8) Info: Sink u_dut.n3_n2_mant_a_opt_inv_LUT4_Z_5.C Info: Defined in: Info: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:221.23-221.43 Info: logic 0.24 6.81 Source u_dut.n3_n2_mant_a_opt_inv_LUT4_Z_5.F Info: routing 1.08 7.89 Net u_dut.n2__mant_a_opt_inv[8] (8,8) -> (8,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_7$CCU2_COMB0.B Info: Defined in: Info: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:221.23-221.43 Info: logic 0.45 8.34 Source u_dut._zz_n3_mant_add_CCU2C_S1_7$CCU2_COMB0.FCO Info: routing 0.00 8.34 Net u_dut._zz_n3_mant_add_CCU2C_S1_7$CCU2_FCI_INT (8,9) -> (8,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_7$CCU2_COMB1.FCI Info: logic 0.00 8.34 Source u_dut._zz_n3_mant_add_CCU2C_S1_7$CCU2_COMB1.FCO Info: routing 0.00 8.34 Net u_dut._zz_n3_mant_add_CCU2C_S0_COUT[8] (8,9) -> (8,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_5$CCU2_COMB0.FCI Info: Defined in: Info: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:442.29-442.72 Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v:63.22-63.23 Info: logic 0.07 8.41 Source u_dut._zz_n3_mant_add_CCU2C_S1_5$CCU2_COMB0.FCO Info: routing 0.00 8.41 Net u_dut._zz_n3_mant_add_CCU2C_S1_5$CCU2_FCI_INT (8,9) -> (8,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_5$CCU2_COMB1.FCI Info: logic 0.00 8.41 Source u_dut._zz_n3_mant_add_CCU2C_S1_5$CCU2_COMB1.FCO Info: routing 0.00 8.41 Net u_dut._zz_n3_mant_add_CCU2C_S0_COUT[10] (8,9) -> (8,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_2$CCU2_COMB0.FCI Info: Defined in: Info: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:442.29-442.72 Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v:63.22-63.23 Info: logic 0.07 8.48 Source u_dut._zz_n3_mant_add_CCU2C_S1_2$CCU2_COMB0.FCO Info: routing 0.00 8.48 Net u_dut._zz_n3_mant_add_CCU2C_S1_2$CCU2_FCI_INT (8,9) -> (8,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_2$CCU2_COMB1.FCI Info: logic 0.00 8.48 Source u_dut._zz_n3_mant_add_CCU2C_S1_2$CCU2_COMB1.FCO Info: routing 0.00 8.48 Net u_dut._zz_n3_mant_add_CCU2C_S0_COUT[12] (8,9) -> (9,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_1$CCU2_COMB0.FCI Info: Defined in: Info: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:442.29-442.72 Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v:63.22-63.23 Info: logic 0.07 8.55 Source u_dut._zz_n3_mant_add_CCU2C_S1_1$CCU2_COMB0.FCO Info: routing 0.00 8.55 Net u_dut._zz_n3_mant_add_CCU2C_S1_1$CCU2_FCI_INT (9,9) -> (9,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_1$CCU2_COMB1.FCI Info: logic 0.00 8.55 Source u_dut._zz_n3_mant_add_CCU2C_S1_1$CCU2_COMB1.FCO Info: routing 0.00 8.55 Net u_dut._zz_n3_mant_add_CCU2C_S0_COUT[14] (9,9) -> (9,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_18$CCU2_COMB0.FCI Info: Defined in: Info: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:442.29-442.72 Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v:63.22-63.23 Info: logic 0.07 8.62 Source u_dut._zz_n3_mant_add_CCU2C_S1_18$CCU2_COMB0.FCO Info: routing 0.00 8.62 Net u_dut._zz_n3_mant_add_CCU2C_S1_18$CCU2_FCI_INT (9,9) -> (9,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_18$CCU2_COMB1.FCI Info: logic 0.00 8.62 Source u_dut._zz_n3_mant_add_CCU2C_S1_18$CCU2_COMB1.FCO Info: routing 0.00 8.62 Net u_dut._zz_n3_mant_add_CCU2C_S0_COUT[16] (9,9) -> (9,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_3$CCU2_COMB0.FCI Info: Defined in: Info: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:442.29-442.72 Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v:63.22-63.23 Info: logic 0.07 8.69 Source u_dut._zz_n3_mant_add_CCU2C_S1_3$CCU2_COMB0.FCO Info: routing 0.00 8.69 Net u_dut._zz_n3_mant_add_CCU2C_S1_3$CCU2_FCI_INT (9,9) -> (9,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_3$CCU2_COMB1.FCI Info: logic 0.00 8.69 Source u_dut._zz_n3_mant_add_CCU2C_S1_3$CCU2_COMB1.FCO Info: routing 0.00 8.69 Net u_dut._zz_n3_mant_add_CCU2C_S0_COUT[18] (9,9) -> (9,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_12$CCU2_COMB0.FCI Info: Defined in: Info: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:442.29-442.72 Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v:63.22-63.23 Info: logic 0.07 8.76 Source u_dut._zz_n3_mant_add_CCU2C_S1_12$CCU2_COMB0.FCO Info: routing 0.00 8.76 Net u_dut._zz_n3_mant_add_CCU2C_S1_12$CCU2_FCI_INT (9,9) -> (9,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_12$CCU2_COMB1.FCI Info: logic 0.00 8.76 Source u_dut._zz_n3_mant_add_CCU2C_S1_12$CCU2_COMB1.FCO Info: routing 0.00 8.76 Net u_dut._zz_n3_mant_add_CCU2C_S0_COUT[20] (9,9) -> (10,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_16$CCU2_COMB0.FCI Info: Defined in: Info: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:442.29-442.72 Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v:63.22-63.23 Info: logic 0.07 8.83 Source u_dut._zz_n3_mant_add_CCU2C_S1_16$CCU2_COMB0.FCO Info: routing 0.00 8.83 Net u_dut._zz_n3_mant_add_CCU2C_S1_16$CCU2_FCI_INT (10,9) -> (10,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_16$CCU2_COMB1.FCI Info: logic 0.00 8.83 Source u_dut._zz_n3_mant_add_CCU2C_S1_16$CCU2_COMB1.FCO Info: routing 0.00 8.83 Net u_dut._zz_n3_mant_add_CCU2C_S0_COUT[22] (10,9) -> (10,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_19$CCU2_COMB0.FCI Info: Defined in: Info: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:442.29-442.72 Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v:63.22-63.23 Info: logic 0.07 8.90 Source u_dut._zz_n3_mant_add_CCU2C_S1_19$CCU2_COMB0.FCO Info: routing 0.00 8.90 Net u_dut._zz_n3_mant_add_CCU2C_S1_19$CCU2_FCI_INT (10,9) -> (10,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_19$CCU2_COMB1.FCI Info: logic 0.00 8.90 Source u_dut._zz_n3_mant_add_CCU2C_S1_19$CCU2_COMB1.FCO Info: routing 0.00 8.90 Net u_dut._zz_n3_mant_add_CCU2C_S0_COUT[24] (10,9) -> (10,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_13$CCU2_COMB0.FCI Info: Defined in: Info: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:442.29-442.72 Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v:63.22-63.23 Info: logic 0.07 8.98 Source u_dut._zz_n3_mant_add_CCU2C_S1_13$CCU2_COMB0.FCO Info: routing 0.00 8.98 Net u_dut._zz_n3_mant_add_CCU2C_S1_13$CCU2_FCI_INT (10,9) -> (10,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_13$CCU2_COMB1.FCI Info: logic 0.00 8.98 Source u_dut._zz_n3_mant_add_CCU2C_S1_13$CCU2_COMB1.FCO Info: routing 0.00 8.98 Net u_dut._zz_n3_mant_add_CCU2C_S0_COUT[26] (10,9) -> (10,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_15$CCU2_COMB0.FCI Info: Defined in: Info: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:442.29-442.72 Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v:63.22-63.23 Info: logic 0.07 9.05 Source u_dut._zz_n3_mant_add_CCU2C_S1_15$CCU2_COMB0.FCO Info: routing 0.00 9.05 Net u_dut._zz_n3_mant_add_CCU2C_S1_15$CCU2_FCI_INT (10,9) -> (10,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_15$CCU2_COMB1.FCI Info: logic 0.00 9.05 Source u_dut._zz_n3_mant_add_CCU2C_S1_15$CCU2_COMB1.FCO Info: routing 0.00 9.05 Net u_dut._zz_n3_mant_add_CCU2C_S0_COUT[28] (10,9) -> (11,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_17$CCU2_COMB0.FCI Info: Defined in: Info: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:442.29-442.72 Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v:63.22-63.23 Info: logic 0.07 9.12 Source u_dut._zz_n3_mant_add_CCU2C_S1_17$CCU2_COMB0.FCO Info: routing 0.00 9.12 Net u_dut._zz_n3_mant_add_CCU2C_S1_17$CCU2_FCI_INT (11,9) -> (11,9) Info: Sink u_dut._zz_n3_mant_add_CCU2C_S1_17$CCU2_COMB1.FCI Info: logic 0.40 9.52 Source u_dut._zz_n3_mant_add_CCU2C_S1_17$CCU2_COMB1.F Info: routing 1.13 10.65 Net u_dut._zz_n3_mant_add[31] (11,9) -> (12,10) Info: Sink u_dut.n5_n4_lz_LUT4_Z_4_D_TRELLIS_FF_Q_1_DI_LUT4_Z_B_LUT4_Z_1.D Info: Defined in: Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.24 10.89 Source u_dut.n5_n4_lz_LUT4_Z_4_D_TRELLIS_FF_Q_1_DI_LUT4_Z_B_LUT4_Z_1.F Info: routing 0.81 11.69 Net u_dut.n5_mant_renormed_LUT4_Z_9_D_PFUMX_Z_C0_LUT4_Z_C_TRELLIS_FF_Q_1_DI_LUT4_D_Z_LUT4_Z_1_D_LUT4_Z_D[2] (12,10) -> (12,10) Info: Sink u_dut.n5_n4_lz_LUT4_Z_4_D_TRELLIS_FF_Q_2_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z_1.D Info: Defined in: Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.24 11.93 Source u_dut.n5_n4_lz_LUT4_Z_4_D_TRELLIS_FF_Q_2_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z_1.F Info: routing 1.16 13.10 Net u_dut.n5_mant_renormed_LUT4_Z_9_D_PFUMX_Z_C0_LUT4_Z_C_TRELLIS_FF_Q_1_DI_LUT4_D_Z_LUT4_Z_B[2] (12,10) -> (12,14) Info: Sink u_dut.n5_mant_renormed_LUT4_Z_9_D_PFUMX_Z_C0_LUT4_Z_C_TRELLIS_FF_Q_1_DI_LUT4_D_Z_LUT4_Z.C Info: Defined in: Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.24 13.33 Source u_dut.n5_mant_renormed_LUT4_Z_9_D_PFUMX_Z_C0_LUT4_Z_C_TRELLIS_FF_Q_1_DI_LUT4_D_Z_LUT4_Z.F Info: routing 1.28 14.61 Net u_dut.io_result_payload_mant_PFUMX_Z_1_ALUT_LUT4_Z_A_CCU2C_S0_COUT_CCU2C_COUT_8_S0_LUT4_Z_A_LUT4_Z_C_LUT4_B_C_TRELLIS_FF_Q_1_DI_PFUMX_Z_BLUT_LUT4_Z_D[1] (12,14) -> (14,11) Info: Sink u_dut.n5_mant_renormed_LUT4_Z_9_B_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_B_TRELLIS_FF_Q_1_DI_PFUMX_Z_BLUT_LUT4_Z.A Info: Defined in: Info: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 Info: logic 0.40 15.02 Source u_dut.n5_mant_renormed_LUT4_Z_9_B_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_B_TRELLIS_FF_Q_1_DI_PFUMX_Z_BLUT_LUT4_Z.OFX Info: routing 0.72 15.73 Net u_dut.n5_mant_renormed_LUT4_Z_9_B_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_B_TRELLIS_FF_Q_1_DI (14,11) -> (15,10) Info: Sink u_dut.n5_mant_renormed_LUT4_Z_9_B_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_B_TRELLIS_FF_Q_1.M Info: setup 0.00 15.73 Source u_dut.n5_mant_renormed_LUT4_Z_9_B_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_B_TRELLIS_FF_Q_1.M Info: 5.67 ns logic, 10.06 ns routing Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: type curr total name Info: source 0.00 0.00 Source rst$tr_io.O Info: routing 4.07 4.07 Net rst$TRELLIS_IO_IN (72,11) -> (4,11) Info: Sink out_valid_o_TRELLIS_FF_Q.LSR Info: Defined in: Info: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/top_tommath_add_e8_m35_round_even_sticky_p3.v:6.33-6.36 Info: setup 0.42 4.49 Source out_valid_o_TRELLIS_FF_Q.LSR Info: 0.42 ns logic, 4.07 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': Info: type curr total name Info: clk-to-q 0.52 0.52 Source y_o_TRELLIS_FF_Q_43.Q Info: routing 4.52 5.04 Net y_o[42]$TRELLIS_IO_OUT (19,16) -> (72,35) Info: Sink y_o[42]$tr_io.I Info: Defined in: Info: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/top_tommath_add_e8_m35_round_even_sticky_p3.v:40.115-40.118 Info: 0.52 ns logic, 4.52 ns routing Warning: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 63.56 MHz (FAIL at 100.00 MHz) Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.49 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 5.04 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ -5733, -4993) |***********************+ Info: [ -4993, -4253) |***************************+ Info: [ -4253, -3513) |**+ Info: [ -3513, -2773) |**********+ Info: [ -2773, -2033) |*******+ Info: [ -2033, -1293) |************************************************************ Info: [ -1293, -553) |*******+ Info: [ -553, 187) |************+ Info: [ 187, 927) |+ Info: [ 927, 1667) |+ Info: [ 1667, 2407) |**+ Info: [ 2407, 3147) |*********+ Info: [ 3147, 3887) |*********+ Info: [ 3887, 4627) |***+ Info: [ 4627, 5367) |*******************+ Info: [ 5367, 6107) |***********+ Info: [ 6107, 6847) |**+ Info: [ 6847, 7587) |*****+ Info: [ 7587, 8327) |***********************+ Info: [ 8327, 9067) |************************+ 1 warning, 0 errors Info: Program finished normally. $ nextpnr-ecp5 --json /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/netlist.json --write /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/nextpnr-routed.json --12k --package CABGA381 --speed 6 --freq 100 --timing-allow-fail --lpf-allow-unconstrained --report /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/nextpnr-report.json [exit code 0]