Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2025.2.1 (lin64) Build 6403652 Thu Mar 19 13:47:00 MDT 2026
| Date         : Sun May 24 15:05:55 2026
| Host         : deep-thought running 64-bit Manjaro Linux
| Command      : report_timing_summary -file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_mul_e8_m35_round_even_p2/timing_summary.rpt -max_paths 10 -nworst 10
| Design       : top_tommath_mul_e8_m35_round_even_p2
| Device       : 7s50-csga324
| Speed File   : -1  PRODUCTION 1.23 2018-06-13
| Design State : Routed
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (90)
6. checking no_output_delay (45)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (90)
-------------------------------
 There are 90 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (45)
--------------------------------
 There are 45 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
     -3.474     -150.173                     94                  380        0.114        0.000                      0                  380        2.833        0.000                       0                   330  


Timing constraints are not met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock  Waveform(ns)         Period(ns)      Frequency(MHz)
-----  ------------         ----------      --------------
clk    {0.000 3.333}        6.667           149.993         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
clk                -3.474     -150.173                     94                  380        0.114        0.000                      0                  380        2.833        0.000                       0                   330  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  clk
  To Clock:  clk

Setup :           94  Failing Endpoints,  Worst Slack       -3.474ns,  Total Violation     -150.173ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.114ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.833ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) :        -3.474ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        10.089ns  (logic 5.319ns (52.719%)  route 4.770ns (47.281%))
  Logic Levels:           31  (CARRY4=23 LUT4=1 LUT5=2 LUT6=5)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.973     0.973    u_dut/clk
    SLICE_X55Y55         FDRE                                         r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y55         FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/Q
                         net (fo=2, routed)           0.629     2.058    u_dut/n2_n1_mant_mul_reg__0_n_105
    SLICE_X54Y55         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520     2.578 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/CO[3]
                         net (fo=1, routed)           0.000     2.578    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X54Y56         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.695 r  u_dut/io_result_payload_mant[34]_INST_0_i_34/CO[3]
                         net (fo=1, routed)           0.000     2.695    u_dut/io_result_payload_mant[34]_INST_0_i_34_n_0
    SLICE_X54Y57         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.812 r  u_dut/io_result_payload_mant[34]_INST_0_i_29/CO[3]
                         net (fo=1, routed)           0.000     2.812    u_dut/io_result_payload_mant[34]_INST_0_i_29_n_0
    SLICE_X54Y58         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.929 r  u_dut/io_result_payload_mant[34]_INST_0_i_24/CO[3]
                         net (fo=1, routed)           0.000     2.929    u_dut/io_result_payload_mant[34]_INST_0_i_24_n_0
    SLICE_X54Y59         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.046 r  u_dut/io_result_payload_mant[34]_INST_0_i_13/CO[3]
                         net (fo=1, routed)           0.000     3.046    u_dut/io_result_payload_mant[34]_INST_0_i_13_n_0
    SLICE_X54Y60         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.163 r  u_dut/io_result_payload_mant[34]_INST_0_i_12/CO[3]
                         net (fo=1, routed)           0.000     3.163    u_dut/io_result_payload_mant[34]_INST_0_i_12_n_0
    SLICE_X54Y61         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.280 r  u_dut/io_result_payload_mant[11]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.280    u_dut/io_result_payload_mant[11]_INST_0_i_11_n_0
    SLICE_X54Y62         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.397 r  u_dut/io_result_payload_mant[15]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.397    u_dut/io_result_payload_mant[15]_INST_0_i_11_n_0
    SLICE_X54Y63         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.514 r  u_dut/io_result_payload_mant[19]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[19]_INST_0_i_11_n_0
    SLICE_X54Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.631 r  u_dut/io_result_payload_mant[23]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.631    u_dut/io_result_payload_mant[23]_INST_0_i_11_n_0
    SLICE_X54Y65         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.748 r  u_dut/io_result_payload_mant[27]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.748    u_dut/io_result_payload_mant[27]_INST_0_i_11_n_0
    SLICE_X54Y66         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.865 r  u_dut/io_result_payload_mant[31]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.865    u_dut/io_result_payload_mant[31]_INST_0_i_11_n_0
    SLICE_X54Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.982 r  u_dut/io_result_payload_exp[1]_INST_0_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.982    u_dut/io_result_payload_exp[1]_INST_0_i_3_n_0
    SLICE_X54Y68         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.315     4.297 r  u_dut/io_result_payload_exp[1]_INST_0_i_2/O[3]
                         net (fo=80, routed)          0.728     5.025    u_dut/n2_exp_mul_adj1
    SLICE_X52Y65         LUT4 (Prop_lut4_I1_O)        0.307     5.332 r  u_dut/io_result_payload_mant[3]_INST_0_i_17/O
                         net (fo=1, routed)           0.165     5.497    u_dut/io_result_payload_mant[3]_INST_0_i_17_n_0
    SLICE_X52Y65         LUT6 (Prop_lut6_I0_O)        0.124     5.621 r  u_dut/io_result_payload_mant[3]_INST_0_i_13/O
                         net (fo=1, routed)           0.417     6.038    u_dut/io_result_payload_mant[3]_INST_0_i_13_n_0
    SLICE_X52Y66         LUT6 (Prop_lut6_I2_O)        0.124     6.162 r  u_dut/io_result_payload_mant[3]_INST_0_i_11/O
                         net (fo=1, routed)           0.000     6.162    u_dut/io_result_payload_mant[3]_INST_0_i_11_n_0
    SLICE_X52Y66         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     6.675 r  u_dut/io_result_payload_mant[3]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.675    u_dut/io_result_payload_mant[3]_INST_0_i_2_n_0
    SLICE_X52Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.792 r  u_dut/io_result_payload_mant[7]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.792    u_dut/io_result_payload_mant[7]_INST_0_i_2_n_0
    SLICE_X52Y68         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.909 r  u_dut/io_result_payload_mant[11]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.909    u_dut/io_result_payload_mant[11]_INST_0_i_2_n_0
    SLICE_X52Y69         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.026 r  u_dut/io_result_payload_mant[15]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.026    u_dut/io_result_payload_mant[15]_INST_0_i_2_n_0
    SLICE_X52Y70         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.143 r  u_dut/io_result_payload_mant[19]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.143    u_dut/io_result_payload_mant[19]_INST_0_i_2_n_0
    SLICE_X52Y71         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.260 r  u_dut/io_result_payload_mant[23]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.260    u_dut/io_result_payload_mant[23]_INST_0_i_2_n_0
    SLICE_X52Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.377 r  u_dut/io_result_payload_mant[27]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.377    u_dut/io_result_payload_mant[27]_INST_0_i_2_n_0
    SLICE_X52Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.494 r  u_dut/io_result_payload_mant[31]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.494    u_dut/io_result_payload_mant[31]_INST_0_i_2_n_0
    SLICE_X52Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.611 f  u_dut/io_result_payload_mant[34]_INST_0_i_4/CO[3]
                         net (fo=3, routed)           0.611     8.222    u_dut/_zz_n2_mant_mul_rounded_1[35]
    SLICE_X51Y73         LUT5 (Prop_lut5_I4_O)        0.124     8.346 f  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=4, routed)           0.325     8.671    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X51Y74         LUT6 (Prop_lut6_I2_O)        0.124     8.795 r  u_dut/io_result_payload_exp[6]_INST_0_i_1/O
                         net (fo=6, routed)           0.558     9.353    u_dut/io_result_payload_exp[6]_INST_0_i_1_n_0
    SLICE_X48Y74         LUT6 (Prop_lut6_I4_O)        0.124     9.477 r  u_dut/io_result_payload_mant[34]_INST_0_i_5/O
                         net (fo=1, routed)           0.689    10.167    u_dut/io_result_payload_mant[34]_INST_0_i_5_n_0
    SLICE_X49Y74         LUT6 (Prop_lut6_I1_O)        0.124    10.291 r  u_dut/io_result_payload_mant[34]_INST_0_i_1/O
                         net (fo=35, routed)          0.648    10.938    u_dut/io_result_payload_mant[34]_INST_0_i_1_n_0
    SLICE_X51Y75         LUT5 (Prop_lut5_I4_O)        0.124    11.062 r  u_dut/io_result_payload_mant[8]_INST_0/O
                         net (fo=1, routed)           0.000    11.062    dut_y[8]
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=333, unset)          0.924     7.591    clk
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X51Y75         FDRE (Setup_fdre_C_D)        0.032     7.588    y_r_reg[8]
  -------------------------------------------------------------------
                         required time                          7.588    
                         arrival time                         -11.062    
  -------------------------------------------------------------------
                         slack                                 -3.474    

Slack (VIOLATED) :        -3.474ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        10.089ns  (logic 5.319ns (52.719%)  route 4.770ns (47.281%))
  Logic Levels:           31  (CARRY4=23 LUT4=1 LUT5=2 LUT6=5)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.973     0.973    u_dut/clk
    SLICE_X55Y55         FDRE                                         r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y55         FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/Q
                         net (fo=2, routed)           0.629     2.058    u_dut/n2_n1_mant_mul_reg__0_n_105
    SLICE_X54Y55         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520     2.578 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/CO[3]
                         net (fo=1, routed)           0.000     2.578    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X54Y56         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.695 r  u_dut/io_result_payload_mant[34]_INST_0_i_34/CO[3]
                         net (fo=1, routed)           0.000     2.695    u_dut/io_result_payload_mant[34]_INST_0_i_34_n_0
    SLICE_X54Y57         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.812 r  u_dut/io_result_payload_mant[34]_INST_0_i_29/CO[3]
                         net (fo=1, routed)           0.000     2.812    u_dut/io_result_payload_mant[34]_INST_0_i_29_n_0
    SLICE_X54Y58         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.929 r  u_dut/io_result_payload_mant[34]_INST_0_i_24/CO[3]
                         net (fo=1, routed)           0.000     2.929    u_dut/io_result_payload_mant[34]_INST_0_i_24_n_0
    SLICE_X54Y59         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.046 r  u_dut/io_result_payload_mant[34]_INST_0_i_13/CO[3]
                         net (fo=1, routed)           0.000     3.046    u_dut/io_result_payload_mant[34]_INST_0_i_13_n_0
    SLICE_X54Y60         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.163 f  u_dut/io_result_payload_mant[34]_INST_0_i_12/CO[3]
                         net (fo=1, routed)           0.000     3.163    u_dut/io_result_payload_mant[34]_INST_0_i_12_n_0
    SLICE_X54Y61         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.280 r  u_dut/io_result_payload_mant[11]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.280    u_dut/io_result_payload_mant[11]_INST_0_i_11_n_0
    SLICE_X54Y62         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.397 r  u_dut/io_result_payload_mant[15]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.397    u_dut/io_result_payload_mant[15]_INST_0_i_11_n_0
    SLICE_X54Y63         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.514 r  u_dut/io_result_payload_mant[19]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[19]_INST_0_i_11_n_0
    SLICE_X54Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.631 r  u_dut/io_result_payload_mant[23]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.631    u_dut/io_result_payload_mant[23]_INST_0_i_11_n_0
    SLICE_X54Y65         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.748 r  u_dut/io_result_payload_mant[27]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.748    u_dut/io_result_payload_mant[27]_INST_0_i_11_n_0
    SLICE_X54Y66         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.865 r  u_dut/io_result_payload_mant[31]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.865    u_dut/io_result_payload_mant[31]_INST_0_i_11_n_0
    SLICE_X54Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.982 r  u_dut/io_result_payload_exp[1]_INST_0_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.982    u_dut/io_result_payload_exp[1]_INST_0_i_3_n_0
    SLICE_X54Y68         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.315     4.297 r  u_dut/io_result_payload_exp[1]_INST_0_i_2/O[3]
                         net (fo=80, routed)          0.728     5.025    u_dut/n2_exp_mul_adj1
    SLICE_X52Y65         LUT4 (Prop_lut4_I1_O)        0.307     5.332 r  u_dut/io_result_payload_mant[3]_INST_0_i_17/O
                         net (fo=1, routed)           0.165     5.497    u_dut/io_result_payload_mant[3]_INST_0_i_17_n_0
    SLICE_X52Y65         LUT6 (Prop_lut6_I0_O)        0.124     5.621 r  u_dut/io_result_payload_mant[3]_INST_0_i_13/O
                         net (fo=1, routed)           0.417     6.038    u_dut/io_result_payload_mant[3]_INST_0_i_13_n_0
    SLICE_X52Y66         LUT6 (Prop_lut6_I2_O)        0.124     6.162 r  u_dut/io_result_payload_mant[3]_INST_0_i_11/O
                         net (fo=1, routed)           0.000     6.162    u_dut/io_result_payload_mant[3]_INST_0_i_11_n_0
    SLICE_X52Y66         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     6.675 r  u_dut/io_result_payload_mant[3]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.675    u_dut/io_result_payload_mant[3]_INST_0_i_2_n_0
    SLICE_X52Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.792 r  u_dut/io_result_payload_mant[7]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.792    u_dut/io_result_payload_mant[7]_INST_0_i_2_n_0
    SLICE_X52Y68         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.909 r  u_dut/io_result_payload_mant[11]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.909    u_dut/io_result_payload_mant[11]_INST_0_i_2_n_0
    SLICE_X52Y69         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.026 r  u_dut/io_result_payload_mant[15]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.026    u_dut/io_result_payload_mant[15]_INST_0_i_2_n_0
    SLICE_X52Y70         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.143 r  u_dut/io_result_payload_mant[19]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.143    u_dut/io_result_payload_mant[19]_INST_0_i_2_n_0
    SLICE_X52Y71         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.260 r  u_dut/io_result_payload_mant[23]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.260    u_dut/io_result_payload_mant[23]_INST_0_i_2_n_0
    SLICE_X52Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.377 r  u_dut/io_result_payload_mant[27]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.377    u_dut/io_result_payload_mant[27]_INST_0_i_2_n_0
    SLICE_X52Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.494 r  u_dut/io_result_payload_mant[31]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.494    u_dut/io_result_payload_mant[31]_INST_0_i_2_n_0
    SLICE_X52Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.611 f  u_dut/io_result_payload_mant[34]_INST_0_i_4/CO[3]
                         net (fo=3, routed)           0.611     8.222    u_dut/_zz_n2_mant_mul_rounded_1[35]
    SLICE_X51Y73         LUT5 (Prop_lut5_I4_O)        0.124     8.346 f  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=4, routed)           0.325     8.671    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X51Y74         LUT6 (Prop_lut6_I2_O)        0.124     8.795 r  u_dut/io_result_payload_exp[6]_INST_0_i_1/O
                         net (fo=6, routed)           0.558     9.353    u_dut/io_result_payload_exp[6]_INST_0_i_1_n_0
    SLICE_X48Y74         LUT6 (Prop_lut6_I4_O)        0.124     9.477 r  u_dut/io_result_payload_mant[34]_INST_0_i_5/O
                         net (fo=1, routed)           0.689    10.167    u_dut/io_result_payload_mant[34]_INST_0_i_5_n_0
    SLICE_X49Y74         LUT6 (Prop_lut6_I1_O)        0.124    10.291 r  u_dut/io_result_payload_mant[34]_INST_0_i_1/O
                         net (fo=35, routed)          0.648    10.938    u_dut/io_result_payload_mant[34]_INST_0_i_1_n_0
    SLICE_X51Y75         LUT5 (Prop_lut5_I4_O)        0.124    11.062 r  u_dut/io_result_payload_mant[8]_INST_0/O
                         net (fo=1, routed)           0.000    11.062    dut_y[8]
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=333, unset)          0.924     7.591    clk
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X51Y75         FDRE (Setup_fdre_C_D)        0.032     7.588    y_r_reg[8]
  -------------------------------------------------------------------
                         required time                          7.588    
                         arrival time                         -11.062    
  -------------------------------------------------------------------
                         slack                                 -3.474    

Slack (VIOLATED) :        -3.474ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        10.089ns  (logic 5.319ns (52.719%)  route 4.770ns (47.281%))
  Logic Levels:           31  (CARRY4=23 LUT4=1 LUT5=2 LUT6=5)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.973     0.973    u_dut/clk
    SLICE_X55Y55         FDRE                                         r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y55         FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/Q
                         net (fo=2, routed)           0.629     2.058    u_dut/n2_n1_mant_mul_reg__0_n_105
    SLICE_X54Y55         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520     2.578 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/CO[3]
                         net (fo=1, routed)           0.000     2.578    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X54Y56         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.695 r  u_dut/io_result_payload_mant[34]_INST_0_i_34/CO[3]
                         net (fo=1, routed)           0.000     2.695    u_dut/io_result_payload_mant[34]_INST_0_i_34_n_0
    SLICE_X54Y57         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.812 r  u_dut/io_result_payload_mant[34]_INST_0_i_29/CO[3]
                         net (fo=1, routed)           0.000     2.812    u_dut/io_result_payload_mant[34]_INST_0_i_29_n_0
    SLICE_X54Y58         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.929 r  u_dut/io_result_payload_mant[34]_INST_0_i_24/CO[3]
                         net (fo=1, routed)           0.000     2.929    u_dut/io_result_payload_mant[34]_INST_0_i_24_n_0
    SLICE_X54Y59         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.046 r  u_dut/io_result_payload_mant[34]_INST_0_i_13/CO[3]
                         net (fo=1, routed)           0.000     3.046    u_dut/io_result_payload_mant[34]_INST_0_i_13_n_0
    SLICE_X54Y60         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.163 r  u_dut/io_result_payload_mant[34]_INST_0_i_12/CO[3]
                         net (fo=1, routed)           0.000     3.163    u_dut/io_result_payload_mant[34]_INST_0_i_12_n_0
    SLICE_X54Y61         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.280 r  u_dut/io_result_payload_mant[11]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.280    u_dut/io_result_payload_mant[11]_INST_0_i_11_n_0
    SLICE_X54Y62         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.397 r  u_dut/io_result_payload_mant[15]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.397    u_dut/io_result_payload_mant[15]_INST_0_i_11_n_0
    SLICE_X54Y63         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.514 r  u_dut/io_result_payload_mant[19]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[19]_INST_0_i_11_n_0
    SLICE_X54Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.631 r  u_dut/io_result_payload_mant[23]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.631    u_dut/io_result_payload_mant[23]_INST_0_i_11_n_0
    SLICE_X54Y65         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.748 r  u_dut/io_result_payload_mant[27]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.748    u_dut/io_result_payload_mant[27]_INST_0_i_11_n_0
    SLICE_X54Y66         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.865 f  u_dut/io_result_payload_mant[31]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.865    u_dut/io_result_payload_mant[31]_INST_0_i_11_n_0
    SLICE_X54Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.982 r  u_dut/io_result_payload_exp[1]_INST_0_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.982    u_dut/io_result_payload_exp[1]_INST_0_i_3_n_0
    SLICE_X54Y68         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.315     4.297 r  u_dut/io_result_payload_exp[1]_INST_0_i_2/O[3]
                         net (fo=80, routed)          0.728     5.025    u_dut/n2_exp_mul_adj1
    SLICE_X52Y65         LUT4 (Prop_lut4_I1_O)        0.307     5.332 r  u_dut/io_result_payload_mant[3]_INST_0_i_17/O
                         net (fo=1, routed)           0.165     5.497    u_dut/io_result_payload_mant[3]_INST_0_i_17_n_0
    SLICE_X52Y65         LUT6 (Prop_lut6_I0_O)        0.124     5.621 r  u_dut/io_result_payload_mant[3]_INST_0_i_13/O
                         net (fo=1, routed)           0.417     6.038    u_dut/io_result_payload_mant[3]_INST_0_i_13_n_0
    SLICE_X52Y66         LUT6 (Prop_lut6_I2_O)        0.124     6.162 r  u_dut/io_result_payload_mant[3]_INST_0_i_11/O
                         net (fo=1, routed)           0.000     6.162    u_dut/io_result_payload_mant[3]_INST_0_i_11_n_0
    SLICE_X52Y66         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     6.675 r  u_dut/io_result_payload_mant[3]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.675    u_dut/io_result_payload_mant[3]_INST_0_i_2_n_0
    SLICE_X52Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.792 r  u_dut/io_result_payload_mant[7]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.792    u_dut/io_result_payload_mant[7]_INST_0_i_2_n_0
    SLICE_X52Y68         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.909 r  u_dut/io_result_payload_mant[11]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.909    u_dut/io_result_payload_mant[11]_INST_0_i_2_n_0
    SLICE_X52Y69         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.026 r  u_dut/io_result_payload_mant[15]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.026    u_dut/io_result_payload_mant[15]_INST_0_i_2_n_0
    SLICE_X52Y70         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.143 r  u_dut/io_result_payload_mant[19]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.143    u_dut/io_result_payload_mant[19]_INST_0_i_2_n_0
    SLICE_X52Y71         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.260 r  u_dut/io_result_payload_mant[23]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.260    u_dut/io_result_payload_mant[23]_INST_0_i_2_n_0
    SLICE_X52Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.377 r  u_dut/io_result_payload_mant[27]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.377    u_dut/io_result_payload_mant[27]_INST_0_i_2_n_0
    SLICE_X52Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.494 r  u_dut/io_result_payload_mant[31]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.494    u_dut/io_result_payload_mant[31]_INST_0_i_2_n_0
    SLICE_X52Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.611 f  u_dut/io_result_payload_mant[34]_INST_0_i_4/CO[3]
                         net (fo=3, routed)           0.611     8.222    u_dut/_zz_n2_mant_mul_rounded_1[35]
    SLICE_X51Y73         LUT5 (Prop_lut5_I4_O)        0.124     8.346 f  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=4, routed)           0.325     8.671    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X51Y74         LUT6 (Prop_lut6_I2_O)        0.124     8.795 r  u_dut/io_result_payload_exp[6]_INST_0_i_1/O
                         net (fo=6, routed)           0.558     9.353    u_dut/io_result_payload_exp[6]_INST_0_i_1_n_0
    SLICE_X48Y74         LUT6 (Prop_lut6_I4_O)        0.124     9.477 r  u_dut/io_result_payload_mant[34]_INST_0_i_5/O
                         net (fo=1, routed)           0.689    10.167    u_dut/io_result_payload_mant[34]_INST_0_i_5_n_0
    SLICE_X49Y74         LUT6 (Prop_lut6_I1_O)        0.124    10.291 r  u_dut/io_result_payload_mant[34]_INST_0_i_1/O
                         net (fo=35, routed)          0.648    10.938    u_dut/io_result_payload_mant[34]_INST_0_i_1_n_0
    SLICE_X51Y75         LUT5 (Prop_lut5_I4_O)        0.124    11.062 r  u_dut/io_result_payload_mant[8]_INST_0/O
                         net (fo=1, routed)           0.000    11.062    dut_y[8]
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=333, unset)          0.924     7.591    clk
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X51Y75         FDRE (Setup_fdre_C_D)        0.032     7.588    y_r_reg[8]
  -------------------------------------------------------------------
                         required time                          7.588    
                         arrival time                         -11.062    
  -------------------------------------------------------------------
                         slack                                 -3.474    

Slack (VIOLATED) :        -3.474ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        10.089ns  (logic 5.319ns (52.719%)  route 4.770ns (47.281%))
  Logic Levels:           31  (CARRY4=23 LUT4=1 LUT5=2 LUT6=5)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.973     0.973    u_dut/clk
    SLICE_X55Y55         FDRE                                         r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y55         FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/Q
                         net (fo=2, routed)           0.629     2.058    u_dut/n2_n1_mant_mul_reg__0_n_105
    SLICE_X54Y55         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520     2.578 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/CO[3]
                         net (fo=1, routed)           0.000     2.578    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X54Y56         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.695 r  u_dut/io_result_payload_mant[34]_INST_0_i_34/CO[3]
                         net (fo=1, routed)           0.000     2.695    u_dut/io_result_payload_mant[34]_INST_0_i_34_n_0
    SLICE_X54Y57         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.812 r  u_dut/io_result_payload_mant[34]_INST_0_i_29/CO[3]
                         net (fo=1, routed)           0.000     2.812    u_dut/io_result_payload_mant[34]_INST_0_i_29_n_0
    SLICE_X54Y58         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.929 r  u_dut/io_result_payload_mant[34]_INST_0_i_24/CO[3]
                         net (fo=1, routed)           0.000     2.929    u_dut/io_result_payload_mant[34]_INST_0_i_24_n_0
    SLICE_X54Y59         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.046 r  u_dut/io_result_payload_mant[34]_INST_0_i_13/CO[3]
                         net (fo=1, routed)           0.000     3.046    u_dut/io_result_payload_mant[34]_INST_0_i_13_n_0
    SLICE_X54Y60         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.163 f  u_dut/io_result_payload_mant[34]_INST_0_i_12/CO[3]
                         net (fo=1, routed)           0.000     3.163    u_dut/io_result_payload_mant[34]_INST_0_i_12_n_0
    SLICE_X54Y61         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.280 r  u_dut/io_result_payload_mant[11]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.280    u_dut/io_result_payload_mant[11]_INST_0_i_11_n_0
    SLICE_X54Y62         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.397 r  u_dut/io_result_payload_mant[15]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.397    u_dut/io_result_payload_mant[15]_INST_0_i_11_n_0
    SLICE_X54Y63         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.514 r  u_dut/io_result_payload_mant[19]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[19]_INST_0_i_11_n_0
    SLICE_X54Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.631 r  u_dut/io_result_payload_mant[23]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.631    u_dut/io_result_payload_mant[23]_INST_0_i_11_n_0
    SLICE_X54Y65         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.748 r  u_dut/io_result_payload_mant[27]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.748    u_dut/io_result_payload_mant[27]_INST_0_i_11_n_0
    SLICE_X54Y66         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.865 f  u_dut/io_result_payload_mant[31]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.865    u_dut/io_result_payload_mant[31]_INST_0_i_11_n_0
    SLICE_X54Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.982 r  u_dut/io_result_payload_exp[1]_INST_0_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.982    u_dut/io_result_payload_exp[1]_INST_0_i_3_n_0
    SLICE_X54Y68         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.315     4.297 r  u_dut/io_result_payload_exp[1]_INST_0_i_2/O[3]
                         net (fo=80, routed)          0.728     5.025    u_dut/n2_exp_mul_adj1
    SLICE_X52Y65         LUT4 (Prop_lut4_I1_O)        0.307     5.332 r  u_dut/io_result_payload_mant[3]_INST_0_i_17/O
                         net (fo=1, routed)           0.165     5.497    u_dut/io_result_payload_mant[3]_INST_0_i_17_n_0
    SLICE_X52Y65         LUT6 (Prop_lut6_I0_O)        0.124     5.621 r  u_dut/io_result_payload_mant[3]_INST_0_i_13/O
                         net (fo=1, routed)           0.417     6.038    u_dut/io_result_payload_mant[3]_INST_0_i_13_n_0
    SLICE_X52Y66         LUT6 (Prop_lut6_I2_O)        0.124     6.162 r  u_dut/io_result_payload_mant[3]_INST_0_i_11/O
                         net (fo=1, routed)           0.000     6.162    u_dut/io_result_payload_mant[3]_INST_0_i_11_n_0
    SLICE_X52Y66         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     6.675 r  u_dut/io_result_payload_mant[3]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.675    u_dut/io_result_payload_mant[3]_INST_0_i_2_n_0
    SLICE_X52Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.792 r  u_dut/io_result_payload_mant[7]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.792    u_dut/io_result_payload_mant[7]_INST_0_i_2_n_0
    SLICE_X52Y68         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.909 r  u_dut/io_result_payload_mant[11]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.909    u_dut/io_result_payload_mant[11]_INST_0_i_2_n_0
    SLICE_X52Y69         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.026 r  u_dut/io_result_payload_mant[15]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.026    u_dut/io_result_payload_mant[15]_INST_0_i_2_n_0
    SLICE_X52Y70         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.143 r  u_dut/io_result_payload_mant[19]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.143    u_dut/io_result_payload_mant[19]_INST_0_i_2_n_0
    SLICE_X52Y71         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.260 r  u_dut/io_result_payload_mant[23]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.260    u_dut/io_result_payload_mant[23]_INST_0_i_2_n_0
    SLICE_X52Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.377 r  u_dut/io_result_payload_mant[27]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.377    u_dut/io_result_payload_mant[27]_INST_0_i_2_n_0
    SLICE_X52Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.494 r  u_dut/io_result_payload_mant[31]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.494    u_dut/io_result_payload_mant[31]_INST_0_i_2_n_0
    SLICE_X52Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.611 f  u_dut/io_result_payload_mant[34]_INST_0_i_4/CO[3]
                         net (fo=3, routed)           0.611     8.222    u_dut/_zz_n2_mant_mul_rounded_1[35]
    SLICE_X51Y73         LUT5 (Prop_lut5_I4_O)        0.124     8.346 f  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=4, routed)           0.325     8.671    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X51Y74         LUT6 (Prop_lut6_I2_O)        0.124     8.795 r  u_dut/io_result_payload_exp[6]_INST_0_i_1/O
                         net (fo=6, routed)           0.558     9.353    u_dut/io_result_payload_exp[6]_INST_0_i_1_n_0
    SLICE_X48Y74         LUT6 (Prop_lut6_I4_O)        0.124     9.477 r  u_dut/io_result_payload_mant[34]_INST_0_i_5/O
                         net (fo=1, routed)           0.689    10.167    u_dut/io_result_payload_mant[34]_INST_0_i_5_n_0
    SLICE_X49Y74         LUT6 (Prop_lut6_I1_O)        0.124    10.291 r  u_dut/io_result_payload_mant[34]_INST_0_i_1/O
                         net (fo=35, routed)          0.648    10.938    u_dut/io_result_payload_mant[34]_INST_0_i_1_n_0
    SLICE_X51Y75         LUT5 (Prop_lut5_I4_O)        0.124    11.062 r  u_dut/io_result_payload_mant[8]_INST_0/O
                         net (fo=1, routed)           0.000    11.062    dut_y[8]
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=333, unset)          0.924     7.591    clk
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X51Y75         FDRE (Setup_fdre_C_D)        0.032     7.588    y_r_reg[8]
  -------------------------------------------------------------------
                         required time                          7.588    
                         arrival time                         -11.062    
  -------------------------------------------------------------------
                         slack                                 -3.474    

Slack (VIOLATED) :        -3.474ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        10.089ns  (logic 5.319ns (52.719%)  route 4.770ns (47.281%))
  Logic Levels:           31  (CARRY4=23 LUT4=1 LUT5=2 LUT6=5)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.973     0.973    u_dut/clk
    SLICE_X55Y55         FDRE                                         r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y55         FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/Q
                         net (fo=2, routed)           0.629     2.058    u_dut/n2_n1_mant_mul_reg__0_n_105
    SLICE_X54Y55         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520     2.578 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/CO[3]
                         net (fo=1, routed)           0.000     2.578    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X54Y56         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.695 r  u_dut/io_result_payload_mant[34]_INST_0_i_34/CO[3]
                         net (fo=1, routed)           0.000     2.695    u_dut/io_result_payload_mant[34]_INST_0_i_34_n_0
    SLICE_X54Y57         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.812 r  u_dut/io_result_payload_mant[34]_INST_0_i_29/CO[3]
                         net (fo=1, routed)           0.000     2.812    u_dut/io_result_payload_mant[34]_INST_0_i_29_n_0
    SLICE_X54Y58         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.929 r  u_dut/io_result_payload_mant[34]_INST_0_i_24/CO[3]
                         net (fo=1, routed)           0.000     2.929    u_dut/io_result_payload_mant[34]_INST_0_i_24_n_0
    SLICE_X54Y59         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.046 r  u_dut/io_result_payload_mant[34]_INST_0_i_13/CO[3]
                         net (fo=1, routed)           0.000     3.046    u_dut/io_result_payload_mant[34]_INST_0_i_13_n_0
    SLICE_X54Y60         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.163 r  u_dut/io_result_payload_mant[34]_INST_0_i_12/CO[3]
                         net (fo=1, routed)           0.000     3.163    u_dut/io_result_payload_mant[34]_INST_0_i_12_n_0
    SLICE_X54Y61         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.280 r  u_dut/io_result_payload_mant[11]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.280    u_dut/io_result_payload_mant[11]_INST_0_i_11_n_0
    SLICE_X54Y62         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.397 r  u_dut/io_result_payload_mant[15]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.397    u_dut/io_result_payload_mant[15]_INST_0_i_11_n_0
    SLICE_X54Y63         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.514 r  u_dut/io_result_payload_mant[19]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[19]_INST_0_i_11_n_0
    SLICE_X54Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.631 r  u_dut/io_result_payload_mant[23]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.631    u_dut/io_result_payload_mant[23]_INST_0_i_11_n_0
    SLICE_X54Y65         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.748 r  u_dut/io_result_payload_mant[27]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.748    u_dut/io_result_payload_mant[27]_INST_0_i_11_n_0
    SLICE_X54Y66         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.865 r  u_dut/io_result_payload_mant[31]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.865    u_dut/io_result_payload_mant[31]_INST_0_i_11_n_0
    SLICE_X54Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.982 f  u_dut/io_result_payload_exp[1]_INST_0_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.982    u_dut/io_result_payload_exp[1]_INST_0_i_3_n_0
    SLICE_X54Y68         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.315     4.297 r  u_dut/io_result_payload_exp[1]_INST_0_i_2/O[3]
                         net (fo=80, routed)          0.728     5.025    u_dut/n2_exp_mul_adj1
    SLICE_X52Y65         LUT4 (Prop_lut4_I1_O)        0.307     5.332 r  u_dut/io_result_payload_mant[3]_INST_0_i_17/O
                         net (fo=1, routed)           0.165     5.497    u_dut/io_result_payload_mant[3]_INST_0_i_17_n_0
    SLICE_X52Y65         LUT6 (Prop_lut6_I0_O)        0.124     5.621 r  u_dut/io_result_payload_mant[3]_INST_0_i_13/O
                         net (fo=1, routed)           0.417     6.038    u_dut/io_result_payload_mant[3]_INST_0_i_13_n_0
    SLICE_X52Y66         LUT6 (Prop_lut6_I2_O)        0.124     6.162 r  u_dut/io_result_payload_mant[3]_INST_0_i_11/O
                         net (fo=1, routed)           0.000     6.162    u_dut/io_result_payload_mant[3]_INST_0_i_11_n_0
    SLICE_X52Y66         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     6.675 r  u_dut/io_result_payload_mant[3]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.675    u_dut/io_result_payload_mant[3]_INST_0_i_2_n_0
    SLICE_X52Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.792 r  u_dut/io_result_payload_mant[7]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.792    u_dut/io_result_payload_mant[7]_INST_0_i_2_n_0
    SLICE_X52Y68         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.909 r  u_dut/io_result_payload_mant[11]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.909    u_dut/io_result_payload_mant[11]_INST_0_i_2_n_0
    SLICE_X52Y69         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.026 r  u_dut/io_result_payload_mant[15]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.026    u_dut/io_result_payload_mant[15]_INST_0_i_2_n_0
    SLICE_X52Y70         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.143 r  u_dut/io_result_payload_mant[19]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.143    u_dut/io_result_payload_mant[19]_INST_0_i_2_n_0
    SLICE_X52Y71         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.260 r  u_dut/io_result_payload_mant[23]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.260    u_dut/io_result_payload_mant[23]_INST_0_i_2_n_0
    SLICE_X52Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.377 r  u_dut/io_result_payload_mant[27]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.377    u_dut/io_result_payload_mant[27]_INST_0_i_2_n_0
    SLICE_X52Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.494 r  u_dut/io_result_payload_mant[31]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.494    u_dut/io_result_payload_mant[31]_INST_0_i_2_n_0
    SLICE_X52Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.611 f  u_dut/io_result_payload_mant[34]_INST_0_i_4/CO[3]
                         net (fo=3, routed)           0.611     8.222    u_dut/_zz_n2_mant_mul_rounded_1[35]
    SLICE_X51Y73         LUT5 (Prop_lut5_I4_O)        0.124     8.346 f  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=4, routed)           0.325     8.671    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X51Y74         LUT6 (Prop_lut6_I2_O)        0.124     8.795 r  u_dut/io_result_payload_exp[6]_INST_0_i_1/O
                         net (fo=6, routed)           0.558     9.353    u_dut/io_result_payload_exp[6]_INST_0_i_1_n_0
    SLICE_X48Y74         LUT6 (Prop_lut6_I4_O)        0.124     9.477 r  u_dut/io_result_payload_mant[34]_INST_0_i_5/O
                         net (fo=1, routed)           0.689    10.167    u_dut/io_result_payload_mant[34]_INST_0_i_5_n_0
    SLICE_X49Y74         LUT6 (Prop_lut6_I1_O)        0.124    10.291 r  u_dut/io_result_payload_mant[34]_INST_0_i_1/O
                         net (fo=35, routed)          0.648    10.938    u_dut/io_result_payload_mant[34]_INST_0_i_1_n_0
    SLICE_X51Y75         LUT5 (Prop_lut5_I4_O)        0.124    11.062 r  u_dut/io_result_payload_mant[8]_INST_0/O
                         net (fo=1, routed)           0.000    11.062    dut_y[8]
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=333, unset)          0.924     7.591    clk
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X51Y75         FDRE (Setup_fdre_C_D)        0.032     7.588    y_r_reg[8]
  -------------------------------------------------------------------
                         required time                          7.588    
                         arrival time                         -11.062    
  -------------------------------------------------------------------
                         slack                                 -3.474    

Slack (VIOLATED) :        -3.474ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        10.089ns  (logic 5.319ns (52.719%)  route 4.770ns (47.281%))
  Logic Levels:           31  (CARRY4=23 LUT4=1 LUT5=2 LUT6=5)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.973     0.973    u_dut/clk
    SLICE_X55Y55         FDRE                                         r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y55         FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/Q
                         net (fo=2, routed)           0.629     2.058    u_dut/n2_n1_mant_mul_reg__0_n_105
    SLICE_X54Y55         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520     2.578 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/CO[3]
                         net (fo=1, routed)           0.000     2.578    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X54Y56         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.695 r  u_dut/io_result_payload_mant[34]_INST_0_i_34/CO[3]
                         net (fo=1, routed)           0.000     2.695    u_dut/io_result_payload_mant[34]_INST_0_i_34_n_0
    SLICE_X54Y57         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.812 r  u_dut/io_result_payload_mant[34]_INST_0_i_29/CO[3]
                         net (fo=1, routed)           0.000     2.812    u_dut/io_result_payload_mant[34]_INST_0_i_29_n_0
    SLICE_X54Y58         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.929 r  u_dut/io_result_payload_mant[34]_INST_0_i_24/CO[3]
                         net (fo=1, routed)           0.000     2.929    u_dut/io_result_payload_mant[34]_INST_0_i_24_n_0
    SLICE_X54Y59         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.046 r  u_dut/io_result_payload_mant[34]_INST_0_i_13/CO[3]
                         net (fo=1, routed)           0.000     3.046    u_dut/io_result_payload_mant[34]_INST_0_i_13_n_0
    SLICE_X54Y60         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.163 f  u_dut/io_result_payload_mant[34]_INST_0_i_12/CO[3]
                         net (fo=1, routed)           0.000     3.163    u_dut/io_result_payload_mant[34]_INST_0_i_12_n_0
    SLICE_X54Y61         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.280 r  u_dut/io_result_payload_mant[11]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.280    u_dut/io_result_payload_mant[11]_INST_0_i_11_n_0
    SLICE_X54Y62         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.397 r  u_dut/io_result_payload_mant[15]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.397    u_dut/io_result_payload_mant[15]_INST_0_i_11_n_0
    SLICE_X54Y63         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.514 r  u_dut/io_result_payload_mant[19]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[19]_INST_0_i_11_n_0
    SLICE_X54Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.631 r  u_dut/io_result_payload_mant[23]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.631    u_dut/io_result_payload_mant[23]_INST_0_i_11_n_0
    SLICE_X54Y65         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.748 r  u_dut/io_result_payload_mant[27]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.748    u_dut/io_result_payload_mant[27]_INST_0_i_11_n_0
    SLICE_X54Y66         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.865 r  u_dut/io_result_payload_mant[31]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.865    u_dut/io_result_payload_mant[31]_INST_0_i_11_n_0
    SLICE_X54Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.982 f  u_dut/io_result_payload_exp[1]_INST_0_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.982    u_dut/io_result_payload_exp[1]_INST_0_i_3_n_0
    SLICE_X54Y68         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.315     4.297 r  u_dut/io_result_payload_exp[1]_INST_0_i_2/O[3]
                         net (fo=80, routed)          0.728     5.025    u_dut/n2_exp_mul_adj1
    SLICE_X52Y65         LUT4 (Prop_lut4_I1_O)        0.307     5.332 r  u_dut/io_result_payload_mant[3]_INST_0_i_17/O
                         net (fo=1, routed)           0.165     5.497    u_dut/io_result_payload_mant[3]_INST_0_i_17_n_0
    SLICE_X52Y65         LUT6 (Prop_lut6_I0_O)        0.124     5.621 r  u_dut/io_result_payload_mant[3]_INST_0_i_13/O
                         net (fo=1, routed)           0.417     6.038    u_dut/io_result_payload_mant[3]_INST_0_i_13_n_0
    SLICE_X52Y66         LUT6 (Prop_lut6_I2_O)        0.124     6.162 r  u_dut/io_result_payload_mant[3]_INST_0_i_11/O
                         net (fo=1, routed)           0.000     6.162    u_dut/io_result_payload_mant[3]_INST_0_i_11_n_0
    SLICE_X52Y66         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     6.675 r  u_dut/io_result_payload_mant[3]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.675    u_dut/io_result_payload_mant[3]_INST_0_i_2_n_0
    SLICE_X52Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.792 r  u_dut/io_result_payload_mant[7]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.792    u_dut/io_result_payload_mant[7]_INST_0_i_2_n_0
    SLICE_X52Y68         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.909 r  u_dut/io_result_payload_mant[11]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.909    u_dut/io_result_payload_mant[11]_INST_0_i_2_n_0
    SLICE_X52Y69         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.026 r  u_dut/io_result_payload_mant[15]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.026    u_dut/io_result_payload_mant[15]_INST_0_i_2_n_0
    SLICE_X52Y70         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.143 r  u_dut/io_result_payload_mant[19]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.143    u_dut/io_result_payload_mant[19]_INST_0_i_2_n_0
    SLICE_X52Y71         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.260 r  u_dut/io_result_payload_mant[23]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.260    u_dut/io_result_payload_mant[23]_INST_0_i_2_n_0
    SLICE_X52Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.377 r  u_dut/io_result_payload_mant[27]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.377    u_dut/io_result_payload_mant[27]_INST_0_i_2_n_0
    SLICE_X52Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.494 r  u_dut/io_result_payload_mant[31]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.494    u_dut/io_result_payload_mant[31]_INST_0_i_2_n_0
    SLICE_X52Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.611 f  u_dut/io_result_payload_mant[34]_INST_0_i_4/CO[3]
                         net (fo=3, routed)           0.611     8.222    u_dut/_zz_n2_mant_mul_rounded_1[35]
    SLICE_X51Y73         LUT5 (Prop_lut5_I4_O)        0.124     8.346 f  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=4, routed)           0.325     8.671    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X51Y74         LUT6 (Prop_lut6_I2_O)        0.124     8.795 r  u_dut/io_result_payload_exp[6]_INST_0_i_1/O
                         net (fo=6, routed)           0.558     9.353    u_dut/io_result_payload_exp[6]_INST_0_i_1_n_0
    SLICE_X48Y74         LUT6 (Prop_lut6_I4_O)        0.124     9.477 r  u_dut/io_result_payload_mant[34]_INST_0_i_5/O
                         net (fo=1, routed)           0.689    10.167    u_dut/io_result_payload_mant[34]_INST_0_i_5_n_0
    SLICE_X49Y74         LUT6 (Prop_lut6_I1_O)        0.124    10.291 r  u_dut/io_result_payload_mant[34]_INST_0_i_1/O
                         net (fo=35, routed)          0.648    10.938    u_dut/io_result_payload_mant[34]_INST_0_i_1_n_0
    SLICE_X51Y75         LUT5 (Prop_lut5_I4_O)        0.124    11.062 r  u_dut/io_result_payload_mant[8]_INST_0/O
                         net (fo=1, routed)           0.000    11.062    dut_y[8]
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=333, unset)          0.924     7.591    clk
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X51Y75         FDRE (Setup_fdre_C_D)        0.032     7.588    y_r_reg[8]
  -------------------------------------------------------------------
                         required time                          7.588    
                         arrival time                         -11.062    
  -------------------------------------------------------------------
                         slack                                 -3.474    

Slack (VIOLATED) :        -3.474ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        10.089ns  (logic 5.319ns (52.719%)  route 4.770ns (47.281%))
  Logic Levels:           31  (CARRY4=23 LUT4=1 LUT5=2 LUT6=5)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.973     0.973    u_dut/clk
    SLICE_X55Y55         FDRE                                         r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y55         FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/Q
                         net (fo=2, routed)           0.629     2.058    u_dut/n2_n1_mant_mul_reg__0_n_105
    SLICE_X54Y55         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520     2.578 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/CO[3]
                         net (fo=1, routed)           0.000     2.578    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X54Y56         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.695 r  u_dut/io_result_payload_mant[34]_INST_0_i_34/CO[3]
                         net (fo=1, routed)           0.000     2.695    u_dut/io_result_payload_mant[34]_INST_0_i_34_n_0
    SLICE_X54Y57         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.812 r  u_dut/io_result_payload_mant[34]_INST_0_i_29/CO[3]
                         net (fo=1, routed)           0.000     2.812    u_dut/io_result_payload_mant[34]_INST_0_i_29_n_0
    SLICE_X54Y58         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.929 r  u_dut/io_result_payload_mant[34]_INST_0_i_24/CO[3]
                         net (fo=1, routed)           0.000     2.929    u_dut/io_result_payload_mant[34]_INST_0_i_24_n_0
    SLICE_X54Y59         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.046 r  u_dut/io_result_payload_mant[34]_INST_0_i_13/CO[3]
                         net (fo=1, routed)           0.000     3.046    u_dut/io_result_payload_mant[34]_INST_0_i_13_n_0
    SLICE_X54Y60         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.163 r  u_dut/io_result_payload_mant[34]_INST_0_i_12/CO[3]
                         net (fo=1, routed)           0.000     3.163    u_dut/io_result_payload_mant[34]_INST_0_i_12_n_0
    SLICE_X54Y61         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.280 r  u_dut/io_result_payload_mant[11]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.280    u_dut/io_result_payload_mant[11]_INST_0_i_11_n_0
    SLICE_X54Y62         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.397 r  u_dut/io_result_payload_mant[15]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.397    u_dut/io_result_payload_mant[15]_INST_0_i_11_n_0
    SLICE_X54Y63         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.514 r  u_dut/io_result_payload_mant[19]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[19]_INST_0_i_11_n_0
    SLICE_X54Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.631 r  u_dut/io_result_payload_mant[23]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.631    u_dut/io_result_payload_mant[23]_INST_0_i_11_n_0
    SLICE_X54Y65         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.748 r  u_dut/io_result_payload_mant[27]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.748    u_dut/io_result_payload_mant[27]_INST_0_i_11_n_0
    SLICE_X54Y66         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.865 f  u_dut/io_result_payload_mant[31]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.865    u_dut/io_result_payload_mant[31]_INST_0_i_11_n_0
    SLICE_X54Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.982 f  u_dut/io_result_payload_exp[1]_INST_0_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.982    u_dut/io_result_payload_exp[1]_INST_0_i_3_n_0
    SLICE_X54Y68         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.315     4.297 r  u_dut/io_result_payload_exp[1]_INST_0_i_2/O[3]
                         net (fo=80, routed)          0.728     5.025    u_dut/n2_exp_mul_adj1
    SLICE_X52Y65         LUT4 (Prop_lut4_I1_O)        0.307     5.332 r  u_dut/io_result_payload_mant[3]_INST_0_i_17/O
                         net (fo=1, routed)           0.165     5.497    u_dut/io_result_payload_mant[3]_INST_0_i_17_n_0
    SLICE_X52Y65         LUT6 (Prop_lut6_I0_O)        0.124     5.621 r  u_dut/io_result_payload_mant[3]_INST_0_i_13/O
                         net (fo=1, routed)           0.417     6.038    u_dut/io_result_payload_mant[3]_INST_0_i_13_n_0
    SLICE_X52Y66         LUT6 (Prop_lut6_I2_O)        0.124     6.162 r  u_dut/io_result_payload_mant[3]_INST_0_i_11/O
                         net (fo=1, routed)           0.000     6.162    u_dut/io_result_payload_mant[3]_INST_0_i_11_n_0
    SLICE_X52Y66         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     6.675 r  u_dut/io_result_payload_mant[3]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.675    u_dut/io_result_payload_mant[3]_INST_0_i_2_n_0
    SLICE_X52Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.792 r  u_dut/io_result_payload_mant[7]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.792    u_dut/io_result_payload_mant[7]_INST_0_i_2_n_0
    SLICE_X52Y68         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.909 r  u_dut/io_result_payload_mant[11]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.909    u_dut/io_result_payload_mant[11]_INST_0_i_2_n_0
    SLICE_X52Y69         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.026 r  u_dut/io_result_payload_mant[15]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.026    u_dut/io_result_payload_mant[15]_INST_0_i_2_n_0
    SLICE_X52Y70         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.143 r  u_dut/io_result_payload_mant[19]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.143    u_dut/io_result_payload_mant[19]_INST_0_i_2_n_0
    SLICE_X52Y71         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.260 r  u_dut/io_result_payload_mant[23]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.260    u_dut/io_result_payload_mant[23]_INST_0_i_2_n_0
    SLICE_X52Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.377 r  u_dut/io_result_payload_mant[27]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.377    u_dut/io_result_payload_mant[27]_INST_0_i_2_n_0
    SLICE_X52Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.494 r  u_dut/io_result_payload_mant[31]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.494    u_dut/io_result_payload_mant[31]_INST_0_i_2_n_0
    SLICE_X52Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.611 f  u_dut/io_result_payload_mant[34]_INST_0_i_4/CO[3]
                         net (fo=3, routed)           0.611     8.222    u_dut/_zz_n2_mant_mul_rounded_1[35]
    SLICE_X51Y73         LUT5 (Prop_lut5_I4_O)        0.124     8.346 f  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=4, routed)           0.325     8.671    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X51Y74         LUT6 (Prop_lut6_I2_O)        0.124     8.795 r  u_dut/io_result_payload_exp[6]_INST_0_i_1/O
                         net (fo=6, routed)           0.558     9.353    u_dut/io_result_payload_exp[6]_INST_0_i_1_n_0
    SLICE_X48Y74         LUT6 (Prop_lut6_I4_O)        0.124     9.477 r  u_dut/io_result_payload_mant[34]_INST_0_i_5/O
                         net (fo=1, routed)           0.689    10.167    u_dut/io_result_payload_mant[34]_INST_0_i_5_n_0
    SLICE_X49Y74         LUT6 (Prop_lut6_I1_O)        0.124    10.291 r  u_dut/io_result_payload_mant[34]_INST_0_i_1/O
                         net (fo=35, routed)          0.648    10.938    u_dut/io_result_payload_mant[34]_INST_0_i_1_n_0
    SLICE_X51Y75         LUT5 (Prop_lut5_I4_O)        0.124    11.062 r  u_dut/io_result_payload_mant[8]_INST_0/O
                         net (fo=1, routed)           0.000    11.062    dut_y[8]
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=333, unset)          0.924     7.591    clk
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X51Y75         FDRE (Setup_fdre_C_D)        0.032     7.588    y_r_reg[8]
  -------------------------------------------------------------------
                         required time                          7.588    
                         arrival time                         -11.062    
  -------------------------------------------------------------------
                         slack                                 -3.474    

Slack (VIOLATED) :        -3.474ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        10.089ns  (logic 5.319ns (52.719%)  route 4.770ns (47.281%))
  Logic Levels:           31  (CARRY4=23 LUT4=1 LUT5=2 LUT6=5)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.973     0.973    u_dut/clk
    SLICE_X55Y55         FDRE                                         r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y55         FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/Q
                         net (fo=2, routed)           0.629     2.058    u_dut/n2_n1_mant_mul_reg__0_n_105
    SLICE_X54Y55         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520     2.578 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/CO[3]
                         net (fo=1, routed)           0.000     2.578    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X54Y56         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.695 r  u_dut/io_result_payload_mant[34]_INST_0_i_34/CO[3]
                         net (fo=1, routed)           0.000     2.695    u_dut/io_result_payload_mant[34]_INST_0_i_34_n_0
    SLICE_X54Y57         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.812 r  u_dut/io_result_payload_mant[34]_INST_0_i_29/CO[3]
                         net (fo=1, routed)           0.000     2.812    u_dut/io_result_payload_mant[34]_INST_0_i_29_n_0
    SLICE_X54Y58         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.929 r  u_dut/io_result_payload_mant[34]_INST_0_i_24/CO[3]
                         net (fo=1, routed)           0.000     2.929    u_dut/io_result_payload_mant[34]_INST_0_i_24_n_0
    SLICE_X54Y59         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.046 r  u_dut/io_result_payload_mant[34]_INST_0_i_13/CO[3]
                         net (fo=1, routed)           0.000     3.046    u_dut/io_result_payload_mant[34]_INST_0_i_13_n_0
    SLICE_X54Y60         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.163 f  u_dut/io_result_payload_mant[34]_INST_0_i_12/CO[3]
                         net (fo=1, routed)           0.000     3.163    u_dut/io_result_payload_mant[34]_INST_0_i_12_n_0
    SLICE_X54Y61         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.280 r  u_dut/io_result_payload_mant[11]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.280    u_dut/io_result_payload_mant[11]_INST_0_i_11_n_0
    SLICE_X54Y62         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.397 r  u_dut/io_result_payload_mant[15]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.397    u_dut/io_result_payload_mant[15]_INST_0_i_11_n_0
    SLICE_X54Y63         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.514 r  u_dut/io_result_payload_mant[19]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[19]_INST_0_i_11_n_0
    SLICE_X54Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.631 r  u_dut/io_result_payload_mant[23]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.631    u_dut/io_result_payload_mant[23]_INST_0_i_11_n_0
    SLICE_X54Y65         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.748 r  u_dut/io_result_payload_mant[27]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.748    u_dut/io_result_payload_mant[27]_INST_0_i_11_n_0
    SLICE_X54Y66         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.865 f  u_dut/io_result_payload_mant[31]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.865    u_dut/io_result_payload_mant[31]_INST_0_i_11_n_0
    SLICE_X54Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.982 f  u_dut/io_result_payload_exp[1]_INST_0_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.982    u_dut/io_result_payload_exp[1]_INST_0_i_3_n_0
    SLICE_X54Y68         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.315     4.297 r  u_dut/io_result_payload_exp[1]_INST_0_i_2/O[3]
                         net (fo=80, routed)          0.728     5.025    u_dut/n2_exp_mul_adj1
    SLICE_X52Y65         LUT4 (Prop_lut4_I1_O)        0.307     5.332 r  u_dut/io_result_payload_mant[3]_INST_0_i_17/O
                         net (fo=1, routed)           0.165     5.497    u_dut/io_result_payload_mant[3]_INST_0_i_17_n_0
    SLICE_X52Y65         LUT6 (Prop_lut6_I0_O)        0.124     5.621 r  u_dut/io_result_payload_mant[3]_INST_0_i_13/O
                         net (fo=1, routed)           0.417     6.038    u_dut/io_result_payload_mant[3]_INST_0_i_13_n_0
    SLICE_X52Y66         LUT6 (Prop_lut6_I2_O)        0.124     6.162 r  u_dut/io_result_payload_mant[3]_INST_0_i_11/O
                         net (fo=1, routed)           0.000     6.162    u_dut/io_result_payload_mant[3]_INST_0_i_11_n_0
    SLICE_X52Y66         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     6.675 r  u_dut/io_result_payload_mant[3]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.675    u_dut/io_result_payload_mant[3]_INST_0_i_2_n_0
    SLICE_X52Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.792 r  u_dut/io_result_payload_mant[7]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.792    u_dut/io_result_payload_mant[7]_INST_0_i_2_n_0
    SLICE_X52Y68         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.909 r  u_dut/io_result_payload_mant[11]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.909    u_dut/io_result_payload_mant[11]_INST_0_i_2_n_0
    SLICE_X52Y69         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.026 r  u_dut/io_result_payload_mant[15]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.026    u_dut/io_result_payload_mant[15]_INST_0_i_2_n_0
    SLICE_X52Y70         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.143 r  u_dut/io_result_payload_mant[19]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.143    u_dut/io_result_payload_mant[19]_INST_0_i_2_n_0
    SLICE_X52Y71         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.260 r  u_dut/io_result_payload_mant[23]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.260    u_dut/io_result_payload_mant[23]_INST_0_i_2_n_0
    SLICE_X52Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.377 r  u_dut/io_result_payload_mant[27]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.377    u_dut/io_result_payload_mant[27]_INST_0_i_2_n_0
    SLICE_X52Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.494 r  u_dut/io_result_payload_mant[31]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.494    u_dut/io_result_payload_mant[31]_INST_0_i_2_n_0
    SLICE_X52Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.611 f  u_dut/io_result_payload_mant[34]_INST_0_i_4/CO[3]
                         net (fo=3, routed)           0.611     8.222    u_dut/_zz_n2_mant_mul_rounded_1[35]
    SLICE_X51Y73         LUT5 (Prop_lut5_I4_O)        0.124     8.346 f  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=4, routed)           0.325     8.671    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X51Y74         LUT6 (Prop_lut6_I2_O)        0.124     8.795 r  u_dut/io_result_payload_exp[6]_INST_0_i_1/O
                         net (fo=6, routed)           0.558     9.353    u_dut/io_result_payload_exp[6]_INST_0_i_1_n_0
    SLICE_X48Y74         LUT6 (Prop_lut6_I4_O)        0.124     9.477 r  u_dut/io_result_payload_mant[34]_INST_0_i_5/O
                         net (fo=1, routed)           0.689    10.167    u_dut/io_result_payload_mant[34]_INST_0_i_5_n_0
    SLICE_X49Y74         LUT6 (Prop_lut6_I1_O)        0.124    10.291 r  u_dut/io_result_payload_mant[34]_INST_0_i_1/O
                         net (fo=35, routed)          0.648    10.938    u_dut/io_result_payload_mant[34]_INST_0_i_1_n_0
    SLICE_X51Y75         LUT5 (Prop_lut5_I4_O)        0.124    11.062 r  u_dut/io_result_payload_mant[8]_INST_0/O
                         net (fo=1, routed)           0.000    11.062    dut_y[8]
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=333, unset)          0.924     7.591    clk
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X51Y75         FDRE (Setup_fdre_C_D)        0.032     7.588    y_r_reg[8]
  -------------------------------------------------------------------
                         required time                          7.588    
                         arrival time                         -11.062    
  -------------------------------------------------------------------
                         slack                                 -3.474    

Slack (VIOLATED) :        -3.474ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        10.089ns  (logic 5.319ns (52.719%)  route 4.770ns (47.281%))
  Logic Levels:           31  (CARRY4=23 LUT4=1 LUT5=2 LUT6=5)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.973     0.973    u_dut/clk
    SLICE_X55Y55         FDRE                                         r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y55         FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/Q
                         net (fo=2, routed)           0.629     2.058    u_dut/n2_n1_mant_mul_reg__0_n_105
    SLICE_X54Y55         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520     2.578 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/CO[3]
                         net (fo=1, routed)           0.000     2.578    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X54Y56         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.695 r  u_dut/io_result_payload_mant[34]_INST_0_i_34/CO[3]
                         net (fo=1, routed)           0.000     2.695    u_dut/io_result_payload_mant[34]_INST_0_i_34_n_0
    SLICE_X54Y57         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.812 r  u_dut/io_result_payload_mant[34]_INST_0_i_29/CO[3]
                         net (fo=1, routed)           0.000     2.812    u_dut/io_result_payload_mant[34]_INST_0_i_29_n_0
    SLICE_X54Y58         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.929 r  u_dut/io_result_payload_mant[34]_INST_0_i_24/CO[3]
                         net (fo=1, routed)           0.000     2.929    u_dut/io_result_payload_mant[34]_INST_0_i_24_n_0
    SLICE_X54Y59         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.046 r  u_dut/io_result_payload_mant[34]_INST_0_i_13/CO[3]
                         net (fo=1, routed)           0.000     3.046    u_dut/io_result_payload_mant[34]_INST_0_i_13_n_0
    SLICE_X54Y60         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.163 r  u_dut/io_result_payload_mant[34]_INST_0_i_12/CO[3]
                         net (fo=1, routed)           0.000     3.163    u_dut/io_result_payload_mant[34]_INST_0_i_12_n_0
    SLICE_X54Y61         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.280 r  u_dut/io_result_payload_mant[11]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.280    u_dut/io_result_payload_mant[11]_INST_0_i_11_n_0
    SLICE_X54Y62         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.397 r  u_dut/io_result_payload_mant[15]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.397    u_dut/io_result_payload_mant[15]_INST_0_i_11_n_0
    SLICE_X54Y63         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.514 r  u_dut/io_result_payload_mant[19]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[19]_INST_0_i_11_n_0
    SLICE_X54Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.631 r  u_dut/io_result_payload_mant[23]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.631    u_dut/io_result_payload_mant[23]_INST_0_i_11_n_0
    SLICE_X54Y65         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.748 r  u_dut/io_result_payload_mant[27]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.748    u_dut/io_result_payload_mant[27]_INST_0_i_11_n_0
    SLICE_X54Y66         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.865 r  u_dut/io_result_payload_mant[31]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.865    u_dut/io_result_payload_mant[31]_INST_0_i_11_n_0
    SLICE_X54Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.982 r  u_dut/io_result_payload_exp[1]_INST_0_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.982    u_dut/io_result_payload_exp[1]_INST_0_i_3_n_0
    SLICE_X54Y68         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.315     4.297 r  u_dut/io_result_payload_exp[1]_INST_0_i_2/O[3]
                         net (fo=80, routed)          0.728     5.025    u_dut/n2_exp_mul_adj1
    SLICE_X52Y65         LUT4 (Prop_lut4_I1_O)        0.307     5.332 r  u_dut/io_result_payload_mant[3]_INST_0_i_17/O
                         net (fo=1, routed)           0.165     5.497    u_dut/io_result_payload_mant[3]_INST_0_i_17_n_0
    SLICE_X52Y65         LUT6 (Prop_lut6_I0_O)        0.124     5.621 r  u_dut/io_result_payload_mant[3]_INST_0_i_13/O
                         net (fo=1, routed)           0.417     6.038    u_dut/io_result_payload_mant[3]_INST_0_i_13_n_0
    SLICE_X52Y66         LUT6 (Prop_lut6_I2_O)        0.124     6.162 r  u_dut/io_result_payload_mant[3]_INST_0_i_11/O
                         net (fo=1, routed)           0.000     6.162    u_dut/io_result_payload_mant[3]_INST_0_i_11_n_0
    SLICE_X52Y66         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     6.675 r  u_dut/io_result_payload_mant[3]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.675    u_dut/io_result_payload_mant[3]_INST_0_i_2_n_0
    SLICE_X52Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.792 f  u_dut/io_result_payload_mant[7]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.792    u_dut/io_result_payload_mant[7]_INST_0_i_2_n_0
    SLICE_X52Y68         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.909 r  u_dut/io_result_payload_mant[11]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.909    u_dut/io_result_payload_mant[11]_INST_0_i_2_n_0
    SLICE_X52Y69         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.026 r  u_dut/io_result_payload_mant[15]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.026    u_dut/io_result_payload_mant[15]_INST_0_i_2_n_0
    SLICE_X52Y70         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.143 r  u_dut/io_result_payload_mant[19]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.143    u_dut/io_result_payload_mant[19]_INST_0_i_2_n_0
    SLICE_X52Y71         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.260 r  u_dut/io_result_payload_mant[23]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.260    u_dut/io_result_payload_mant[23]_INST_0_i_2_n_0
    SLICE_X52Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.377 r  u_dut/io_result_payload_mant[27]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.377    u_dut/io_result_payload_mant[27]_INST_0_i_2_n_0
    SLICE_X52Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.494 r  u_dut/io_result_payload_mant[31]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.494    u_dut/io_result_payload_mant[31]_INST_0_i_2_n_0
    SLICE_X52Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.611 f  u_dut/io_result_payload_mant[34]_INST_0_i_4/CO[3]
                         net (fo=3, routed)           0.611     8.222    u_dut/_zz_n2_mant_mul_rounded_1[35]
    SLICE_X51Y73         LUT5 (Prop_lut5_I4_O)        0.124     8.346 f  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=4, routed)           0.325     8.671    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X51Y74         LUT6 (Prop_lut6_I2_O)        0.124     8.795 r  u_dut/io_result_payload_exp[6]_INST_0_i_1/O
                         net (fo=6, routed)           0.558     9.353    u_dut/io_result_payload_exp[6]_INST_0_i_1_n_0
    SLICE_X48Y74         LUT6 (Prop_lut6_I4_O)        0.124     9.477 r  u_dut/io_result_payload_mant[34]_INST_0_i_5/O
                         net (fo=1, routed)           0.689    10.167    u_dut/io_result_payload_mant[34]_INST_0_i_5_n_0
    SLICE_X49Y74         LUT6 (Prop_lut6_I1_O)        0.124    10.291 r  u_dut/io_result_payload_mant[34]_INST_0_i_1/O
                         net (fo=35, routed)          0.648    10.938    u_dut/io_result_payload_mant[34]_INST_0_i_1_n_0
    SLICE_X51Y75         LUT5 (Prop_lut5_I4_O)        0.124    11.062 r  u_dut/io_result_payload_mant[8]_INST_0/O
                         net (fo=1, routed)           0.000    11.062    dut_y[8]
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=333, unset)          0.924     7.591    clk
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X51Y75         FDRE (Setup_fdre_C_D)        0.032     7.588    y_r_reg[8]
  -------------------------------------------------------------------
                         required time                          7.588    
                         arrival time                         -11.062    
  -------------------------------------------------------------------
                         slack                                 -3.474    

Slack (VIOLATED) :        -3.474ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        10.089ns  (logic 5.319ns (52.719%)  route 4.770ns (47.281%))
  Logic Levels:           31  (CARRY4=23 LUT4=1 LUT5=2 LUT6=5)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.973     0.973    u_dut/clk
    SLICE_X55Y55         FDRE                                         r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y55         FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/io_result_payload_mant[3]_INST_0_i_21_psdsp/Q
                         net (fo=2, routed)           0.629     2.058    u_dut/n2_n1_mant_mul_reg__0_n_105
    SLICE_X54Y55         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520     2.578 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/CO[3]
                         net (fo=1, routed)           0.000     2.578    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X54Y56         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.695 r  u_dut/io_result_payload_mant[34]_INST_0_i_34/CO[3]
                         net (fo=1, routed)           0.000     2.695    u_dut/io_result_payload_mant[34]_INST_0_i_34_n_0
    SLICE_X54Y57         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.812 r  u_dut/io_result_payload_mant[34]_INST_0_i_29/CO[3]
                         net (fo=1, routed)           0.000     2.812    u_dut/io_result_payload_mant[34]_INST_0_i_29_n_0
    SLICE_X54Y58         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     2.929 r  u_dut/io_result_payload_mant[34]_INST_0_i_24/CO[3]
                         net (fo=1, routed)           0.000     2.929    u_dut/io_result_payload_mant[34]_INST_0_i_24_n_0
    SLICE_X54Y59         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.046 r  u_dut/io_result_payload_mant[34]_INST_0_i_13/CO[3]
                         net (fo=1, routed)           0.000     3.046    u_dut/io_result_payload_mant[34]_INST_0_i_13_n_0
    SLICE_X54Y60         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.163 r  u_dut/io_result_payload_mant[34]_INST_0_i_12/CO[3]
                         net (fo=1, routed)           0.000     3.163    u_dut/io_result_payload_mant[34]_INST_0_i_12_n_0
    SLICE_X54Y61         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.280 r  u_dut/io_result_payload_mant[11]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.280    u_dut/io_result_payload_mant[11]_INST_0_i_11_n_0
    SLICE_X54Y62         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.397 r  u_dut/io_result_payload_mant[15]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.397    u_dut/io_result_payload_mant[15]_INST_0_i_11_n_0
    SLICE_X54Y63         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.514 r  u_dut/io_result_payload_mant[19]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[19]_INST_0_i_11_n_0
    SLICE_X54Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.631 r  u_dut/io_result_payload_mant[23]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.631    u_dut/io_result_payload_mant[23]_INST_0_i_11_n_0
    SLICE_X54Y65         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.748 r  u_dut/io_result_payload_mant[27]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.748    u_dut/io_result_payload_mant[27]_INST_0_i_11_n_0
    SLICE_X54Y66         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.865 r  u_dut/io_result_payload_mant[31]_INST_0_i_11/CO[3]
                         net (fo=1, routed)           0.000     3.865    u_dut/io_result_payload_mant[31]_INST_0_i_11_n_0
    SLICE_X54Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.982 f  u_dut/io_result_payload_exp[1]_INST_0_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.982    u_dut/io_result_payload_exp[1]_INST_0_i_3_n_0
    SLICE_X54Y68         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.315     4.297 r  u_dut/io_result_payload_exp[1]_INST_0_i_2/O[3]
                         net (fo=80, routed)          0.728     5.025    u_dut/n2_exp_mul_adj1
    SLICE_X52Y65         LUT4 (Prop_lut4_I1_O)        0.307     5.332 r  u_dut/io_result_payload_mant[3]_INST_0_i_17/O
                         net (fo=1, routed)           0.165     5.497    u_dut/io_result_payload_mant[3]_INST_0_i_17_n_0
    SLICE_X52Y65         LUT6 (Prop_lut6_I0_O)        0.124     5.621 r  u_dut/io_result_payload_mant[3]_INST_0_i_13/O
                         net (fo=1, routed)           0.417     6.038    u_dut/io_result_payload_mant[3]_INST_0_i_13_n_0
    SLICE_X52Y66         LUT6 (Prop_lut6_I2_O)        0.124     6.162 r  u_dut/io_result_payload_mant[3]_INST_0_i_11/O
                         net (fo=1, routed)           0.000     6.162    u_dut/io_result_payload_mant[3]_INST_0_i_11_n_0
    SLICE_X52Y66         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     6.675 r  u_dut/io_result_payload_mant[3]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.675    u_dut/io_result_payload_mant[3]_INST_0_i_2_n_0
    SLICE_X52Y67         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.792 f  u_dut/io_result_payload_mant[7]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.792    u_dut/io_result_payload_mant[7]_INST_0_i_2_n_0
    SLICE_X52Y68         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     6.909 r  u_dut/io_result_payload_mant[11]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     6.909    u_dut/io_result_payload_mant[11]_INST_0_i_2_n_0
    SLICE_X52Y69         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.026 r  u_dut/io_result_payload_mant[15]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.026    u_dut/io_result_payload_mant[15]_INST_0_i_2_n_0
    SLICE_X52Y70         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.143 r  u_dut/io_result_payload_mant[19]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.143    u_dut/io_result_payload_mant[19]_INST_0_i_2_n_0
    SLICE_X52Y71         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.260 r  u_dut/io_result_payload_mant[23]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.260    u_dut/io_result_payload_mant[23]_INST_0_i_2_n_0
    SLICE_X52Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.377 r  u_dut/io_result_payload_mant[27]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.377    u_dut/io_result_payload_mant[27]_INST_0_i_2_n_0
    SLICE_X52Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.494 r  u_dut/io_result_payload_mant[31]_INST_0_i_2/CO[3]
                         net (fo=1, routed)           0.000     7.494    u_dut/io_result_payload_mant[31]_INST_0_i_2_n_0
    SLICE_X52Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     7.611 f  u_dut/io_result_payload_mant[34]_INST_0_i_4/CO[3]
                         net (fo=3, routed)           0.611     8.222    u_dut/_zz_n2_mant_mul_rounded_1[35]
    SLICE_X51Y73         LUT5 (Prop_lut5_I4_O)        0.124     8.346 f  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=4, routed)           0.325     8.671    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X51Y74         LUT6 (Prop_lut6_I2_O)        0.124     8.795 r  u_dut/io_result_payload_exp[6]_INST_0_i_1/O
                         net (fo=6, routed)           0.558     9.353    u_dut/io_result_payload_exp[6]_INST_0_i_1_n_0
    SLICE_X48Y74         LUT6 (Prop_lut6_I4_O)        0.124     9.477 r  u_dut/io_result_payload_mant[34]_INST_0_i_5/O
                         net (fo=1, routed)           0.689    10.167    u_dut/io_result_payload_mant[34]_INST_0_i_5_n_0
    SLICE_X49Y74         LUT6 (Prop_lut6_I1_O)        0.124    10.291 r  u_dut/io_result_payload_mant[34]_INST_0_i_1/O
                         net (fo=35, routed)          0.648    10.938    u_dut/io_result_payload_mant[34]_INST_0_i_1_n_0
    SLICE_X51Y75         LUT5 (Prop_lut5_I4_O)        0.124    11.062 r  u_dut/io_result_payload_mant[8]_INST_0/O
                         net (fo=1, routed)           0.000    11.062    dut_y[8]
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=333, unset)          0.924     7.591    clk
    SLICE_X51Y75         FDRE                                         r  y_r_reg[8]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X51Y75         FDRE (Setup_fdre_C_D)        0.032     7.588    y_r_reg[8]
  -------------------------------------------------------------------
                         required time                          7.588    
                         arrival time                         -11.062    
  -------------------------------------------------------------------
                         slack                                 -3.474    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.114ns  (arrival time - required time)
  Source:                 b_r_reg[41]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_b_exp_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.212ns  (logic 0.141ns (66.546%)  route 0.071ns (33.454%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.410     0.410    clk
    SLICE_X44Y75         FDRE                                         r  b_r_reg[41]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y75         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  b_r_reg[41]/Q
                         net (fo=3, routed)           0.071     0.622    u_dut/io_input_payload_b_exp[6]
    SLICE_X44Y75         FDRE                                         r  u_dut/n1_n0_b_exp_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.432     0.432    u_dut/clk
    SLICE_X44Y75         FDRE                                         r  u_dut/n1_n0_b_exp_reg[6]/C
                         clock pessimism              0.000     0.432    
    SLICE_X44Y75         FDRE (Hold_fdre_C_D)         0.076     0.508    u_dut/n1_n0_b_exp_reg[6]
  -------------------------------------------------------------------
                         required time                         -0.508    
                         arrival time                           0.622    
  -------------------------------------------------------------------
                         slack                                  0.114    

Slack (MET) :             0.114ns  (arrival time - required time)
  Source:                 b_r_reg[41]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_b_exp_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.212ns  (logic 0.141ns (66.546%)  route 0.071ns (33.454%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.410     0.410    clk
    SLICE_X44Y75         FDRE                                         r  b_r_reg[41]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y75         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  b_r_reg[41]/Q
                         net (fo=3, routed)           0.071     0.622    u_dut/io_input_payload_b_exp[6]
    SLICE_X44Y75         FDRE                                         f  u_dut/n1_n0_b_exp_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.432     0.432    u_dut/clk
    SLICE_X44Y75         FDRE                                         r  u_dut/n1_n0_b_exp_reg[6]/C
                         clock pessimism              0.000     0.432    
    SLICE_X44Y75         FDRE (Hold_fdre_C_D)         0.076     0.508    u_dut/n1_n0_b_exp_reg[6]
  -------------------------------------------------------------------
                         required time                         -0.508    
                         arrival time                           0.622    
  -------------------------------------------------------------------
                         slack                                  0.114    

Slack (MET) :             0.115ns  (arrival time - required time)
  Source:                 b_r_reg[42]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_b_exp_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.215ns  (logic 0.141ns (65.642%)  route 0.074ns (34.358%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.410     0.410    clk
    SLICE_X44Y75         FDRE                                         r  b_r_reg[42]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y75         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  b_r_reg[42]/Q
                         net (fo=3, routed)           0.074     0.625    u_dut/io_input_payload_b_exp[7]
    SLICE_X44Y75         FDRE                                         r  u_dut/n1_n0_b_exp_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.432     0.432    u_dut/clk
    SLICE_X44Y75         FDRE                                         r  u_dut/n1_n0_b_exp_reg[7]/C
                         clock pessimism              0.000     0.432    
    SLICE_X44Y75         FDRE (Hold_fdre_C_D)         0.078     0.510    u_dut/n1_n0_b_exp_reg[7]
  -------------------------------------------------------------------
                         required time                         -0.510    
                         arrival time                           0.625    
  -------------------------------------------------------------------
                         slack                                  0.115    

Slack (MET) :             0.115ns  (arrival time - required time)
  Source:                 b_r_reg[42]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_b_exp_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.215ns  (logic 0.141ns (65.642%)  route 0.074ns (34.358%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.410     0.410    clk
    SLICE_X44Y75         FDRE                                         r  b_r_reg[42]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y75         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  b_r_reg[42]/Q
                         net (fo=3, routed)           0.074     0.625    u_dut/io_input_payload_b_exp[7]
    SLICE_X44Y75         FDRE                                         f  u_dut/n1_n0_b_exp_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.432     0.432    u_dut/clk
    SLICE_X44Y75         FDRE                                         r  u_dut/n1_n0_b_exp_reg[7]/C
                         clock pessimism              0.000     0.432    
    SLICE_X44Y75         FDRE (Hold_fdre_C_D)         0.078     0.510    u_dut/n1_n0_b_exp_reg[7]
  -------------------------------------------------------------------
                         required time                         -0.510    
                         arrival time                           0.625    
  -------------------------------------------------------------------
                         slack                                  0.115    

Slack (MET) :             0.118ns  (arrival time - required time)
  Source:                 b_r_reg[40]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_b_exp_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.211ns  (logic 0.141ns (66.849%)  route 0.070ns (33.151%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.410     0.410    clk
    SLICE_X44Y75         FDRE                                         r  b_r_reg[40]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y75         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  b_r_reg[40]/Q
                         net (fo=3, routed)           0.070     0.621    u_dut/io_input_payload_b_exp[5]
    SLICE_X44Y75         FDRE                                         r  u_dut/n1_n0_b_exp_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.432     0.432    u_dut/clk
    SLICE_X44Y75         FDRE                                         r  u_dut/n1_n0_b_exp_reg[5]/C
                         clock pessimism              0.000     0.432    
    SLICE_X44Y75         FDRE (Hold_fdre_C_D)         0.071     0.503    u_dut/n1_n0_b_exp_reg[5]
  -------------------------------------------------------------------
                         required time                         -0.503    
                         arrival time                           0.621    
  -------------------------------------------------------------------
                         slack                                  0.118    

Slack (MET) :             0.118ns  (arrival time - required time)
  Source:                 b_r_reg[40]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_b_exp_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.211ns  (logic 0.141ns (66.849%)  route 0.070ns (33.151%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.410     0.410    clk
    SLICE_X44Y75         FDRE                                         r  b_r_reg[40]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y75         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  b_r_reg[40]/Q
                         net (fo=3, routed)           0.070     0.621    u_dut/io_input_payload_b_exp[5]
    SLICE_X44Y75         FDRE                                         f  u_dut/n1_n0_b_exp_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.432     0.432    u_dut/clk
    SLICE_X44Y75         FDRE                                         r  u_dut/n1_n0_b_exp_reg[5]/C
                         clock pessimism              0.000     0.432    
    SLICE_X44Y75         FDRE (Hold_fdre_C_D)         0.071     0.503    u_dut/n1_n0_b_exp_reg[5]
  -------------------------------------------------------------------
                         required time                         -0.503    
                         arrival time                           0.621    
  -------------------------------------------------------------------
                         slack                                  0.118    

Slack (MET) :             0.121ns  (arrival time - required time)
  Source:                 b_r_reg[38]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_b_exp_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.217ns  (logic 0.141ns (64.847%)  route 0.076ns (35.153%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.410     0.410    clk
    SLICE_X44Y74         FDRE                                         r  b_r_reg[38]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y74         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  b_r_reg[38]/Q
                         net (fo=3, routed)           0.076     0.628    u_dut/io_input_payload_b_exp[3]
    SLICE_X44Y74         FDRE                                         r  u_dut/n1_n0_b_exp_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.432     0.432    u_dut/clk
    SLICE_X44Y74         FDRE                                         r  u_dut/n1_n0_b_exp_reg[3]/C
                         clock pessimism              0.000     0.432    
    SLICE_X44Y74         FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/n1_n0_b_exp_reg[3]
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.628    
  -------------------------------------------------------------------
                         slack                                  0.121    

Slack (MET) :             0.121ns  (arrival time - required time)
  Source:                 b_r_reg[38]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_b_exp_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.217ns  (logic 0.141ns (64.847%)  route 0.076ns (35.153%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.410     0.410    clk
    SLICE_X44Y74         FDRE                                         r  b_r_reg[38]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y74         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  b_r_reg[38]/Q
                         net (fo=3, routed)           0.076     0.628    u_dut/io_input_payload_b_exp[3]
    SLICE_X44Y74         FDRE                                         f  u_dut/n1_n0_b_exp_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.432     0.432    u_dut/clk
    SLICE_X44Y74         FDRE                                         r  u_dut/n1_n0_b_exp_reg[3]/C
                         clock pessimism              0.000     0.432    
    SLICE_X44Y74         FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/n1_n0_b_exp_reg[3]
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.628    
  -------------------------------------------------------------------
                         slack                                  0.121    

Slack (MET) :             0.134ns  (arrival time - required time)
  Source:                 b_r_reg[39]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_b_exp_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.231ns  (logic 0.141ns (61.144%)  route 0.090ns (38.856%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.410     0.410    clk
    SLICE_X44Y75         FDRE                                         r  b_r_reg[39]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y75         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  b_r_reg[39]/Q
                         net (fo=3, routed)           0.090     0.641    u_dut/io_input_payload_b_exp[4]
    SLICE_X44Y75         FDRE                                         r  u_dut/n1_n0_b_exp_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.432     0.432    u_dut/clk
    SLICE_X44Y75         FDRE                                         r  u_dut/n1_n0_b_exp_reg[4]/C
                         clock pessimism              0.000     0.432    
    SLICE_X44Y75         FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/n1_n0_b_exp_reg[4]
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.641    
  -------------------------------------------------------------------
                         slack                                  0.134    

Slack (MET) :             0.134ns  (arrival time - required time)
  Source:                 b_r_reg[39]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_b_exp_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.231ns  (logic 0.141ns (61.144%)  route 0.090ns (38.856%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.410     0.410    clk
    SLICE_X44Y75         FDRE                                         r  b_r_reg[39]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y75         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  b_r_reg[39]/Q
                         net (fo=3, routed)           0.090     0.641    u_dut/io_input_payload_b_exp[4]
    SLICE_X44Y75         FDRE                                         f  u_dut/n1_n0_b_exp_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=333, unset)          0.432     0.432    u_dut/clk
    SLICE_X44Y75         FDRE                                         r  u_dut/n1_n0_b_exp_reg[4]/C
                         clock pessimism              0.000     0.432    
    SLICE_X44Y75         FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/n1_n0_b_exp_reg[4]
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.641    
  -------------------------------------------------------------------
                         slack                                  0.134    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.667
Sources:            { clk }

Check Type        Corner  Lib Pin  Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X52Y61  a_r_reg[0]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X53Y57  a_r_reg[10]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X53Y57  a_r_reg[11]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X53Y58  a_r_reg[12]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X52Y58  a_r_reg[13]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X52Y58  a_r_reg[14]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X52Y58  a_r_reg[15]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X52Y58  a_r_reg[16]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X56Y60  a_r_reg[17]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X54Y61  a_r_reg[18]/C
Low Pulse Width   Slow    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X52Y61  a_r_reg[0]/C
Low Pulse Width   Fast    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X52Y61  a_r_reg[0]/C
Low Pulse Width   Slow    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X53Y57  a_r_reg[10]/C
Low Pulse Width   Fast    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X53Y57  a_r_reg[10]/C
Low Pulse Width   Slow    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X53Y57  a_r_reg[11]/C
Low Pulse Width   Fast    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X53Y57  a_r_reg[11]/C
Low Pulse Width   Slow    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X53Y58  a_r_reg[12]/C
Low Pulse Width   Fast    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X53Y58  a_r_reg[12]/C
Low Pulse Width   Slow    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X52Y58  a_r_reg[13]/C
Low Pulse Width   Fast    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X52Y58  a_r_reg[13]/C
High Pulse Width  Slow    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X52Y61  a_r_reg[0]/C
High Pulse Width  Fast    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X52Y61  a_r_reg[0]/C
High Pulse Width  Slow    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X53Y57  a_r_reg[10]/C
High Pulse Width  Fast    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X53Y57  a_r_reg[10]/C
High Pulse Width  Slow    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X53Y57  a_r_reg[11]/C
High Pulse Width  Fast    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X53Y57  a_r_reg[11]/C
High Pulse Width  Slow    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X53Y58  a_r_reg[12]/C
High Pulse Width  Fast    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X53Y58  a_r_reg[12]/C
High Pulse Width  Slow    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X52Y58  a_r_reg[13]/C
High Pulse Width  Fast    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X52Y58  a_r_reg[13]/C



