Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved. Sat May 23 22:34:49 2026 Command Line: /usr/local/diamond/3.14/ispfpga/bin/lin64/synthesis -f /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/lse.synproj Synthesis options: The -a option is ECP5U. The -s option is 6. The -t option is CABGA381. The -d option is LFE5U-12F. Using package CABGA381. Using performance grade 6. ########################################################## ### Lattice Family : ECP5U ### Device : LFE5U-12F ### Package : CABGA381 ### Speed : 6 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Timing Top-level module name = top_flopoco_add_we8_wf17_zynq7000_native_single_f200. Target frequency = 100.000000 MHz. Maximum fanout = 1000. Timing path count = 10 BRAM utilization = 100.000000 % DSP usage = true (default) DSP utilization = 100 % (default) fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = auto Use Carry Chain = true carry_chain_length = 0 Use IO Insertion = TRUE Use IO Reg = FALSE Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = no ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p /usr/local/diamond/3.14/ispfpga/sa5p00/data (searchpath added) -p /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200 (searchpath added) VHDL library = work VHDL design file = /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl VHDL design file = /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/top_flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl NGO file = /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/top_flopoco_add_we8_wf17_zynq7000_native_single_f200.ngo -sdc option: SDC file input is /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/constraints.sdc. -lpf option: Output file option is not used. -vh2008 Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file /usr/local/diamond/3.14/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5u.v. VERI-1482 Compile design. Compile Design Begin INFO - synthesis: The default VHDL library search path is now "/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200". VHDL-1504 Analyzing VHDL file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl. VHDL-1481 INFO - synthesis: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl(24): analyzing entity rightshiftersticky18_by_max_20_freq200_uid4. VHDL-1012 INFO - synthesis: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl(32): analyzing architecture arch. VHDL-1010 INFO - synthesis: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl(113): analyzing entity intadder_21_freq200_uid6. VHDL-1012 INFO - synthesis: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl(121): analyzing architecture arch. VHDL-1010 INFO - synthesis: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl(173): analyzing entity normalizer_z_22_22_22_freq200_uid8. VHDL-1012 INFO - synthesis: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl(180): analyzing architecture arch. VHDL-1010 INFO - synthesis: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl(259): analyzing entity intadder_28_freq200_uid11. VHDL-1012 INFO - synthesis: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl(267): analyzing architecture arch. VHDL-1010 INFO - synthesis: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl(322): analyzing entity flopoco_add_we8_wf17_zynq7000_native_single_f200. VHDL-1012 INFO - synthesis: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl(329): analyzing architecture arch. VHDL-1010 Analyzing VHDL file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/top_flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl. VHDL-1481 INFO - synthesis: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/top_flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl(4): analyzing entity top_flopoco_add_we8_wf17_zynq7000_native_single_f200. VHDL-1012 INFO - synthesis: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/top_flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl(13): analyzing architecture rtl. VHDL-1010 unit top_flopoco_add_we8_wf17_zynq7000_native_single_f200 is not yet analyzed. VHDL-1485 /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/top_flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl(4): executing top_flopoco_add_we8_wf17_zynq7000_native_single_f200(rtl) WARNING - synthesis: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/top_flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl(11): replacing existing netlist top_flopoco_add_we8_wf17_zynq7000_native_single_f200(rtl). VHDL-1205 Top module name (VHDL): top_flopoco_add_we8_wf17_zynq7000_native_single_f200 Loading NGL library '/usr/local/diamond/3.14/ispfpga/sa5p00/data/sa5plib.ngl'... Loading NGL library '/usr/local/diamond/3.14/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library '/usr/local/diamond/3.14/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library '/usr/local/diamond/3.14/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'sa5p25.nph' in environment: /usr/local/diamond/3.14/ispfpga. Package Status: Final Version 1.44. Top-level module name = top_flopoco_add_we8_wf17_zynq7000_native_single_f200. WARNING - synthesis: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl(288): Register \u_dut/roundingAdder/Y_1_d1_i0 is stuck at Zero. VDB-5013 WARNING - synthesis: Bit 21 of Register \u_dut/fracAdder/X_1_d1 is stuck at Zero WARNING - synthesis: Bit 20 of Register \u_dut/fracAdder/X_1_d1 is stuck at Zero WARNING - synthesis: Bit 19 of Register \u_dut/fracAdder/X_1_d1 is stuck at One WARNING - synthesis: Bit 1 of Register \u_dut/fracAdder/X_1_d1 is stuck at Zero WARNING - synthesis: Bit 0 of Register \u_dut/fracAdder/X_1_d1 is stuck at Zero WARNING - synthesis: Bit 21 of Register \u_dut/fracAdder/X_1_d2 is stuck at Zero WARNING - synthesis: Bit 20 of Register \u_dut/fracAdder/X_1_d2 is stuck at Zero WARNING - synthesis: Bit 19 of Register \u_dut/fracAdder/X_1_d2 is stuck at One WARNING - synthesis: Bit 1 of Register \u_dut/fracAdder/X_1_d2 is stuck at Zero WARNING - synthesis: Bit 0 of Register \u_dut/fracAdder/X_1_d2 is stuck at Zero WARNING - synthesis: Bit 21 of Register \u_dut/fracAdder/Y_1_d1 is stuck at Zero WARNING - synthesis: Bit 28 of Register \u_dut/roundingAdder/X_1_d1 is stuck at Zero WARNING - synthesis: Bit 0 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 0 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 0 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 28 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 27 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 26 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 25 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 24 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 23 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 22 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 21 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 20 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 19 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 18 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 17 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 16 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 15 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 14 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 13 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 12 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 11 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 10 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 9 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 8 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 7 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 6 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 5 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 4 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 3 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 2 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 1 of Register \u_dut/roundingAdder/Y_1_d2 is stuck at Zero WARNING - synthesis: Bit 28 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 27 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 26 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 25 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 24 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 23 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 22 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 21 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 20 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 19 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 18 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 17 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 16 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 15 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 14 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 13 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 12 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 11 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 10 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 9 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 8 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 7 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 6 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 5 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 4 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 3 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 2 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 1 of Register \u_dut/roundingAdder/Y_1_d3 is stuck at Zero WARNING - synthesis: Bit 28 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 27 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 26 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 25 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 24 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 23 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 22 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 21 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 20 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 19 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 18 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 17 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 16 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 15 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 14 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 13 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 12 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 11 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 10 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 9 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 8 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 7 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 6 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 5 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 4 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 3 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 2 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero WARNING - synthesis: Bit 1 of Register \u_dut/roundingAdder/Y_1_d4 is stuck at Zero Duplicate register/latch removal. \u_dut/EffSubVector_d1_i1 is a one-to-one match with \u_dut/EffSub_d1_63. ######## GSR will not be inferred in an NGO flow, unless force_gsr=yes. WARNING - synthesis: No .lpf file will be written because the -lpf option is not used or is set to zero. Results of NGD DRC are available in top_flopoco_add_we8_wf17_zynq7000_native_single_f200_drc.log. WARNING - synthesis: DRC checking was skipped because the -ngo option was used. Writing NGD file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-diamond/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/top_flopoco_add_we8_wf17_zynq7000_native_single_f200.ngo. ################### Begin Area Report (top_flopoco_add_we8_wf17_zynq7000_native_single_f200)###################### Number of register bits => 272 of 12687 (2 % ) CCU2C => 51 FD1S3AX => 234 FD1S3IX => 38 GSR => 1 IB => 57 LUT4 => 300 OB => 28 PDPW16KD => 1 PFUMX => 5 ################### End Area Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 1 Net : clk_c, loads : 273 Clock Enable Nets Number of Clock Enables: 0 Top 0 highest fanout Clock Enables: Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : swap_N_6, loads : 62 Net : u_dut/LZCAndShifter/nZerosNew_2, loads : 26 Net : u_dut/RightShifterComponent/n2986, loads : 25 Net : u_dut/fracYpadXorOp_20, loads : 22 Net : u_dut/RightShifterComponent/ps_d1_1, loads : 22 Net : u_dut/LZCAndShifter/level2_20, loads : 20 Net : u_dut/RightShifterComponent/ps_d1_0, loads : 20 Net : u_dut/LZCAndShifter/level1_21, loads : 20 Net : u_dut/shiftVal_2, loads : 19 Net : u_dut/LZCAndShifter/count4, loads : 18 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 10.000000 | | | -waveform { 0.000000 5.000000 } -name | | | clk [ get_ports { clk } ] | 100.000 MHz| 66.348 MHz| 20 * | | | -------------------------------------------------------------------------------- 1 constraints not met. Peak Memory Usage: 259.375 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 2.057 secs --------------------------------------------------------------