/----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3) -- Executing script file `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_mul_w8_m18_base/yosys.ys' -- 1. Executing Verilog-2005 frontend: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v Parsing SystemVerilog input from `/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v' to AST representation. Generating RTLIL representation for module `\_zkf_pack'. Generating RTLIL representation for module `\_zkf_pack_delay'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v Parsing SystemVerilog input from `/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v' to AST representation. Generating RTLIL representation for module `\zkf_mul'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_mul_w8_m18_base/src/top_zkf_mul_w8_m18_base.v Parsing SystemVerilog input from `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_mul_w8_m18_base/src/top_zkf_mul_w8_m18_base.v' to AST representation. Generating RTLIL representation for module `\top_zkf_mul_w8_m18_base'. Successfully finished Verilog frontend. 4. Executing SYNTH_LATTICE pass. 4.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\VLO'. Generating RTLIL representation for module `\VHI'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\DP16KD'. Replacing existing blackbox module `\FD1P3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:2.1-2.261. Generating RTLIL representation for module `\FD1P3AX'. Replacing existing blackbox module `\FD1P3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:3.1-3.261. Generating RTLIL representation for module `\FD1P3AY'. Replacing existing blackbox module `\FD1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:4.1-4.261. Generating RTLIL representation for module `\FD1P3BX'. Replacing existing blackbox module `\FD1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:5.1-5.261. Generating RTLIL representation for module `\FD1P3DX'. Replacing existing blackbox module `\FD1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:6.1-6.261. Generating RTLIL representation for module `\FD1P3IX'. Replacing existing blackbox module `\FD1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:7.1-7.261. Generating RTLIL representation for module `\FD1P3JX'. Replacing existing blackbox module `\FD1S3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:8.1-8.261. Generating RTLIL representation for module `\FD1S3AX'. Replacing existing blackbox module `\FD1S3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:9.1-9.261. Generating RTLIL representation for module `\FD1S3AY'. Replacing existing blackbox module `\FD1S3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:10.1-10.261. Generating RTLIL representation for module `\FD1S3BX'. Replacing existing blackbox module `\FD1S3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:11.1-11.261. Generating RTLIL representation for module `\FD1S3DX'. Replacing existing blackbox module `\FD1S3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:12.1-12.261. Generating RTLIL representation for module `\FD1S3IX'. Replacing existing blackbox module `\FD1S3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:13.1-13.261. Generating RTLIL representation for module `\FD1S3JX'. Replacing existing blackbox module `\IFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:26.1-26.301. Generating RTLIL representation for module `\IFS1P3BX'. Replacing existing blackbox module `\IFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:27.1-27.301. Generating RTLIL representation for module `\IFS1P3DX'. Replacing existing blackbox module `\IFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:28.1-28.301. Generating RTLIL representation for module `\IFS1P3IX'. Replacing existing blackbox module `\IFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:29.1-29.301. Generating RTLIL representation for module `\IFS1P3JX'. Replacing existing blackbox module `\OFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:31.1-31.302. Generating RTLIL representation for module `\OFS1P3BX'. Replacing existing blackbox module `\OFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:32.1-32.302. Generating RTLIL representation for module `\OFS1P3DX'. Replacing existing blackbox module `\OFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:33.1-33.302. Generating RTLIL representation for module `\OFS1P3IX'. Replacing existing blackbox module `\OFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:34.1-34.302. Generating RTLIL representation for module `\OFS1P3JX'. Replacing existing blackbox module `\IB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:2.1-2.157. Generating RTLIL representation for module `\IB'. Replacing existing blackbox module `\IBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:3.1-3.157. Generating RTLIL representation for module `\IBPU'. Replacing existing blackbox module `\IBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:4.1-4.157. Generating RTLIL representation for module `\IBPD'. Replacing existing blackbox module `\OB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:5.1-5.157. Generating RTLIL representation for module `\OB'. Replacing existing blackbox module `\OBZ' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:6.1-6.164. Generating RTLIL representation for module `\OBZ'. Replacing existing blackbox module `\OBZPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:7.1-7.164. Generating RTLIL representation for module `\OBZPU'. Replacing existing blackbox module `\OBZPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:8.1-8.164. Generating RTLIL representation for module `\OBZPD'. Replacing existing blackbox module `\OBCO' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:9.1-9.90. Generating RTLIL representation for module `\OBCO'. Replacing existing blackbox module `\BB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:10.1-10.179. Generating RTLIL representation for module `\BB'. Replacing existing blackbox module `\BBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:11.1-11.179. Generating RTLIL representation for module `\BBPU'. Replacing existing blackbox module `\BBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:12.1-12.179. Generating RTLIL representation for module `\BBPD'. Replacing existing blackbox module `\ILVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:13.1-13.139. Generating RTLIL representation for module `\ILVDS'. Replacing existing blackbox module `\OLVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:14.1-14.146. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 4.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DCUA'. Successfully finished Verilog frontend. 4.3. Executing HIERARCHY pass (managing design hierarchy). 4.3.1. Analyzing design hierarchy.. Top module: \top_zkf_mul_w8_m18_base Used module: \zkf_mul Used module: \_zkf_pack Parameter \WEXP = 6 Parameter \WMAN = 18 Parameter \STAGE_OUTPUT = 0 4.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_pack'. Parameter \WEXP = 6 Parameter \WMAN = 18 Parameter \STAGE_OUTPUT = 0 Generating RTLIL representation for module `$paramod$675ec1474bf954e7f473e995bb3ba11c2185af00\_zkf_pack'. Parameter \WEXP = 8 Parameter \WMAN = 18 Parameter \STAGE_PRODUCT = 0 Parameter \STAGE_OUTPUT = 0 4.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\zkf_mul'. Parameter \WEXP = 8 Parameter \WMAN = 18 Parameter \STAGE_PRODUCT = 0 Parameter \STAGE_OUTPUT = 0 Generating RTLIL representation for module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. 4.3.4. Analyzing design hierarchy.. Top module: \top_zkf_mul_w8_m18_base Used module: $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul Used module: \_zkf_pack Parameter \WEXP = 8 Parameter \WMAN = 18 Parameter \STAGE_OUTPUT = 0 4.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_pack'. Parameter \WEXP = 8 Parameter \WMAN = 18 Parameter \STAGE_OUTPUT = 0 Generating RTLIL representation for module `$paramod$fd955d6c5ad1b45d4ea0b7728598a7e5012c6e65\_zkf_pack'. 4.3.6. Analyzing design hierarchy.. Top module: \top_zkf_mul_w8_m18_base Used module: $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul Used module: $paramod$fd955d6c5ad1b45d4ea0b7728598a7e5012c6e65\_zkf_pack 4.3.7. Analyzing design hierarchy.. Top module: \top_zkf_mul_w8_m18_base Used module: $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul Used module: $paramod$fd955d6c5ad1b45d4ea0b7728598a7e5012c6e65\_zkf_pack Removing unused module `$paramod$675ec1474bf954e7f473e995bb3ba11c2185af00\_zkf_pack'. Removing unused module `\zkf_mul'. Removing unused module `\_zkf_pack_delay'. Removing unused module `\_zkf_pack'. Removed 4 unused modules. 4.4. Executing PROC pass (convert processes to netlists). 4.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_mul_w8_m18_base/src/top_zkf_mul_w8_m18_base.v:34$58 in module top_zkf_mul_w8_m18_base. Marked 1 switch rules as full_case in process $proc$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:211$339 in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. Removed a total of 0 dead cases. 4.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 3 redundant assignments. Promoted 8 assignments to connections. 4.4.4. Executing PROC_INIT pass (extract init attributes). 4.4.5. Executing PROC_ARST pass (detect async resets in processes). 4.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 4.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\top_zkf_mul_w8_m18_base.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_mul_w8_m18_base/src/top_zkf_mul_w8_m18_base.v:34$58'. 1/2: $0\out_valid_r[0:0] 2/2: $0\in_valid_r[0:0] Creating decoders for process `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$proc$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:211$339'. 1/1: $0\s1_valid[0:0] 4.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 4.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\top_zkf_mul_w8_m18_base.\a_r' using process `\top_zkf_mul_w8_m18_base.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_mul_w8_m18_base/src/top_zkf_mul_w8_m18_base.v:34$58'. created $dff cell `$procdff$385' with positive edge clock. Creating register for signal `\top_zkf_mul_w8_m18_base.\b_r' using process `\top_zkf_mul_w8_m18_base.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_mul_w8_m18_base/src/top_zkf_mul_w8_m18_base.v:34$58'. created $dff cell `$procdff$386' with positive edge clock. Creating register for signal `\top_zkf_mul_w8_m18_base.\in_valid_r' using process `\top_zkf_mul_w8_m18_base.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_mul_w8_m18_base/src/top_zkf_mul_w8_m18_base.v:34$58'. created $dff cell `$procdff$387' with positive edge clock. Creating register for signal `\top_zkf_mul_w8_m18_base.\y_r' using process `\top_zkf_mul_w8_m18_base.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_mul_w8_m18_base/src/top_zkf_mul_w8_m18_base.v:34$58'. created $dff cell `$procdff$388' with positive edge clock. Creating register for signal `\top_zkf_mul_w8_m18_base.\out_valid_r' using process `\top_zkf_mul_w8_m18_base.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_mul_w8_m18_base/src/top_zkf_mul_w8_m18_base.v:34$58'. created $dff cell `$procdff$389' with positive edge clock. Creating register for signal `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.\s1_valid' using process `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$proc$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:211$339'. created $dff cell `$procdff$390' with positive edge clock. Creating register for signal `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.\s1_sign' using process `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$proc$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:211$339'. created $dff cell `$procdff$391' with positive edge clock. Creating register for signal `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.\s1_mag' using process `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$proc$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:211$339'. created $dff cell `$procdff$392' with positive edge clock. Creating register for signal `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.\s1_exp_unbiased_base' using process `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$proc$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:211$339'. created $dff cell `$procdff$393' with positive edge clock. Creating register for signal `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.\s1_force_zero' using process `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$proc$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:211$339'. created $dff cell `$procdff$394' with positive edge clock. Creating register for signal `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.\s1_force_inf' using process `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$proc$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:211$339'. created $dff cell `$procdff$395' with positive edge clock. 4.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 4.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\top_zkf_mul_w8_m18_base.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_mul_w8_m18_base/src/top_zkf_mul_w8_m18_base.v:34$58'. Removing empty process `top_zkf_mul_w8_m18_base.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_mul_w8_m18_base/src/top_zkf_mul_w8_m18_base.v:34$58'. Found and cleaned up 1 empty switch in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$proc$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:211$339'. Removing empty process `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$proc$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:211$339'. Cleaned up 2 empty switches. 4.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_mul_w8_m18_base. Optimizing module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. Optimizing module $paramod$fd955d6c5ad1b45d4ea0b7728598a7e5012c6e65\_zkf_pack. 4.5. Executing CHECK pass (checking for obvious problems). Checking module top_zkf_mul_w8_m18_base... Checking module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul... Checking module $paramod$fd955d6c5ad1b45d4ea0b7728598a7e5012c6e65\_zkf_pack... Found and reported 0 problems. 4.6. Executing FLATTEN pass (flatten design). Keeping top_zkf_mul_w8_m18_base.u_dut (found keep_hierarchy attribute). Deleting now unused module $paramod$fd955d6c5ad1b45d4ea0b7728598a7e5012c6e65\_zkf_pack. 4.7. Executing TRIBUF pass. 4.8. Executing DEMINOUT pass (demote inout ports to input or output). 4.9. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_mul_w8_m18_base. Optimizing module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. 4.10. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. Removed 0 unused cells and 47 unused wires. 4.11. Executing CHECK pass (checking for obvious problems). Checking module top_zkf_mul_w8_m18_base... Checking module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul... Found and reported 0 problems. 4.12. Executing OPT pass (performing simple optimizations). 4.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_mul_w8_m18_base. Optimizing module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. 4.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_mul_w8_m18_base'. Computing hashes of 8 cells of `\top_zkf_mul_w8_m18_base'. Finding duplicate cells in `\top_zkf_mul_w8_m18_base'. Finding identical cells in module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 63 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 60 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Removed a total of 3 cells. 4.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_mul_w8_m18_base.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $ternary$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:202$335: \s1_mag [35:18] -> { 1'1 \s1_mag [34:18] } Analyzing evaluation results. Removed 0 multiplexer ports. 4.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_mul_w8_m18_base. Optimizing cells in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. Performed a total of 0 changes. 4.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_mul_w8_m18_base'. Computing hashes of 8 cells of `\top_zkf_mul_w8_m18_base'. Finding duplicate cells in `\top_zkf_mul_w8_m18_base'. Finding identical cells in module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 60 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Removed a total of 0 cells. 4.12.6. Executing OPT_DFF pass (perform DFF optimizations). 4.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. Removed 0 unused cells and 3 unused wires. 4.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_mul_w8_m18_base. Optimizing module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. 4.12.9. Rerunning OPT passes. (Maybe there is more to do..) 4.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_mul_w8_m18_base.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_mul_w8_m18_base. Optimizing cells in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. Performed a total of 0 changes. 4.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_mul_w8_m18_base'. Computing hashes of 8 cells of `\top_zkf_mul_w8_m18_base'. Finding duplicate cells in `\top_zkf_mul_w8_m18_base'. Finding identical cells in module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 60 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Removed a total of 0 cells. 4.12.13. Executing OPT_DFF pass (perform DFF optimizations). 4.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. 4.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_mul_w8_m18_base. Optimizing module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. 4.12.16. Finished fast OPT passes. (There is nothing left to do.) 4.13. Executing FSM pass (extract and optimize FSM). 4.13.1. Executing FSM_DETECT pass (finding FSMs in design). 4.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). 4.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). 4.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. 4.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). 4.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 4.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 4.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 4.14. Executing OPT pass (performing simple optimizations). 4.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_mul_w8_m18_base. Optimizing module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. 4.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_mul_w8_m18_base'. Computing hashes of 8 cells of `\top_zkf_mul_w8_m18_base'. Finding duplicate cells in `\top_zkf_mul_w8_m18_base'. Finding identical cells in module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 60 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Removed a total of 0 cells. 4.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_mul_w8_m18_base.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_mul_w8_m18_base. Optimizing cells in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. Performed a total of 0 changes. 4.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_mul_w8_m18_base'. Computing hashes of 8 cells of `\top_zkf_mul_w8_m18_base'. Finding duplicate cells in `\top_zkf_mul_w8_m18_base'. Finding identical cells in module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 60 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Removed a total of 0 cells. 4.14.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $procdff$387 ($dff) from module top_zkf_mul_w8_m18_base (D = \in_valid_i, Q = \in_valid_r, rval = 1'0). Adding SRST signal on $procdff$389 ($dff) from module top_zkf_mul_w8_m18_base (D = \dut_valid, Q = \out_valid_r, rval = 1'0). Adding SRST signal on $procdff$390 ($dff) from module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul (D = \in_valid, Q = \s1_valid, rval = 1'0). 4.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. Removed 3 unused cells and 3 unused wires. 4.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_mul_w8_m18_base. Optimizing module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. 4.14.9. Rerunning OPT passes. (Maybe there is more to do..) 4.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_mul_w8_m18_base.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_mul_w8_m18_base. Optimizing cells in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. Performed a total of 0 changes. 4.14.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_mul_w8_m18_base'. Computing hashes of 6 cells of `\top_zkf_mul_w8_m18_base'. Finding duplicate cells in `\top_zkf_mul_w8_m18_base'. Finding identical cells in module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 59 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Removed a total of 0 cells. 4.14.13. Executing OPT_DFF pass (perform DFF optimizations). 4.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. 4.14.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_mul_w8_m18_base. Optimizing module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. 4.14.16. Finished fast OPT passes. (There is nothing left to do.) 4.15. Executing WREDUCE pass (reducing word size of cells). Removed top 1 bits (of 10) from port A of cell $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$add$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:79$327 ($add). Removed top 1 bits (of 10) from port B of cell $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$add$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:79$327 ($add). Converting cell $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$add$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:79$327 ($add) from signed to unsigned. Removed top 1 bits (of 9) from port A of cell $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$add$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:79$327 ($add). Removed top 1 bits (of 9) from port B of cell $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$add$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:79$327 ($add). Removed top 1 bits (of 10) from port Y of cell $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$add$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:79$327 ($add). Removed top 1 bits (of 10) from port B of cell $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$sub$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:79$329 ($sub). Converting cell $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$sub$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:79$329 ($sub) from signed to unsigned. Removed top 1 bits (of 10) from port A of cell $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$sub$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:79$329 ($sub). Removed top 1 bits (of 9) from port B of cell $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$sub$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:79$329 ($sub). Removed top 9 bits (of 10) from mux cell $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$ternary$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:182$331 ($mux). Removed top 8 bits (of 10) from port B of cell $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$add$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:184$332 ($add). Removed top 25 bits (of 26) from port B of cell $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:92$351 ($add). Converting cell $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:69$341 ($add) from unsigned to signed. Removed top 1 bits (of 11) from port A of cell $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:69$341 ($add). Removed top 3 bits (of 11) from port B of cell $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:69$341 ($add). Removed top 1 bits (of 10) from wire $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.$add$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:79$327_Y. Removed top 9 bits (of 10) from wire $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.s1_exp_adjust. 4.16. Executing PEEPOPT pass (run peephole optimizers). 4.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. Removed 0 unused cells and 2 unused wires. 4.18. Executing SHARE pass (SAT-based resource sharing). 4.19. Executing TECHMAP pass (map to technology primitives). 4.19.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 4.19.2. Continuing TECHMAP pass. No more expansions possible. 4.20. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_mul_w8_m18_base. Optimizing module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. 4.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. 4.22. Executing TECHMAP pass (map to technology primitives). 4.22.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 4.22.2. Continuing TECHMAP pass. Using template $paramod$55e849a2191f17b159b997340cb0ebb72d635590\_80_mul for cells of type $mul. No more expansions possible. 4.23. Executing TECHMAP pass (map to technology primitives). 4.23.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. Generating RTLIL representation for module `$__MUL18X18'. Successfully finished Verilog frontend. 4.23.2. Continuing TECHMAP pass. Using template $paramod$6d12bf30e693aad43884066ff41c02c3d61c4f33$__MUL18X18 for cells of type $__MUL18X18. No more expansions possible. 4.24. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top_zkf_mul_w8_m18_base: created 0 $alu and 0 $macc cells. Extracting $alu and $macc cells in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul: creating $macc model for $flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:92$351 ($add). creating $macc model for $flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:69$341 ($add). creating $macc model for $add$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:184$332 ($add). creating $macc model for $sub$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:79$329 ($sub). creating $macc model for $add$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:79$327 ($add). merging $macc model for $add$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:79$327 into $sub$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:79$329. creating $alu model for $macc $add$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:184$332. creating $alu model for $macc $flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:69$341. creating $alu model for $macc $flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:92$351. creating $macc cell for $sub$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:79$329: $auto$alumacc.cc:382:replace_macc$405 creating $alu cell for $flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:92$351: $auto$alumacc.cc:512:replace_alu$406 creating $alu cell for $flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:69$341: $auto$alumacc.cc:512:replace_alu$409 creating $alu cell for $add$/mnt/storage/zubax/kulibin2/float/hdl/zkf_mul.v:184$332: $auto$alumacc.cc:512:replace_alu$412 created 3 $alu and 1 $macc cells. 4.25. Executing OPT pass (performing simple optimizations). 4.25.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_mul_w8_m18_base. Optimizing module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. 4.25.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_mul_w8_m18_base'. Computing hashes of 6 cells of `\top_zkf_mul_w8_m18_base'. Finding duplicate cells in `\top_zkf_mul_w8_m18_base'. Finding identical cells in module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 59 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Removed a total of 0 cells. 4.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_mul_w8_m18_base.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_mul_w8_m18_base. Optimizing cells in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. Performed a total of 0 changes. 4.25.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_mul_w8_m18_base'. Computing hashes of 6 cells of `\top_zkf_mul_w8_m18_base'. Finding duplicate cells in `\top_zkf_mul_w8_m18_base'. Finding identical cells in module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 59 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Removed a total of 0 cells. 4.25.6. Executing OPT_DFF pass (perform DFF optimizations). 4.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. Removed 1 unused cells and 10 unused wires. 4.25.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_mul_w8_m18_base. Optimizing module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. 4.25.9. Rerunning OPT passes. (Maybe there is more to do..) 4.25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_mul_w8_m18_base.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_mul_w8_m18_base. Optimizing cells in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. Performed a total of 0 changes. 4.25.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_mul_w8_m18_base'. Computing hashes of 6 cells of `\top_zkf_mul_w8_m18_base'. Finding duplicate cells in `\top_zkf_mul_w8_m18_base'. Finding identical cells in module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 58 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Removed a total of 0 cells. 4.25.13. Executing OPT_DFF pass (perform DFF optimizations). 4.25.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. 4.25.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_mul_w8_m18_base. Optimizing module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. 4.25.16. Finished fast OPT passes. (There is nothing left to do.) 4.26. Executing MEMORY pass. 4.26.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 4.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 4.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 4.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 4.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 4.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. 4.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 4.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 4.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. 4.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). 4.27. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. 4.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). 4.29. Executing TECHMAP pass (map to technology primitives). 4.29.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 4.29.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v' to AST representation. Generating RTLIL representation for module `$__DP16KD_'. Generating RTLIL representation for module `$__PDPW16KD_'. Successfully finished Verilog frontend. 4.29.3. Continuing TECHMAP pass. No more expansions possible. 4.30. Executing OPT pass (performing simple optimizations). 4.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_mul_w8_m18_base. Optimizing module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. 4.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_mul_w8_m18_base'. Computing hashes of 6 cells of `\top_zkf_mul_w8_m18_base'. Finding duplicate cells in `\top_zkf_mul_w8_m18_base'. Finding identical cells in module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 57 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Removed a total of 0 cells. 4.30.3. Executing OPT_DFF pass (perform DFF optimizations). 4.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. 4.30.5. Finished fast OPT passes. 4.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 4.32. Executing OPT pass (performing simple optimizations). 4.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_mul_w8_m18_base. Optimizing module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. 4.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_mul_w8_m18_base'. Computing hashes of 6 cells of `\top_zkf_mul_w8_m18_base'. Finding duplicate cells in `\top_zkf_mul_w8_m18_base'. Finding identical cells in module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 57 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Removed a total of 0 cells. 4.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_mul_w8_m18_base.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_mul_w8_m18_base. Optimizing cells in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. Performed a total of 0 changes. 4.32.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_mul_w8_m18_base'. Computing hashes of 6 cells of `\top_zkf_mul_w8_m18_base'. Finding duplicate cells in `\top_zkf_mul_w8_m18_base'. Finding identical cells in module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 57 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Removed a total of 0 cells. 4.32.6. Executing OPT_DFF pass (perform DFF optimizations). 4.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. 4.32.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_mul_w8_m18_base. Optimizing module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. 4.32.9. Finished fast OPT passes. (There is nothing left to do.) 4.33. Executing TECHMAP pass (map to technology primitives). 4.33.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 4.33.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. Generating RTLIL representation for module `\_80_ccu2c_alu'. Successfully finished Verilog frontend. 4.33.3. Continuing TECHMAP pass. Using template $paramod$b1ed770e5c6a32495d5bf09fda6cf0327bb52128\_80_ccu2c_alu for cells of type $alu. Using template $paramod$8105d46316cb99041c6dc3f486b2ad084df41ba8\_80_ccu2c_alu for cells of type $alu. Using template $paramod$a8151eed7df109f18d5adf1169b40bb7b9e884a8\_80_ccu2c_alu for cells of type $alu. Using extmapper maccmap for cells of type $macc_v2. add \a [24:17] (8 bits, unsigned) add \b [24:17] (8 bits, unsigned) add 10'1100000010 (10 bits, unsigned) Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $logic_or. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $reduce_and. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000001010 for cells of type $fa. Using template $paramod$484d51534650924b7ed4c69e46eed3a56904771f\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using extmapper simplemap for cells of type $or. No more expansions possible. 4.34. Executing OPT pass (performing simple optimizations). 4.34.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_mul_w8_m18_base. Optimizing module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. 4.34.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_mul_w8_m18_base'. Computing hashes of 81 cells of `\top_zkf_mul_w8_m18_base'. Finding duplicate cells in `\top_zkf_mul_w8_m18_base'. Finding identical cells in module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 394 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 375 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 372 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 371 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Removed a total of 23 cells. 4.34.3. Executing OPT_DFF pass (perform DFF optimizations). 4.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. Removed 101 unused cells and 228 unused wires. 4.34.5. Finished fast OPT passes. 4.35. Executing ABC pass (technology mapping using ABC). 4.35.1. Summary of detected clock domains: 3 cells in clk=\clk, en={ }, arst={ }, srst=\rst 78 cells in clk=\clk, en={ }, arst={ }, srst={ } 4.35.2. Extracting gate netlist of module `\top_zkf_mul_w8_m18_base' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by \rst 4.35.3. Extracting gate netlist of module `\top_zkf_mul_w8_m18_base' to `/input.blif'.. Found matching posedge clock domain: \clk 4.35.3.1. Executed ABC. Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 2 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 4.35.3.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 4 ABC RESULTS: DFF cells: 2 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 2 ABC RESULTS: output signals: 2 Removing temp directory. 4.35.3.1. Executed ABC. Extracted 78 gates and 156 wires to a netlist network with 78 inputs and 78 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 78 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 4.35.3.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 156 ABC RESULTS: DFF cells: 78 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 78 ABC RESULTS: output signals: 78 Removing temp directory. 4.35.4. Summary of detected clock domains: 1 cells in clk={ }, en={ }, arst={ }, srst={ } 3 cells in clk=\clk, en={ }, arst={ }, srst=\rst 266 cells in clk=\clk, en={ }, arst={ }, srst={ } 4.35.5. Extracting gate netlist of module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 4.35.6. Extracting gate netlist of module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by \rst 4.35.7. Extracting gate netlist of module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul' to `/input.blif'.. Found matching posedge clock domain: \clk 4.35.7.1. Executed ABC. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 4.35.7.1. Executed ABC. Extracted 3 gates and 5 wires to a netlist network with 2 inputs and 1 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 4.35.7.2. Re-integrating ABC results. ABC RESULTS: ANDNOT cells: 1 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 1 ABC RESULTS: internal signals: 2 ABC RESULTS: input signals: 2 ABC RESULTS: output signals: 1 Removing temp directory. 4.35.7.1. Executed ABC. Extracted 236 gates and 338 wires to a netlist network with 100 inputs and 72 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 49 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 4.35.7.2. Re-integrating ABC results. ABC RESULTS: AND cells: 62 ABC RESULTS: ANDNOT cells: 3 ABC RESULTS: BUF cells: 41 ABC RESULTS: DFF cells: 33 ABC RESULTS: MUX cells: 18 ABC RESULTS: NAND cells: 27 ABC RESULTS: NOR cells: 24 ABC RESULTS: OR cells: 2 ABC RESULTS: ORNOT cells: 2 ABC RESULTS: XNOR cells: 1 ABC RESULTS: XOR cells: 8 ABC RESULTS: internal signals: 166 ABC RESULTS: input signals: 100 ABC RESULTS: output signals: 72 Removing temp directory. Removing global temp directory. 4.36. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. Removed 0 unused cells and 630 unused wires. 4.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 4.38. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_mul_w8_m18_base'. Computing hashes of 81 cells of `\top_zkf_mul_w8_m18_base'. Finding duplicate cells in `\top_zkf_mul_w8_m18_base'. Finding identical cells in module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Computing hashes of 213 cells of `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Finding duplicate cells in `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul'. Removed a total of 0 cells. 4.39. Executing TECHMAP pass (map to technology primitives). 4.39.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 4.39.2. Continuing TECHMAP pass. Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. No more expansions possible. 4.40. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_mul_w8_m18_base. Optimizing module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. 4.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). 4.42. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in top_zkf_mul_w8_m18_base. Handling GSR in $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. 4.43. Executing ATTRMVCP pass (move or copy attributes). 4.44. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_mul_w8_m18_base.. Finding unused cells or wires in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul.. Removed 0 unused cells and 459 unused wires. 4.45. Executing ABC pass (technology mapping using ABC). 4.45.1. Extracting gate netlist of module `\top_zkf_mul_w8_m18_base' to `/input.blif'.. 4.45.1.1. Executed ABC. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 4.45.2. Extracting gate netlist of module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul' to `/input.blif'.. 4.45.2.1. Executed ABC. Extracted 148 gates and 245 wires to a netlist network with 97 inputs and 65 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 4.45.2.2. Re-integrating ABC results. ABC RESULTS: AND cells: 60 ABC RESULTS: ANDNOT cells: 5 ABC RESULTS: MUX cells: 18 ABC RESULTS: NAND cells: 27 ABC RESULTS: NOR cells: 23 ABC RESULTS: OR cells: 3 ABC RESULTS: ORNOT cells: 1 ABC RESULTS: XNOR cells: 1 ABC RESULTS: XOR cells: 8 ABC RESULTS: internal signals: 83 ABC RESULTS: input signals: 97 ABC RESULTS: output signals: 65 Removing temp directory. Removing global temp directory. 4.46. Executing TECHMAP pass (map to technology primitives). 4.46.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v' to AST representation. Generating RTLIL representation for module `$_DLATCH_N_'. Generating RTLIL representation for module `$_DLATCH_P_'. Successfully finished Verilog frontend. 4.46.2. Continuing TECHMAP pass. No more expansions possible. 4.47. Executing ABC pass (technology mapping using ABC). 4.47.1. Summary of detected clock domains: 81 cells in clk={ }, en={ }, arst={ }, srst={ } 4.47.2. Extracting gate netlist of module `\top_zkf_mul_w8_m18_base' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 4.47.2.1. Executed ABC. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 4.47.3. Summary of detected clock domains: 211 cells in clk={ }, en={ }, arst={ }, srst={ } 4.47.4. Extracting gate netlist of module `$paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 4.47.4.1. Executed ABC. Extracted 146 gates and 243 wires to a netlist network with 97 inputs and 65 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_lut /lutdefs.txt ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + dress /input.blif ABC: Total number of equiv classes = 81. ABC: Participating nodes from both networks = 160. ABC: Participating nodes from the first network = 80. ( 91.95 % of nodes) ABC: Participating nodes from the second network = 80. ( 91.95 % of nodes) ABC: Node pairs (any polarity) = 80. ( 91.95 % of names can be moved) ABC: Node pairs (same polarity) = 77. ( 88.51 % of names can be moved) ABC: Total runtime = 0.15 sec ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 4.47.4.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 86 ABC RESULTS: internal signals: 81 ABC RESULTS: input signals: 97 ABC RESULTS: output signals: 65 Removing temp directory. Removing global temp directory. Removed 0 unused cells and 488 unused wires. 4.48. Executing TECHMAP pass (map to technology primitives). 4.48.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `$lut'. Successfully finished Verilog frontend. 4.48.2. Continuing TECHMAP pass. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f$lut for cells of type $lut. Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut. Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8$lut for cells of type $lut. Using template $paramod$c24ed72ebb67e9ead6029e42e909ef7fc0abbb11$lut for cells of type $lut. Using template $paramod$4a3b52f0ff954dd8ed3855717db25116f663e2a8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. No more expansions possible. 4.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in top_zkf_mul_w8_m18_base. Optimizing LUTs in $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul. Optimizing lut $abc$2254$auto$blifparse.cc:557:parse_blif$2256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$2254$auto$blifparse.cc:557:parse_blif$2269.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Removed 0 unused cells and 191 unused wires. 4.50. Executing AUTONAME pass. Renamed 80 objects in module top_zkf_mul_w8_m18_base (4 iterations). Renamed 197 objects in module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul (51 iterations). 4.51. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `top_zkf_mul_w8_m18_base'. Setting top module to top_zkf_mul_w8_m18_base. 4.51.1. Analyzing design hierarchy.. Top module: \top_zkf_mul_w8_m18_base Used module: $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul 4.51.2. Analyzing design hierarchy.. Top module: \top_zkf_mul_w8_m18_base Used module: $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul Removed 0 unused modules. 4.52. Printing statistics. === top_zkf_mul_w8_m18_base === +----------Local Count, excluding submodules. | 14 wires 189 wire bits 14 public wires 189 public wire bits 7 ports 82 port bits 81 submodules 1 $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul 80 TRELLIS_FF === $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul === +----------Local Count, excluding submodules. | 92 wires 789 wire bits 92 public wires 789 public wire bits 7 ports 82 port bits 2 cells 1 $scopeinfo 1 MULT18X18D 153 submodules 29 CCU2C 88 LUT4 2 PFUMX 34 TRELLIS_FF === design hierarchy === +----------Count including submodules. | 2 top_zkf_mul_w8_m18_base 2 $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul +----------Count including submodules. | 106 wires 978 wire bits 106 public wires 978 public wire bits 14 ports 164 port bits - memories - memory bits - processes 2 cells 1 $scopeinfo 1 MULT18X18D 81 submodules 1 $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul 80 TRELLIS_FF 4.53. Executing CHECK pass (checking for obvious problems). Checking module top_zkf_mul_w8_m18_base... Checking module $paramod$a16795aa979ebe91261a649fd198e39220b1e512\zkf_mul... Found and reported 0 problems. 4.54. Executing JSON backend. End of script. Logfile hash: 5b8d395347, time: 3.66s, user: 0.90s, system: 0.06s, MEM: 31.36 MB peak Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3) Time spent: 37% 19x read_verilog (0 sec), 36% 3x abc (0 sec), ... $ yosys -s /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_mul_w8_m18_base/yosys.ys [exit code 0]