/----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3) -- Executing script file `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_div_w8_m18_base/yosys.ys' -- 1. Executing Verilog-2005 frontend: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v Parsing SystemVerilog input from `/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v' to AST representation. Generating RTLIL representation for module `\_zkf_pack'. Generating RTLIL representation for module `\_zkf_pack_delay'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_pipe.v Parsing SystemVerilog input from `/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pipe.v' to AST representation. Generating RTLIL representation for module `\_zkf_pipe'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v Parsing SystemVerilog input from `/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v' to AST representation. Generating RTLIL representation for module `\_zkf_div_core'. Warning: Replacing memory \r_rem with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:138 Warning: Replacing memory \r_den3 with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:137 Warning: Replacing memory \r_den with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:136 Warning: Replacing memory \r_div0 with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:135 Warning: Replacing memory \r_force_inf with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:134 Warning: Replacing memory \r_force_zero with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:133 Warning: Replacing memory \r_exp_unbiased with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:132 Warning: Replacing memory \r_sign with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:131 Warning: Replacing memory \r_valid with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:127 Generating RTLIL representation for module `\_zkf_div_raw_stage'. Generating RTLIL representation for module `\_zkf_div_radix4_step'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: /mnt/storage/zubax/kulibin2/float/hdl/zkf_div.v Parsing SystemVerilog input from `/mnt/storage/zubax/kulibin2/float/hdl/zkf_div.v' to AST representation. Generating RTLIL representation for module `\zkf_div'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_div_w8_m18_base/src/top_zkf_div_w8_m18_base.v Parsing SystemVerilog input from `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_div_w8_m18_base/src/top_zkf_div_w8_m18_base.v' to AST representation. Generating RTLIL representation for module `\top_zkf_div_w8_m18_base'. Successfully finished Verilog frontend. 6. Executing SYNTH_LATTICE pass. 6.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\VLO'. Generating RTLIL representation for module `\VHI'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\DP16KD'. Replacing existing blackbox module `\FD1P3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:2.1-2.261. Generating RTLIL representation for module `\FD1P3AX'. Replacing existing blackbox module `\FD1P3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:3.1-3.261. Generating RTLIL representation for module `\FD1P3AY'. Replacing existing blackbox module `\FD1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:4.1-4.261. Generating RTLIL representation for module `\FD1P3BX'. Replacing existing blackbox module `\FD1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:5.1-5.261. Generating RTLIL representation for module `\FD1P3DX'. Replacing existing blackbox module `\FD1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:6.1-6.261. Generating RTLIL representation for module `\FD1P3IX'. Replacing existing blackbox module `\FD1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:7.1-7.261. Generating RTLIL representation for module `\FD1P3JX'. Replacing existing blackbox module `\FD1S3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:8.1-8.261. Generating RTLIL representation for module `\FD1S3AX'. Replacing existing blackbox module `\FD1S3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:9.1-9.261. Generating RTLIL representation for module `\FD1S3AY'. Replacing existing blackbox module `\FD1S3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:10.1-10.261. Generating RTLIL representation for module `\FD1S3BX'. Replacing existing blackbox module `\FD1S3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:11.1-11.261. Generating RTLIL representation for module `\FD1S3DX'. Replacing existing blackbox module `\FD1S3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:12.1-12.261. Generating RTLIL representation for module `\FD1S3IX'. Replacing existing blackbox module `\FD1S3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:13.1-13.261. Generating RTLIL representation for module `\FD1S3JX'. Replacing existing blackbox module `\IFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:26.1-26.301. Generating RTLIL representation for module `\IFS1P3BX'. Replacing existing blackbox module `\IFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:27.1-27.301. Generating RTLIL representation for module `\IFS1P3DX'. Replacing existing blackbox module `\IFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:28.1-28.301. Generating RTLIL representation for module `\IFS1P3IX'. Replacing existing blackbox module `\IFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:29.1-29.301. Generating RTLIL representation for module `\IFS1P3JX'. Replacing existing blackbox module `\OFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:31.1-31.302. Generating RTLIL representation for module `\OFS1P3BX'. Replacing existing blackbox module `\OFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:32.1-32.302. Generating RTLIL representation for module `\OFS1P3DX'. Replacing existing blackbox module `\OFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:33.1-33.302. Generating RTLIL representation for module `\OFS1P3IX'. Replacing existing blackbox module `\OFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:34.1-34.302. Generating RTLIL representation for module `\OFS1P3JX'. Replacing existing blackbox module `\IB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:2.1-2.157. Generating RTLIL representation for module `\IB'. Replacing existing blackbox module `\IBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:3.1-3.157. Generating RTLIL representation for module `\IBPU'. Replacing existing blackbox module `\IBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:4.1-4.157. Generating RTLIL representation for module `\IBPD'. Replacing existing blackbox module `\OB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:5.1-5.157. Generating RTLIL representation for module `\OB'. Replacing existing blackbox module `\OBZ' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:6.1-6.164. Generating RTLIL representation for module `\OBZ'. Replacing existing blackbox module `\OBZPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:7.1-7.164. Generating RTLIL representation for module `\OBZPU'. Replacing existing blackbox module `\OBZPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:8.1-8.164. Generating RTLIL representation for module `\OBZPD'. Replacing existing blackbox module `\OBCO' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:9.1-9.90. Generating RTLIL representation for module `\OBCO'. Replacing existing blackbox module `\BB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:10.1-10.179. Generating RTLIL representation for module `\BB'. Replacing existing blackbox module `\BBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:11.1-11.179. Generating RTLIL representation for module `\BBPU'. Replacing existing blackbox module `\BBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:12.1-12.179. Generating RTLIL representation for module `\BBPD'. Replacing existing blackbox module `\ILVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:13.1-13.139. Generating RTLIL representation for module `\ILVDS'. Replacing existing blackbox module `\OLVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:14.1-14.146. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 6.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DCUA'. Successfully finished Verilog frontend. 6.3. Executing HIERARCHY pass (managing design hierarchy). 6.3.1. Analyzing design hierarchy.. Top module: \top_zkf_div_w8_m18_base Used module: \zkf_div Used module: \_zkf_pack_delay Used module: \_zkf_pack Used module: \_zkf_div_core Used module: \_zkf_div_raw_stage Used module: \_zkf_div_radix4_step Used module: \_zkf_pipe Parameter \WIN = 19 6.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_div_raw_stage'. Parameter \WIN = 19 Generating RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010011'. Parameter \WMAN = 18 6.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_div_radix4_step'. Parameter \WMAN = 18 Generating RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 17 6.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_div_raw_stage'. Parameter \WIN = 17 Generating RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010001'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 15 6.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_div_raw_stage'. Parameter \WIN = 15 Generating RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001111'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 13 6.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_div_raw_stage'. Parameter \WIN = 13 Generating RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001101'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 11 6.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_div_raw_stage'. Parameter \WIN = 11 Generating RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001011'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 9 6.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_div_raw_stage'. Parameter \WIN = 9 Generating RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001001'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 7 6.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_div_raw_stage'. Parameter \WIN = 7 Generating RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000111'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 5 6.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_div_raw_stage'. Parameter \WIN = 5 Generating RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000101'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 3 6.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_div_raw_stage'. Parameter \WIN = 3 Generating RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000011'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 1 6.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_div_raw_stage'. Parameter \WIN = 1 Generating RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000001'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Reprocessing module _zkf_div_core because instantiated module _zkf_div_radix4_step has become available. Generating RTLIL representation for module `\_zkf_div_core'. Warning: Replacing memory \r_rem with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:138 Warning: Replacing memory \r_den3 with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:137 Warning: Replacing memory \r_den with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:136 Warning: Replacing memory \r_div0 with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:135 Warning: Replacing memory \r_force_inf with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:134 Warning: Replacing memory \r_force_zero with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:133 Warning: Replacing memory \r_exp_unbiased with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:132 Warning: Replacing memory \r_sign with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:131 Warning: Replacing memory \r_valid with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:127 Parameter \W = 1 Parameter \STAGE_OUTPUT = 0 6.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_pack_delay'. Parameter \W = 1 Parameter \STAGE_OUTPUT = 0 Generating RTLIL representation for module `$paramod$b1798e4f7776d4b6f8f2f33461822b434fd6cf47\_zkf_pack_delay'. Parameter \WEXP = 6 Parameter \WMAN = 18 Parameter \STAGE_OUTPUT = 0 6.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_pack'. Parameter \WEXP = 6 Parameter \WMAN = 18 Parameter \STAGE_OUTPUT = 0 Generating RTLIL representation for module `$paramod$675ec1474bf954e7f473e995bb3ba11c2185af00\_zkf_pack'. Parameter \WEXP = 6 Parameter \WMAN = 18 6.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_div_core'. Parameter \WEXP = 6 Parameter \WMAN = 18 Generating RTLIL representation for module `$paramod$a6e93af8078101aff1e34083bdb646ec398e9508\_zkf_div_core'. Warning: Replacing memory \r_rem with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:138 Warning: Replacing memory \r_den3 with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:137 Warning: Replacing memory \r_den with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:136 Warning: Replacing memory \r_div0 with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:135 Warning: Replacing memory \r_force_inf with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:134 Warning: Replacing memory \r_force_zero with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:133 Warning: Replacing memory \r_exp_unbiased with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:132 Warning: Replacing memory \r_sign with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:131 Warning: Replacing memory \r_valid with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:127 Parameter \W = 48 Parameter \N = 0 6.3.16. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_pipe'. Parameter \W = 48 Parameter \N = 0 Generating RTLIL representation for module `$paramod$8afea04472a9eb93c462d16da2207b379229f6a2\_zkf_pipe'. Parameter \WEXP = 8 Parameter \WMAN = 18 Parameter \STAGE_INPUT = 0 Parameter \STAGE_OUTPUT = 0 6.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\zkf_div'. Parameter \WEXP = 8 Parameter \WMAN = 18 Parameter \STAGE_INPUT = 0 Parameter \STAGE_OUTPUT = 0 Generating RTLIL representation for module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. 6.3.18. Analyzing design hierarchy.. Top module: \top_zkf_div_w8_m18_base Used module: $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div Used module: \_zkf_pack_delay Used module: \_zkf_pack Used module: \_zkf_div_core Used module: \_zkf_div_raw_stage Used module: \_zkf_div_radix4_step Used module: \_zkf_pipe Parameter \WIN = 19 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010011'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 17 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010001'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 15 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001111'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 13 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001101'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 11 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001011'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 9 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001001'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 7 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000111'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 5 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000101'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 3 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000011'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 1 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000001'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \W = 1 Parameter \STAGE_OUTPUT = 0 Found cached RTLIL representation for module `$paramod$b1798e4f7776d4b6f8f2f33461822b434fd6cf47\_zkf_pack_delay'. Parameter \WEXP = 8 Parameter \WMAN = 18 Parameter \STAGE_OUTPUT = 0 6.3.19. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_pack'. Parameter \WEXP = 8 Parameter \WMAN = 18 Parameter \STAGE_OUTPUT = 0 Generating RTLIL representation for module `$paramod$fd955d6c5ad1b45d4ea0b7728598a7e5012c6e65\_zkf_pack'. Parameter \WEXP = 8 Parameter \WMAN = 18 6.3.20. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_div_core'. Parameter \WEXP = 8 Parameter \WMAN = 18 Generating RTLIL representation for module `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core'. Warning: Replacing memory \r_rem with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:138 Warning: Replacing memory \r_den3 with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:137 Warning: Replacing memory \r_den with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:136 Warning: Replacing memory \r_div0 with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:135 Warning: Replacing memory \r_force_inf with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:134 Warning: Replacing memory \r_force_zero with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:133 Warning: Replacing memory \r_exp_unbiased with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:132 Warning: Replacing memory \r_sign with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:131 Warning: Replacing memory \r_valid with list of registers. See /mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:127 Parameter \W = 52 Parameter \N = 0 6.3.21. Executing AST frontend in derive mode using pre-parsed AST for module `\_zkf_pipe'. Parameter \W = 52 Parameter \N = 0 Generating RTLIL representation for module `$paramod$2a41383f0bc6a35d237219c395f573952f3279a3\_zkf_pipe'. 6.3.22. Analyzing design hierarchy.. Top module: \top_zkf_div_w8_m18_base Used module: $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div Used module: $paramod$b1798e4f7776d4b6f8f2f33461822b434fd6cf47\_zkf_pack_delay Used module: $paramod$fd955d6c5ad1b45d4ea0b7728598a7e5012c6e65\_zkf_pack Used module: $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core Used module: \_zkf_div_raw_stage Used module: \_zkf_div_radix4_step Used module: $paramod$2a41383f0bc6a35d237219c395f573952f3279a3\_zkf_pipe Parameter \WIN = 19 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010011'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 17 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010001'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 15 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001111'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 13 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001101'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 11 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001011'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 9 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001001'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 7 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000111'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 5 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000101'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 3 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000011'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. Parameter \WIN = 1 Found cached RTLIL representation for module `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000001'. Parameter \WMAN = 18 Found cached RTLIL representation for module `$paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010'. 6.3.23. Analyzing design hierarchy.. Top module: \top_zkf_div_w8_m18_base Used module: $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div Used module: $paramod$b1798e4f7776d4b6f8f2f33461822b434fd6cf47\_zkf_pack_delay Used module: $paramod$fd955d6c5ad1b45d4ea0b7728598a7e5012c6e65\_zkf_pack Used module: $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010011 Used module: $paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010001 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001111 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001101 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001011 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001001 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000111 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000101 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000011 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000001 Used module: $paramod$2a41383f0bc6a35d237219c395f573952f3279a3\_zkf_pipe 6.3.24. Analyzing design hierarchy.. Top module: \top_zkf_div_w8_m18_base Used module: $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div Used module: $paramod$b1798e4f7776d4b6f8f2f33461822b434fd6cf47\_zkf_pack_delay Used module: $paramod$fd955d6c5ad1b45d4ea0b7728598a7e5012c6e65\_zkf_pack Used module: $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010011 Used module: $paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010001 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001111 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001101 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001011 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001001 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000111 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000101 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000011 Used module: $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000001 Used module: $paramod$2a41383f0bc6a35d237219c395f573952f3279a3\_zkf_pipe Removing unused module `$paramod$8afea04472a9eb93c462d16da2207b379229f6a2\_zkf_pipe'. Removing unused module `$paramod$a6e93af8078101aff1e34083bdb646ec398e9508\_zkf_div_core'. Removing unused module `$paramod$675ec1474bf954e7f473e995bb3ba11c2185af00\_zkf_pack'. Removing unused module `\_zkf_div_core'. Removing unused module `\zkf_div'. Removing unused module `\_zkf_div_radix4_step'. Removing unused module `\_zkf_div_raw_stage'. Removing unused module `\_zkf_pipe'. Removing unused module `\_zkf_pack_delay'. Removing unused module `\_zkf_pack'. Removed 10 unused modules. 6.4. Executing PROC pass (convert processes to netlists). 6.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 6.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_div_w8_m18_base/src/top_zkf_div_w8_m18_base.v:37$90 in module top_zkf_div_w8_m18_base. Marked 1 switch rules as full_case in process $proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$613 in module $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core. Marked 1 switch rules as full_case in process $proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$612 in module $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core. Marked 1 switch rules as full_case in process $proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$611 in module $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core. Marked 1 switch rules as full_case in process $proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$610 in module $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core. Marked 1 switch rules as full_case in process $proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$609 in module $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core. Marked 1 switch rules as full_case in process $proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$608 in module $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core. Marked 1 switch rules as full_case in process $proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$607 in module $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core. Marked 1 switch rules as full_case in process $proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$606 in module $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core. Marked 1 switch rules as full_case in process $proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$605 in module $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core. Marked 1 switch rules as full_case in process $proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$604 in module $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core. Marked 1 switch rules as full_case in process $proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:226$598 in module $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core. Marked 1 switch rules as full_case in process $proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:125$593 in module $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core. Removed a total of 0 dead cases. 6.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 14 redundant assignments. Promoted 113 assignments to connections. 6.4.4. Executing PROC_INIT pass (extract init attributes). 6.4.5. Executing PROC_ARST pass (detect async resets in processes). 6.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 6.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000101.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$335'. Creating decoders for process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000111.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$334'. Creating decoders for process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001001.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$333'. Creating decoders for process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001011.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$332'. Creating decoders for process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001101.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$331'. Creating decoders for process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001111.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$330'. Creating decoders for process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010001.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$329'. Creating decoders for process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010011.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$316'. Creating decoders for process `\top_zkf_div_w8_m18_base.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_div_w8_m18_base/src/top_zkf_div_w8_m18_base.v:37$90'. 1/2: $0\out_valid_r[0:0] 2/2: $0\in_valid_r[0:0] Creating decoders for process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$613'. 1/1: $0\r_valid[10][0:0] Creating decoders for process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$612'. 1/1: $0\r_valid[9][0:0] Creating decoders for process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$611'. 1/1: $0\r_valid[8][0:0] Creating decoders for process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$610'. 1/1: $0\r_valid[7][0:0] Creating decoders for process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$609'. 1/1: $0\r_valid[6][0:0] Creating decoders for process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$608'. 1/1: $0\r_valid[5][0:0] Creating decoders for process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$607'. 1/1: $0\r_valid[4][0:0] Creating decoders for process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$606'. 1/1: $0\r_valid[3][0:0] Creating decoders for process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$605'. 1/1: $0\r_valid[2][0:0] Creating decoders for process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$604'. 1/1: $0\r_valid[1][0:0] Creating decoders for process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:226$598'. 1/1: $0\out_valid[0:0] Creating decoders for process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:125$593'. 1/1: $0\r_valid[0][0:0] Creating decoders for process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000001.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$337'. Creating decoders for process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000011.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$336'. 6.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 6.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000101.\raw_next' using process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000101.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$335'. created $dff cell `$procdff$657' with positive edge clock. Creating register for signal `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000111.\raw_next' using process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000111.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$334'. created $dff cell `$procdff$658' with positive edge clock. Creating register for signal `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001001.\raw_next' using process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001001.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$333'. created $dff cell `$procdff$659' with positive edge clock. Creating register for signal `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001011.\raw_next' using process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001011.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$332'. created $dff cell `$procdff$660' with positive edge clock. Creating register for signal `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001101.\raw_next' using process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001101.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$331'. created $dff cell `$procdff$661' with positive edge clock. Creating register for signal `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001111.\raw_next' using process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001111.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$330'. created $dff cell `$procdff$662' with positive edge clock. Creating register for signal `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010001.\raw_next' using process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010001.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$329'. created $dff cell `$procdff$663' with positive edge clock. Creating register for signal `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010011.\raw_next' using process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010011.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$316'. created $dff cell `$procdff$664' with positive edge clock. Creating register for signal `\top_zkf_div_w8_m18_base.\a_r' using process `\top_zkf_div_w8_m18_base.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_div_w8_m18_base/src/top_zkf_div_w8_m18_base.v:37$90'. created $dff cell `$procdff$665' with positive edge clock. Creating register for signal `\top_zkf_div_w8_m18_base.\b_r' using process `\top_zkf_div_w8_m18_base.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_div_w8_m18_base/src/top_zkf_div_w8_m18_base.v:37$90'. created $dff cell `$procdff$666' with positive edge clock. Creating register for signal `\top_zkf_div_w8_m18_base.\in_valid_r' using process `\top_zkf_div_w8_m18_base.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_div_w8_m18_base/src/top_zkf_div_w8_m18_base.v:37$90'. created $dff cell `$procdff$667' with positive edge clock. Creating register for signal `\top_zkf_div_w8_m18_base.\div0_r' using process `\top_zkf_div_w8_m18_base.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_div_w8_m18_base/src/top_zkf_div_w8_m18_base.v:37$90'. created $dff cell `$procdff$668' with positive edge clock. Creating register for signal `\top_zkf_div_w8_m18_base.\y_r' using process `\top_zkf_div_w8_m18_base.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_div_w8_m18_base/src/top_zkf_div_w8_m18_base.v:37$90'. created $dff cell `$procdff$669' with positive edge clock. Creating register for signal `\top_zkf_div_w8_m18_base.\out_valid_r' using process `\top_zkf_div_w8_m18_base.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_div_w8_m18_base/src/top_zkf_div_w8_m18_base.v:37$90'. created $dff cell `$procdff$670' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_valid[10]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$613'. created $dff cell `$procdff$671' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_sign[10]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$613'. created $dff cell `$procdff$672' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_exp_unbiased[10]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$613'. created $dff cell `$procdff$673' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_zero[10]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$613'. created $dff cell `$procdff$674' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_inf[10]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$613'. created $dff cell `$procdff$675' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_div0[10]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$613'. created $dff cell `$procdff$676' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den[10]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$613'. created $dff cell `$procdff$677' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den3[10]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$613'. created $dff cell `$procdff$678' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_rem[10]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$613'. created $dff cell `$procdff$679' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_valid[9]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$612'. created $dff cell `$procdff$680' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_sign[9]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$612'. created $dff cell `$procdff$681' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_exp_unbiased[9]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$612'. created $dff cell `$procdff$682' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_zero[9]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$612'. created $dff cell `$procdff$683' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_inf[9]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$612'. created $dff cell `$procdff$684' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_div0[9]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$612'. created $dff cell `$procdff$685' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den[9]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$612'. created $dff cell `$procdff$686' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den3[9]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$612'. created $dff cell `$procdff$687' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_rem[9]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$612'. created $dff cell `$procdff$688' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_valid[8]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$611'. created $dff cell `$procdff$689' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_sign[8]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$611'. created $dff cell `$procdff$690' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_exp_unbiased[8]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$611'. created $dff cell `$procdff$691' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_zero[8]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$611'. created $dff cell `$procdff$692' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_inf[8]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$611'. created $dff cell `$procdff$693' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_div0[8]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$611'. created $dff cell `$procdff$694' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den[8]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$611'. created $dff cell `$procdff$695' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den3[8]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$611'. created $dff cell `$procdff$696' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_rem[8]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$611'. created $dff cell `$procdff$697' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_valid[7]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$610'. created $dff cell `$procdff$698' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_sign[7]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$610'. created $dff cell `$procdff$699' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_exp_unbiased[7]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$610'. created $dff cell `$procdff$700' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_zero[7]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$610'. created $dff cell `$procdff$701' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_inf[7]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$610'. created $dff cell `$procdff$702' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_div0[7]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$610'. created $dff cell `$procdff$703' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den[7]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$610'. created $dff cell `$procdff$704' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den3[7]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$610'. created $dff cell `$procdff$705' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_rem[7]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$610'. created $dff cell `$procdff$706' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_valid[6]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$609'. created $dff cell `$procdff$707' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_sign[6]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$609'. created $dff cell `$procdff$708' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_exp_unbiased[6]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$609'. created $dff cell `$procdff$709' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_zero[6]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$609'. created $dff cell `$procdff$710' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_inf[6]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$609'. created $dff cell `$procdff$711' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_div0[6]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$609'. created $dff cell `$procdff$712' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den[6]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$609'. created $dff cell `$procdff$713' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den3[6]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$609'. created $dff cell `$procdff$714' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_rem[6]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$609'. created $dff cell `$procdff$715' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_valid[5]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$608'. created $dff cell `$procdff$716' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_sign[5]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$608'. created $dff cell `$procdff$717' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_exp_unbiased[5]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$608'. created $dff cell `$procdff$718' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_zero[5]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$608'. created $dff cell `$procdff$719' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_inf[5]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$608'. created $dff cell `$procdff$720' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_div0[5]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$608'. created $dff cell `$procdff$721' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den[5]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$608'. created $dff cell `$procdff$722' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den3[5]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$608'. created $dff cell `$procdff$723' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_rem[5]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$608'. created $dff cell `$procdff$724' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_valid[4]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$607'. created $dff cell `$procdff$725' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_sign[4]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$607'. created $dff cell `$procdff$726' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_exp_unbiased[4]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$607'. created $dff cell `$procdff$727' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_zero[4]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$607'. created $dff cell `$procdff$728' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_inf[4]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$607'. created $dff cell `$procdff$729' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_div0[4]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$607'. created $dff cell `$procdff$730' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den[4]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$607'. created $dff cell `$procdff$731' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den3[4]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$607'. created $dff cell `$procdff$732' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_rem[4]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$607'. created $dff cell `$procdff$733' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_valid[3]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$606'. created $dff cell `$procdff$734' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_sign[3]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$606'. created $dff cell `$procdff$735' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_exp_unbiased[3]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$606'. created $dff cell `$procdff$736' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_zero[3]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$606'. created $dff cell `$procdff$737' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_inf[3]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$606'. created $dff cell `$procdff$738' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_div0[3]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$606'. created $dff cell `$procdff$739' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den[3]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$606'. created $dff cell `$procdff$740' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den3[3]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$606'. created $dff cell `$procdff$741' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_rem[3]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$606'. created $dff cell `$procdff$742' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_valid[2]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$605'. created $dff cell `$procdff$743' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_sign[2]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$605'. created $dff cell `$procdff$744' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_exp_unbiased[2]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$605'. created $dff cell `$procdff$745' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_zero[2]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$605'. created $dff cell `$procdff$746' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_inf[2]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$605'. created $dff cell `$procdff$747' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_div0[2]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$605'. created $dff cell `$procdff$748' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den[2]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$605'. created $dff cell `$procdff$749' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den3[2]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$605'. created $dff cell `$procdff$750' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_rem[2]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$605'. created $dff cell `$procdff$751' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_valid[1]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$604'. created $dff cell `$procdff$752' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_sign[1]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$604'. created $dff cell `$procdff$753' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_exp_unbiased[1]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$604'. created $dff cell `$procdff$754' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_zero[1]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$604'. created $dff cell `$procdff$755' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_inf[1]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$604'. created $dff cell `$procdff$756' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_div0[1]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$604'. created $dff cell `$procdff$757' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den[1]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$604'. created $dff cell `$procdff$758' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den3[1]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$604'. created $dff cell `$procdff$759' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_rem[1]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$604'. created $dff cell `$procdff$760' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\round' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:226$598'. created $dff cell `$procdff$761' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\sign' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:226$598'. created $dff cell `$procdff$762' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\force_zero' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:226$598'. created $dff cell `$procdff$763' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\force_inf' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:226$598'. created $dff cell `$procdff$764' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\exp_unbiased' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:226$598'. created $dff cell `$procdff$765' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\significand' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:226$598'. created $dff cell `$procdff$766' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\guard' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:226$598'. created $dff cell `$procdff$767' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\sticky' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:226$598'. created $dff cell `$procdff$768' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\out_valid' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:226$598'. created $dff cell `$procdff$769' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\div0' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:226$598'. created $dff cell `$procdff$770' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\partial_rem' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:226$598'. created $dff cell `$procdff$771' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_raw0' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:125$593'. created $dff cell `$procdff$772' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_valid[0]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:125$593'. created $dff cell `$procdff$773' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_sign[0]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:125$593'. created $dff cell `$procdff$774' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_exp_unbiased[0]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:125$593'. created $dff cell `$procdff$775' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_zero[0]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:125$593'. created $dff cell `$procdff$776' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_force_inf[0]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:125$593'. created $dff cell `$procdff$777' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_div0[0]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:125$593'. created $dff cell `$procdff$778' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den[0]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:125$593'. created $dff cell `$procdff$779' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_den3[0]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:125$593'. created $dff cell `$procdff$780' with positive edge clock. Creating register for signal `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.\r_rem[0]' using process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:125$593'. created $dff cell `$procdff$781' with positive edge clock. Creating register for signal `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000001.\raw_next' using process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000001.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$337'. created $dff cell `$procdff$782' with positive edge clock. Creating register for signal `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000011.\raw_next' using process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000011.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$336'. created $dff cell `$procdff$783' with positive edge clock. 6.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 6.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000101.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$335'. Removing empty process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000111.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$334'. Removing empty process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001001.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$333'. Removing empty process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001011.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$332'. Removing empty process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001101.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$331'. Removing empty process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001111.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$330'. Removing empty process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010001.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$329'. Removing empty process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010011.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$316'. Found and cleaned up 1 empty switch in `\top_zkf_div_w8_m18_base.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_div_w8_m18_base/src/top_zkf_div_w8_m18_base.v:37$90'. Removing empty process `top_zkf_div_w8_m18_base.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_div_w8_m18_base/src/top_zkf_div_w8_m18_base.v:37$90'. Found and cleaned up 1 empty switch in `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$613'. Removing empty process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$613'. Found and cleaned up 1 empty switch in `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$612'. Removing empty process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$612'. Found and cleaned up 1 empty switch in `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$611'. Removing empty process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$611'. Found and cleaned up 1 empty switch in `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$610'. Removing empty process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$610'. Found and cleaned up 1 empty switch in `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$609'. Removing empty process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$609'. Found and cleaned up 1 empty switch in `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$608'. Removing empty process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$608'. Found and cleaned up 1 empty switch in `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$607'. Removing empty process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$607'. Found and cleaned up 1 empty switch in `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$606'. Removing empty process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$606'. Found and cleaned up 1 empty switch in `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$605'. Removing empty process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$605'. Found and cleaned up 1 empty switch in `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$604'. Removing empty process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:168$604'. Found and cleaned up 1 empty switch in `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:226$598'. Removing empty process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:226$598'. Found and cleaned up 1 empty switch in `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:125$593'. Removing empty process `$paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:125$593'. Removing empty process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000001.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$337'. Removing empty process `$paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000011.$proc$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:256$336'. Cleaned up 13 empty switches. 6.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000101. Optimizing module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000111. Optimizing module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001001. Optimizing module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001011. Optimizing module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001101. Optimizing module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001111. Optimizing module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010001. Optimizing module $paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010. Optimizing module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010011. Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core. Optimizing module $paramod$fd955d6c5ad1b45d4ea0b7728598a7e5012c6e65\_zkf_pack. Optimizing module $paramod$b1798e4f7776d4b6f8f2f33461822b434fd6cf47\_zkf_pack_delay. Optimizing module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000001. Optimizing module $paramod$2a41383f0bc6a35d237219c395f573952f3279a3\_zkf_pipe. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Optimizing module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000011. 6.5. Executing CHECK pass (checking for obvious problems). Checking module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000101... Checking module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000111... Checking module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001001... Checking module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001011... Checking module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001101... Checking module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001111... Checking module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010001... Checking module $paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010... Checking module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010011... Checking module top_zkf_div_w8_m18_base... Checking module $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core... Checking module $paramod$fd955d6c5ad1b45d4ea0b7728598a7e5012c6e65\_zkf_pack... Checking module $paramod$b1798e4f7776d4b6f8f2f33461822b434fd6cf47\_zkf_pack_delay... Checking module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000001... Checking module $paramod$2a41383f0bc6a35d237219c395f573952f3279a3\_zkf_pipe... Checking module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div... Checking module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000011... Found and reported 0 problems. 6.6. Executing FLATTEN pass (flatten design). Keeping top_zkf_div_w8_m18_base.u_dut (found keep_hierarchy attribute). Deleting now unused module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000101. Deleting now unused module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000111. Deleting now unused module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001001. Deleting now unused module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001011. Deleting now unused module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001101. Deleting now unused module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000001111. Deleting now unused module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010001. Deleting now unused module $paramod\_zkf_div_radix4_step\WMAN=s32'00000000000000000000000000010010. Deleting now unused module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000010011. Deleting now unused module $paramod$eb9cfa992757aee2d2c098778b3d22c23ee95d9f\_zkf_div_core. Deleting now unused module $paramod$fd955d6c5ad1b45d4ea0b7728598a7e5012c6e65\_zkf_pack. Deleting now unused module $paramod$b1798e4f7776d4b6f8f2f33461822b434fd6cf47\_zkf_pack_delay. Deleting now unused module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000001. Deleting now unused module $paramod$2a41383f0bc6a35d237219c395f573952f3279a3\_zkf_pipe. Deleting now unused module $paramod\_zkf_div_raw_stage\WIN=s32'00000000000000000000000000000011. 6.7. Executing TRIBUF pass. 6.8. Executing DEMINOUT pass (demote inout ports to input or output). 6.9. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.10. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Removed 3 unused cells and 295 unused wires. 6.11. Executing CHECK pass (checking for obvious problems). Checking module top_zkf_div_w8_m18_base... Checking module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div... Found and reported 0 problems. 6.12. Executing OPT pass (performing simple optimizations). 6.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 9 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 324 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 321 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 3 cells. 6.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_div_w8_m18_base.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $flatten\u_core.$ternary$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:238$600: \u_core.g_stage[10].u_raw.raw_next [20:3] -> { 1'1 \u_core.g_stage[10].u_raw.raw_next [19:3] } Analyzing evaluation results. Removed 0 multiplexer ports. 6.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_div_w8_m18_base. Optimizing cells in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Performed a total of 0 changes. 6.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 9 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 321 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.12.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 17 on $flatten\u_core.$procdff$779 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Removed 0 unused cells and 3 unused wires. 6.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.9. Rerunning OPT passes. (Maybe there is more to do..) 6.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_div_w8_m18_base.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 6.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_div_w8_m18_base. Optimizing cells in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Performed a total of 0 changes. 6.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 9 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 321 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.12.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 17 on $flatten\u_core.$procdff$758 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.16. Rerunning OPT passes. (Maybe there is more to do..) 6.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_div_w8_m18_base.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 6.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_div_w8_m18_base. Optimizing cells in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Performed a total of 0 changes. 6.12.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 9 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 321 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.12.20. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 17 on $flatten\u_core.$procdff$749 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.12.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.23. Rerunning OPT passes. (Maybe there is more to do..) 6.12.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_div_w8_m18_base.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 6.12.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_div_w8_m18_base. Optimizing cells in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Performed a total of 0 changes. 6.12.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 9 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 321 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.12.27. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 17 on $flatten\u_core.$procdff$740 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.12.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.30. Rerunning OPT passes. (Maybe there is more to do..) 6.12.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_div_w8_m18_base.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 6.12.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_div_w8_m18_base. Optimizing cells in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Performed a total of 0 changes. 6.12.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 9 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 321 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.12.34. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 17 on $flatten\u_core.$procdff$731 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.12.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.37. Rerunning OPT passes. (Maybe there is more to do..) 6.12.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_div_w8_m18_base.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 6.12.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_div_w8_m18_base. Optimizing cells in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Performed a total of 0 changes. 6.12.40. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 9 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 321 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.12.41. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 17 on $flatten\u_core.$procdff$722 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.42. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.12.43. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.44. Rerunning OPT passes. (Maybe there is more to do..) 6.12.45. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_div_w8_m18_base.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 6.12.46. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_div_w8_m18_base. Optimizing cells in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Performed a total of 0 changes. 6.12.47. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 9 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 321 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.12.48. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 17 on $flatten\u_core.$procdff$713 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.49. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.12.50. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.51. Rerunning OPT passes. (Maybe there is more to do..) 6.12.52. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_div_w8_m18_base.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 6.12.53. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_div_w8_m18_base. Optimizing cells in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Performed a total of 0 changes. 6.12.54. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 9 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 321 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.12.55. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 17 on $flatten\u_core.$procdff$704 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.56. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.12.57. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.58. Rerunning OPT passes. (Maybe there is more to do..) 6.12.59. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_div_w8_m18_base.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 6.12.60. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_div_w8_m18_base. Optimizing cells in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Performed a total of 0 changes. 6.12.61. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 9 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 321 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.12.62. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 17 on $flatten\u_core.$procdff$695 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.63. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.12.64. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.65. Rerunning OPT passes. (Maybe there is more to do..) 6.12.66. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_div_w8_m18_base.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 6.12.67. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_div_w8_m18_base. Optimizing cells in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Performed a total of 0 changes. 6.12.68. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 9 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 321 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.12.69. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 17 on $flatten\u_core.$procdff$686 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.70. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.12.71. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.72. Rerunning OPT passes. (Maybe there is more to do..) 6.12.73. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_div_w8_m18_base.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 6.12.74. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_div_w8_m18_base. Optimizing cells in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Performed a total of 0 changes. 6.12.75. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 9 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 321 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.12.76. Executing OPT_DFF pass (perform DFF optimizations). 6.12.77. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.12.78. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.12.79. Finished fast OPT passes. (There is nothing left to do.) 6.13. Executing FSM pass (extract and optimize FSM). 6.13.1. Executing FSM_DETECT pass (finding FSMs in design). 6.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). 6.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). 6.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). 6.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 6.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 6.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 6.14. Executing OPT pass (performing simple optimizations). 6.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 9 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 321 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_div_w8_m18_base.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 6.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_div_w8_m18_base. Optimizing cells in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Performed a total of 0 changes. 6.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 9 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 321 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.14.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $procdff$667 ($dff) from module top_zkf_div_w8_m18_base (D = \in_valid_i, Q = \in_valid_r, rval = 1'0). Adding SRST signal on $procdff$670 ($dff) from module top_zkf_div_w8_m18_base (D = \dut_valid, Q = \out_valid_r, rval = 1'0). Adding SRST signal on $flatten\u_core.$procdff$773 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div (D = \in_valid, Q = \u_core.r_valid[0], rval = 1'0). Adding SRST signal on $flatten\u_core.$procdff$769 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div (D = \u_core.r_valid[10], Q = \u_core.out_valid, rval = 1'0). Adding SRST signal on $flatten\u_core.$procdff$766 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div (D = \u_core.g_stage[10].u_raw.raw_next [19], Q = \u_core.significand [17], rval = 1'1). Adding SRST signal on $flatten\u_core.$procdff$752 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div (D = \u_core.r_valid[0], Q = \u_core.r_valid[1], rval = 1'0). Adding SRST signal on $flatten\u_core.$procdff$743 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div (D = \u_core.r_valid[1], Q = \u_core.r_valid[2], rval = 1'0). Adding SRST signal on $flatten\u_core.$procdff$734 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div (D = \u_core.r_valid[2], Q = \u_core.r_valid[3], rval = 1'0). Adding SRST signal on $flatten\u_core.$procdff$725 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div (D = \u_core.r_valid[3], Q = \u_core.r_valid[4], rval = 1'0). Adding SRST signal on $flatten\u_core.$procdff$716 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div (D = \u_core.r_valid[4], Q = \u_core.r_valid[5], rval = 1'0). Adding SRST signal on $flatten\u_core.$procdff$707 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div (D = \u_core.r_valid[5], Q = \u_core.r_valid[6], rval = 1'0). Adding SRST signal on $flatten\u_core.$procdff$698 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div (D = \u_core.r_valid[6], Q = \u_core.r_valid[7], rval = 1'0). Adding SRST signal on $flatten\u_core.$procdff$689 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div (D = \u_core.r_valid[7], Q = \u_core.r_valid[8], rval = 1'0). Adding SRST signal on $flatten\u_core.$procdff$680 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div (D = \u_core.r_valid[8], Q = \u_core.r_valid[9], rval = 1'0). Adding SRST signal on $flatten\u_core.$procdff$671 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div (D = \u_core.r_valid[9], Q = \u_core.r_valid[10], rval = 1'0). Adding SRST signal on $flatten\u_core.$procdff$781 ($dff) from module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div (D = $flatten\u_core.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:89$589_Y [17], Q = \u_core.r_rem[0] [17], rval = 1'1). 6.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Removed 14 unused cells and 14 unused wires. 6.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.14.9. Rerunning OPT passes. (Maybe there is more to do..) 6.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_div_w8_m18_base.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 6.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_div_w8_m18_base. Optimizing cells in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Performed a total of 0 changes. 6.14.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 7 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 311 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.14.13. Executing OPT_DFF pass (perform DFF optimizations). 6.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.14.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.14.16. Finished fast OPT passes. (There is nothing left to do.) 6.15. Executing WREDUCE pass (reducing word size of cells). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[10].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 2 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[10].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[10].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[10].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[9].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 2 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[9].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[9].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[9].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[8].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 2 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[8].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[8].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[8].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[7].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 2 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[7].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[7].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[7].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[6].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 2 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[6].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[6].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[6].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[5].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 2 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[5].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[5].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[5].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[4].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 2 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[4].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[4].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[4].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[3].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 2 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[3].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[3].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[3].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[2].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 2 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[2].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[2].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[2].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[1].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 2 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[1].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[1].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[1].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[10].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 3 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[10].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[9].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 3 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[9].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[8].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 3 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[8].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[7].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 3 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[7].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[6].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 3 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[6].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[5].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 3 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[5].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[4].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 3 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[4].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[3].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 3 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[3].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[2].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 3 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[2].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 1 bits (of 21) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[1].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 3 bits (of 21) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.\g_stage[1].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). Removed top 1 bits (of 18) from mux cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.$ternary$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:238$600 ($mux). Removed top 9 bits (of 10) from mux cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.$ternary$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:203$597 ($mux). Removed top 1 bits (of 10) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:97$592 ($sub). Removed top 1 bits (of 10) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:97$592 ($sub). Converting cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:97$592 ($sub) from signed to unsigned. Removed top 1 bits (of 9) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:97$592 ($sub). Removed top 1 bits (of 9) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:97$592 ($sub). Removed top 1 bits (of 10) from port Y of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:97$592 ($sub). Removed top 1 bits (of 20) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:90$591 ($add). Removed top 2 bits (of 20) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:90$591 ($add). Removed top 1 bits (of 18) from mux cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.$ternary$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:89$590 ($mux). Removed top 25 bits (of 26) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:92$521 ($add). Converting cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:69$511 ($add) from unsigned to signed. Removed top 1 bits (of 11) from port A of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:69$511 ($add). Removed top 3 bits (of 11) from port B of cell $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:69$511 ($add). Removed top 1 bits (of 18) from wire $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.$flatten\u_core.$0\significand[17:0]. 6.16. Executing PEEPOPT pass (run peephole optimizers). 6.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Removed 0 unused cells and 1 unused wires. 6.18. Executing SHARE pass (SAT-based resource sharing). 6.19. Executing TECHMAP pass (map to technology primitives). 6.19.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 6.19.2. Continuing TECHMAP pass. No more expansions possible. 6.20. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.22. Executing TECHMAP pass (map to technology primitives). 6.22.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 6.22.2. Continuing TECHMAP pass. No more expansions possible. 6.23. Executing TECHMAP pass (map to technology primitives). 6.23.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. Generating RTLIL representation for module `$__MUL18X18'. Successfully finished Verilog frontend. 6.23.2. Continuing TECHMAP pass. No more expansions possible. 6.24. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top_zkf_div_w8_m18_base: created 0 $alu and 0 $macc cells. Extracting $alu and $macc cells in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div: creating $macc model for $flatten\u_core.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:89$589 ($sub). creating $macc model for $flatten\u_core.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:90$591 ($add). creating $macc model for $flatten\u_core.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:97$592 ($sub). creating $macc model for $flatten\u_core.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:235$599 ($sub). creating $macc model for $flatten\u_core.\g_stage[1].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). creating $macc model for $flatten\u_core.\g_stage[2].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). creating $macc model for $flatten\u_core.\g_stage[3].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). creating $macc model for $flatten\u_core.\g_stage[4].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). creating $macc model for $flatten\u_core.\g_stage[5].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). creating $macc model for $flatten\u_core.\g_stage[6].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). creating $macc model for $flatten\u_core.\g_stage[7].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). creating $macc model for $flatten\u_core.\g_stage[8].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). creating $macc model for $flatten\u_core.\g_stage[9].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). creating $macc model for $flatten\u_core.\g_stage[10].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317 ($sub). creating $macc model for $flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:92$521 ($add). creating $macc model for $flatten\u_core.\g_stage[1].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). creating $macc model for $flatten\u_core.\g_stage[1].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). creating $macc model for $flatten\u_core.\g_stage[2].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). creating $macc model for $flatten\u_core.\g_stage[2].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). creating $macc model for $flatten\u_core.\g_stage[3].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). creating $macc model for $flatten\u_core.\g_stage[3].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). creating $macc model for $flatten\u_core.\g_stage[4].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). creating $macc model for $flatten\u_core.\g_stage[4].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). creating $macc model for $flatten\u_core.\g_stage[5].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). creating $macc model for $flatten\u_core.\g_stage[5].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). creating $macc model for $flatten\u_core.\g_stage[6].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). creating $macc model for $flatten\u_core.\g_stage[6].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). creating $macc model for $flatten\u_core.\g_stage[7].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). creating $macc model for $flatten\u_core.\g_stage[7].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). creating $macc model for $flatten\u_core.\g_stage[8].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). creating $macc model for $flatten\u_core.\g_stage[8].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). creating $macc model for $flatten\u_core.\g_stage[9].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). creating $macc model for $flatten\u_core.\g_stage[9].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). creating $macc model for $flatten\u_core.\g_stage[10].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319 ($sub). creating $macc model for $flatten\u_core.\g_stage[10].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318 ($sub). creating $macc model for $flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:69$511 ($add). creating $alu model for $macc $flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:69$511. creating $alu model for $macc $flatten\u_core.\g_stage[10].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318. creating $alu model for $macc $flatten\u_core.\g_stage[10].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319. creating $alu model for $macc $flatten\u_core.\g_stage[9].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318. creating $alu model for $macc $flatten\u_core.\g_stage[9].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319. creating $alu model for $macc $flatten\u_core.\g_stage[8].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318. creating $alu model for $macc $flatten\u_core.\g_stage[8].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319. creating $alu model for $macc $flatten\u_core.\g_stage[7].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318. creating $alu model for $macc $flatten\u_core.\g_stage[7].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319. creating $alu model for $macc $flatten\u_core.\g_stage[6].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318. creating $alu model for $macc $flatten\u_core.\g_stage[6].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319. creating $alu model for $macc $flatten\u_core.\g_stage[5].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318. creating $alu model for $macc $flatten\u_core.\g_stage[5].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319. creating $alu model for $macc $flatten\u_core.\g_stage[4].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318. creating $alu model for $macc $flatten\u_core.\g_stage[4].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319. creating $alu model for $macc $flatten\u_core.\g_stage[3].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318. creating $alu model for $macc $flatten\u_core.\g_stage[3].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319. creating $alu model for $macc $flatten\u_core.\g_stage[2].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318. creating $alu model for $macc $flatten\u_core.\g_stage[2].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319. creating $alu model for $macc $flatten\u_core.\g_stage[1].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318. creating $alu model for $macc $flatten\u_core.\g_stage[1].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319. creating $alu model for $macc $flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:92$521. creating $alu model for $macc $flatten\u_core.\g_stage[10].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317. creating $alu model for $macc $flatten\u_core.\g_stage[9].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317. creating $alu model for $macc $flatten\u_core.\g_stage[8].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317. creating $alu model for $macc $flatten\u_core.\g_stage[7].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317. creating $alu model for $macc $flatten\u_core.\g_stage[6].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317. creating $alu model for $macc $flatten\u_core.\g_stage[5].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317. creating $alu model for $macc $flatten\u_core.\g_stage[4].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317. creating $alu model for $macc $flatten\u_core.\g_stage[3].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317. creating $alu model for $macc $flatten\u_core.\g_stage[2].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317. creating $alu model for $macc $flatten\u_core.\g_stage[1].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317. creating $alu model for $macc $flatten\u_core.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:235$599. creating $alu model for $macc $flatten\u_core.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:97$592. creating $alu model for $macc $flatten\u_core.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:90$591. creating $alu model for $macc $flatten\u_core.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:89$589. creating $alu model for $flatten\u_core.$ge$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:88$588 ($ge): merged with $flatten\u_core.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:89$589. creating $alu cell for $flatten\u_core.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:89$589, $flatten\u_core.$ge$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:88$588: $auto$alumacc.cc:512:replace_alu$838 creating $alu cell for $flatten\u_core.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:90$591: $auto$alumacc.cc:512:replace_alu$851 creating $alu cell for $flatten\u_core.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:97$592: $auto$alumacc.cc:512:replace_alu$854 creating $alu cell for $flatten\u_core.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:235$599: $auto$alumacc.cc:512:replace_alu$857 creating $alu cell for $flatten\u_core.\g_stage[1].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317: $auto$alumacc.cc:512:replace_alu$860 creating $alu cell for $flatten\u_core.\g_stage[2].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317: $auto$alumacc.cc:512:replace_alu$863 creating $alu cell for $flatten\u_core.\g_stage[3].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317: $auto$alumacc.cc:512:replace_alu$866 creating $alu cell for $flatten\u_core.\g_stage[4].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317: $auto$alumacc.cc:512:replace_alu$869 creating $alu cell for $flatten\u_core.\g_stage[5].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317: $auto$alumacc.cc:512:replace_alu$872 creating $alu cell for $flatten\u_core.\g_stage[6].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317: $auto$alumacc.cc:512:replace_alu$875 creating $alu cell for $flatten\u_core.\g_stage[7].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317: $auto$alumacc.cc:512:replace_alu$878 creating $alu cell for $flatten\u_core.\g_stage[8].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317: $auto$alumacc.cc:512:replace_alu$881 creating $alu cell for $flatten\u_core.\g_stage[9].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317: $auto$alumacc.cc:512:replace_alu$884 creating $alu cell for $flatten\u_core.\g_stage[10].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:285$317: $auto$alumacc.cc:512:replace_alu$887 creating $alu cell for $flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:92$521: $auto$alumacc.cc:512:replace_alu$890 creating $alu cell for $flatten\u_core.\g_stage[1].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319: $auto$alumacc.cc:512:replace_alu$893 creating $alu cell for $flatten\u_core.\g_stage[1].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318: $auto$alumacc.cc:512:replace_alu$896 creating $alu cell for $flatten\u_core.\g_stage[2].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319: $auto$alumacc.cc:512:replace_alu$899 creating $alu cell for $flatten\u_core.\g_stage[2].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318: $auto$alumacc.cc:512:replace_alu$902 creating $alu cell for $flatten\u_core.\g_stage[3].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319: $auto$alumacc.cc:512:replace_alu$905 creating $alu cell for $flatten\u_core.\g_stage[3].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318: $auto$alumacc.cc:512:replace_alu$908 creating $alu cell for $flatten\u_core.\g_stage[4].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319: $auto$alumacc.cc:512:replace_alu$911 creating $alu cell for $flatten\u_core.\g_stage[4].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318: $auto$alumacc.cc:512:replace_alu$914 creating $alu cell for $flatten\u_core.\g_stage[5].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319: $auto$alumacc.cc:512:replace_alu$917 creating $alu cell for $flatten\u_core.\g_stage[5].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318: $auto$alumacc.cc:512:replace_alu$920 creating $alu cell for $flatten\u_core.\g_stage[6].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319: $auto$alumacc.cc:512:replace_alu$923 creating $alu cell for $flatten\u_core.\g_stage[6].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318: $auto$alumacc.cc:512:replace_alu$926 creating $alu cell for $flatten\u_core.\g_stage[7].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319: $auto$alumacc.cc:512:replace_alu$929 creating $alu cell for $flatten\u_core.\g_stage[7].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318: $auto$alumacc.cc:512:replace_alu$932 creating $alu cell for $flatten\u_core.\g_stage[8].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319: $auto$alumacc.cc:512:replace_alu$935 creating $alu cell for $flatten\u_core.\g_stage[8].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318: $auto$alumacc.cc:512:replace_alu$938 creating $alu cell for $flatten\u_core.\g_stage[9].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319: $auto$alumacc.cc:512:replace_alu$941 creating $alu cell for $flatten\u_core.\g_stage[9].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318: $auto$alumacc.cc:512:replace_alu$944 creating $alu cell for $flatten\u_core.\g_stage[10].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:287$319: $auto$alumacc.cc:512:replace_alu$947 creating $alu cell for $flatten\u_core.\g_stage[10].u_step.$sub$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_div_core.v:286$318: $auto$alumacc.cc:512:replace_alu$950 creating $alu cell for $flatten\u_pack.$add$/mnt/storage/zubax/kulibin2/float/hdl/_zkf_pack.v:69$511: $auto$alumacc.cc:512:replace_alu$953 created 36 $alu and 0 $macc cells. 6.25. Executing OPT pass (performing simple optimizations). 6.25.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.25.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 7 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 315 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_div_w8_m18_base.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 6.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_div_w8_m18_base. Optimizing cells in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Performed a total of 0 changes. 6.25.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 7 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 315 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.25.6. Executing OPT_DFF pass (perform DFF optimizations). 6.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Removed 0 unused cells and 1 unused wires. 6.25.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.25.9. Rerunning OPT passes. (Maybe there is more to do..) 6.25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_div_w8_m18_base.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 6.25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_div_w8_m18_base. Optimizing cells in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Performed a total of 0 changes. 6.25.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 7 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 315 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.25.13. Executing OPT_DFF pass (perform DFF optimizations). 6.25.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.25.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.25.16. Finished fast OPT passes. (There is nothing left to do.) 6.26. Executing MEMORY pass. 6.26.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 6.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 6.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 6.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 6.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 6.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 6.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 6.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). 6.27. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). 6.29. Executing TECHMAP pass (map to technology primitives). 6.29.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 6.29.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v' to AST representation. Generating RTLIL representation for module `$__DP16KD_'. Generating RTLIL representation for module `$__PDPW16KD_'. Successfully finished Verilog frontend. 6.29.3. Continuing TECHMAP pass. No more expansions possible. 6.30. Executing OPT pass (performing simple optimizations). 6.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 7 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 315 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.30.3. Executing OPT_DFF pass (perform DFF optimizations). 6.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Removed 0 unused cells and 10 unused wires. 6.30.5. Finished fast OPT passes. 6.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 6.32. Executing OPT pass (performing simple optimizations). 6.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 7 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 315 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_zkf_div_w8_m18_base.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 6.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_zkf_div_w8_m18_base. Optimizing cells in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Performed a total of 0 changes. 6.32.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 7 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 315 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 0 cells. 6.32.6. Executing OPT_DFF pass (perform DFF optimizations). 6.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. 6.32.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.32.9. Finished fast OPT passes. (There is nothing left to do.) 6.33. Executing TECHMAP pass (map to technology primitives). 6.33.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 6.33.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. Generating RTLIL representation for module `\_80_ccu2c_alu'. Successfully finished Verilog frontend. 6.33.3. Continuing TECHMAP pass. Using template $paramod$8105d46316cb99041c6dc3f486b2ad084df41ba8\_80_ccu2c_alu for cells of type $alu. Using template $paramod$3f130b1307126b2ad59695abd14050e58a80d0ee\_80_ccu2c_alu for cells of type $alu. Using template $paramod$a7926d38756e33b5022e02ebfd484599309272c7\_80_ccu2c_alu for cells of type $alu. Using template $paramod$a8151eed7df109f18d5adf1169b40bb7b9e884a8\_80_ccu2c_alu for cells of type $alu. Using template $paramod$9162d2e9231026f804a2f624da34d1efec0cc524\_80_ccu2c_alu for cells of type $alu. Using template $paramod$3d4d857737ce5ee764ebe220e87ff73b66d6d0ad\_80_ccu2c_alu for cells of type $alu. Using template $paramod$4ccbe221165818e15f326ddee3d1183c7924e12f\_80_ccu2c_alu for cells of type $alu. Using template $paramod$997095b0d0841f90940aeb655a2c287938600ca1\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $reduce_and. Using template $paramod$12350b8c8422a70d10b7db4eaae1202a7148b784\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $logic_or. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $pos. No more expansions possible. 6.34. Executing OPT pass (performing simple optimizations). 6.34.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.34.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 82 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 4410 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 4192 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 4189 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 4186 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 4183 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 4180 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 4177 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 4174 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 4171 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 4168 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 4165 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 4163 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 4162 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 248 cells. 6.34.3. Executing OPT_DFF pass (perform DFF optimizations). 6.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Removed 2067 unused cells and 2245 unused wires. 6.34.5. Finished fast OPT passes. 6.35. Executing ABC pass (technology mapping using ABC). 6.35.1. Summary of detected clock domains: 3 cells in clk=\clk, en={ }, arst={ }, srst=\rst 79 cells in clk=\clk, en={ }, arst={ }, srst={ } 6.35.2. Extracting gate netlist of module `\top_zkf_div_w8_m18_base' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by \rst 6.35.3. Extracting gate netlist of module `\top_zkf_div_w8_m18_base' to `/input.blif'.. Found matching posedge clock domain: \clk 6.35.3.1. Executed ABC. Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 2 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 6.35.3.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 4 ABC RESULTS: DFF cells: 2 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 2 ABC RESULTS: output signals: 2 Removing temp directory. 6.35.3.1. Executed ABC. Extracted 79 gates and 158 wires to a netlist network with 79 inputs and 79 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 79 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 6.35.3.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 158 ABC RESULTS: DFF cells: 79 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 79 ABC RESULTS: output signals: 79 Removing temp directory. 6.35.4. Summary of detected clock domains: 24 cells in clk={ }, en={ }, arst={ }, srst={ } 3 cells in clk=\clk, en={ }, arst={ }, srst=\u_core.g_stage[10].u_raw.raw_next [20] 14 cells in clk=\clk, en={ }, arst={ }, srst=\rst 3 cells in clk=\clk, en={ }, arst={ }, srst=!\u_core.initial_bit 2051 cells in clk=\clk, en={ }, arst={ }, srst={ } 6.35.5. Extracting gate netlist of module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 6.35.6. Extracting gate netlist of module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by \u_core.g_stage[10].u_raw.raw_next [20] 6.35.7. Extracting gate netlist of module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by \rst 6.35.8. Extracting gate netlist of module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !\u_core.initial_bit 6.35.9. Extracting gate netlist of module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div' to `/input.blif'.. Found matching posedge clock domain: \clk 6.35.9.1. Executed ABC. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 6.35.9.1. Executed ABC. Extracted 2 gates and 5 wires to a netlist network with 3 inputs and 2 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 6.35.9.2. Re-integrating ABC results. ABC RESULTS: AND cells: 1 ABC RESULTS: DFF cells: 1 ABC RESULTS: NOT cells: 2 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 3 ABC RESULTS: output signals: 2 Removing temp directory. 6.35.9.1. Executed ABC. Extracted 14 gates and 16 wires to a netlist network with 2 inputs and 1 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 6.35.9.2. Re-integrating ABC results. ABC RESULTS: ANDNOT cells: 1 ABC RESULTS: BUF cells: 12 ABC RESULTS: DFF cells: 12 ABC RESULTS: internal signals: 13 ABC RESULTS: input signals: 2 ABC RESULTS: output signals: 1 Removing temp directory. 6.35.9.1. Executed ABC. Extracted 1 gates and 2 wires to a netlist network with 1 inputs and 1 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 6.35.9.2. Re-integrating ABC results. ABC RESULTS: DFF cells: 1 ABC RESULTS: NOT cells: 2 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 1 ABC RESULTS: output signals: 1 Removing temp directory. 6.35.9.1. Executed ABC. Extracted 1686 gates and 2391 wires to a netlist network with 703 inputs and 607 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 855 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 6.35.9.2. Re-integrating ABC results. ABC RESULTS: AND cells: 123 ABC RESULTS: ANDNOT cells: 10 ABC RESULTS: BUF cells: 1209 ABC RESULTS: DFF cells: 854 ABC RESULTS: MUX cells: 469 ABC RESULTS: NAND cells: 130 ABC RESULTS: NOR cells: 20 ABC RESULTS: NOT cells: 16 ABC RESULTS: OR cells: 32 ABC RESULTS: ORNOT cells: 67 ABC RESULTS: XNOR cells: 8 ABC RESULTS: internal signals: 1081 ABC RESULTS: input signals: 703 ABC RESULTS: output signals: 607 Removing temp directory. Removing global temp directory. 6.36. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Removed 0 unused cells and 3155 unused wires. 6.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 6.38. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_zkf_div_w8_m18_base'. Computing hashes of 82 cells of `\top_zkf_div_w8_m18_base'. Finding duplicate cells in `\top_zkf_div_w8_m18_base'. Finding identical cells in module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 2142 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Computing hashes of 2141 cells of `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Finding duplicate cells in `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div'. Removed a total of 1 cells. 6.39. Executing TECHMAP pass (map to technology primitives). 6.39.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 6.39.2. Continuing TECHMAP pass. Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. No more expansions possible. 6.40. Executing OPT_EXPR pass (perform const folding). Optimizing module top_zkf_div_w8_m18_base. Optimizing module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). 6.42. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in top_zkf_div_w8_m18_base. Handling GSR in $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. 6.43. Executing ATTRMVCP pass (move or copy attributes). 6.44. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_zkf_div_w8_m18_base.. Finding unused cells or wires in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div.. Removed 0 unused cells and 3813 unused wires. 6.45. Executing ABC pass (technology mapping using ABC). 6.45.1. Extracting gate netlist of module `\top_zkf_div_w8_m18_base' to `/input.blif'.. 6.45.1.1. Executed ABC. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 6.45.2. Extracting gate netlist of module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div' to `/input.blif'.. 6.45.2.1. Executed ABC. Extracted 881 gates and 1743 wires to a netlist network with 862 inputs and 257 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 6.45.2.2. Re-integrating ABC results. ABC RESULTS: AND cells: 125 ABC RESULTS: ANDNOT cells: 14 ABC RESULTS: MUX cells: 456 ABC RESULTS: NAND cells: 109 ABC RESULTS: NOR cells: 46 ABC RESULTS: NOT cells: 23 ABC RESULTS: OR cells: 12 ABC RESULTS: ORNOT cells: 62 ABC RESULTS: XNOR cells: 5 ABC RESULTS: internal signals: 624 ABC RESULTS: input signals: 862 ABC RESULTS: output signals: 257 Removing temp directory. Removing global temp directory. 6.46. Executing TECHMAP pass (map to technology primitives). 6.46.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v' to AST representation. Generating RTLIL representation for module `$_DLATCH_N_'. Generating RTLIL representation for module `$_DLATCH_P_'. Successfully finished Verilog frontend. 6.46.2. Continuing TECHMAP pass. No more expansions possible. 6.47. Executing ABC pass (technology mapping using ABC). 6.47.1. Summary of detected clock domains: 82 cells in clk={ }, en={ }, arst={ }, srst={ } 6.47.2. Extracting gate netlist of module `\top_zkf_div_w8_m18_base' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 6.47.2.1. Executed ABC. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 6.47.3. Summary of detected clock domains: 2112 cells in clk={ }, en={ }, arst={ }, srst={ } 6.47.4. Extracting gate netlist of module `$paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 6.47.4.1. Executed ABC. Extracted 852 gates and 1714 wires to a netlist network with 862 inputs and 257 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_lut /lutdefs.txt ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + dress /input.blif ABC: Total number of equiv classes = 431. ABC: Participating nodes from both networks = 863. ABC: Participating nodes from the first network = 431. ( 91.51 % of nodes) ABC: Participating nodes from the second network = 432. ( 91.72 % of nodes) ABC: Node pairs (any polarity) = 431. ( 91.51 % of names can be moved) ABC: Node pairs (same polarity) = 289. ( 61.36 % of names can be moved) ABC: Total runtime = 0.08 sec ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 6.47.4.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 470 ABC RESULTS: internal signals: 595 ABC RESULTS: input signals: 862 ABC RESULTS: output signals: 257 Removing temp directory. Removing global temp directory. Removed 0 unused cells and 3457 unused wires. 6.48. Executing TECHMAP pass (map to technology primitives). 6.48.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `$lut'. Successfully finished Verilog frontend. 6.48.2. Continuing TECHMAP pass. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. Using template $paramod$f44e1eab45e047e709d5dfed32527eb1f7745488$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut. Using template $paramod$2b2b3565ec13859d2b24f2fa297fa46249270140$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod$09194da5f2c8e08bed8f609fd0e254d8629b24b3$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f$lut for cells of type $lut. Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. Using template $paramod$a4df2b5be2b644499880e088a11556935f22b401$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$4e115fda7df2e35206b57277c1e9b791162b6f83$lut for cells of type $lut. Using template $paramod$56d36648044d0bf0f892c2050a60c21ad090a3b1$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut. Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1$lut for cells of type $lut. Using template $paramod$68ddec0fa51e887f01749f7dbab50dc0a13f0f42$lut for cells of type $lut. Using template $paramod$eb453e5c4284f97a8ffea70cb552841f9d2d6223$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110100 for cells of type $lut. Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8$lut for cells of type $lut. Using template $paramod$c24ed72ebb67e9ead6029e42e909ef7fc0abbb11$lut for cells of type $lut. Using template $paramod$83a094b6fe9fb738dfff353a8cb39fb4b34c4f40$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut. Using template $paramod$acf24144bd04b2510ba144e14b69922c6aff2b7e$lut for cells of type $lut. Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14$lut for cells of type $lut. Using template $paramod$b4d0f4738a5ce50c7f36c2aa2ecc09cfb874f2b6$lut for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut. Using template $paramod$16773ebb5e5d8dbce266b8a86bb4af4574d61ffd$lut for cells of type $lut. Using template $paramod$575b200168b9e109c2ed99df4359056f2c6696ac$lut for cells of type $lut. Using template $paramod$b75e8306635d621cb7e96e5d2ad1327ab1afa025$lut for cells of type $lut. Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912$lut for cells of type $lut. Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c$lut for cells of type $lut. Using template $paramod$56bf14dbc639ee1088c927767cae18d43a852b63$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. No more expansions possible. 6.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in top_zkf_div_w8_m18_base. Optimizing LUTs in $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div. Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12399.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12467.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12614.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12250.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12255.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12257.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12257.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12259.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12269.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12275.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12277.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12277.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12279.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12281.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12283.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12285.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12287.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12294.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12297.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12300.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12314.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12318.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12325.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12328.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12331.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12342.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12344.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12346.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12348.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12350.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12352.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12354.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12356.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12362.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12364.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12366.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12370.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12374.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12376.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12376.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12378.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12390.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12394.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12396.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12402.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12405.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12408.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12411.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12422.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12424.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12424.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12428.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12430.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12432.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12436.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12440.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12440.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12444.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12446.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12448.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12452.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12454.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12456.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12460.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12464.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12467.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12471.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12473.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12479.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12481.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12481.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12483.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12483.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12485.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12485.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12487.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12491.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12493.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12495.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12497.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12499.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12501.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12503.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12505.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12509.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12509.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12511.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12511.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12513.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12515.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12515.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12517.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12519.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12523.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12523.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12525.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12533.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12535.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12537.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12539.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12541.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12541.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12543.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12543.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12545.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12547.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12549.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12551.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12553.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12555.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12557.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12559.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12561.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12561.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12563.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12570.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12572.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12576.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12578.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12580.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12584.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12592.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12592.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12595.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12597.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12601.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12604.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12611.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12613.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12207$auto$blifparse.cc:557:parse_blif$12663.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Removed 0 unused cells and 1009 unused wires. 6.50. Executing AUTONAME pass. Renamed 81 objects in module top_zkf_div_w8_m18_base (5 iterations). Renamed 3110 objects in module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div (299 iterations). 6.51. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `top_zkf_div_w8_m18_base'. Setting top module to top_zkf_div_w8_m18_base. 6.51.1. Analyzing design hierarchy.. Top module: \top_zkf_div_w8_m18_base Used module: $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div 6.51.2. Analyzing design hierarchy.. Top module: \top_zkf_div_w8_m18_base Used module: $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div Removed 0 unused modules. 6.52. Printing statistics. === top_zkf_div_w8_m18_base === +----------Local Count, excluding submodules. | 17 wires 192 wire bits 17 public wires 192 public wire bits 8 ports 83 port bits 82 submodules 1 $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div 81 TRELLIS_FF === $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div === +----------Local Count, excluding submodules. | 1297 wires 6896 wire bits 1297 public wires 6896 public wire bits 8 ports 83 port bits 24 cells 24 $scopeinfo 2030 submodules 368 CCU2C 2 L6MUX21 632 LUT4 160 PFUMX 868 TRELLIS_FF === design hierarchy === +----------Count including submodules. | 24 top_zkf_div_w8_m18_base 24 $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div +----------Count including submodules. | 1314 wires 7088 wire bits 1314 public wires 7088 public wire bits 16 ports 166 port bits - memories - memory bits - processes 24 cells 24 $scopeinfo 82 submodules 1 $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div 81 TRELLIS_FF 6.53. Executing CHECK pass (checking for obvious problems). Checking module top_zkf_div_w8_m18_base... Checking module $paramod$2c0294452123a482caae4bbee0f8b6e4018be1b8\zkf_div... Found and reported 0 problems. 6.54. Executing JSON backend. Warnings: 9 unique messages, 36 total End of script. Logfile hash: b65699d5a1, time: 8.98s, user: 3.43s, system: 0.11s, MEM: 54.23 MB peak Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3) Time spent: 27% 3x abc (1 sec), 15% 1x autoname (0 sec), ... $ yosys -s /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/zkf_div_w8_m18_base/yosys.ys [exit code 0]