/----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3) -- Executing script file `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/flopoco_mul_we8_wf35_zynq7000_native_f500/yosys.ys' -- 1. Executing GHDL. Importing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Importing module flopoco_mul_we8_wf35_zynq7000_native_f500_Barch. Importing module intmultiplier_36x36_72_freq500_uid5_Barch. Importing module intadder_45_freq500_uid392_Barch. Importing module dspblock_24x17_freq500_uid10_Barch. Importing module dspblock_24x17_freq500_uid12_Barch. Importing module intkaratsuba_16x24_order_0_freq500_uid14_Barch. Importing module intmultiplierlut_3x2_freq500_uid18_Barch. Importing module intmultiplierlut_3x2_freq500_uid23_Barch. Importing module intmultiplierlut_3x2_freq500_uid28_Barch. Importing module intmultiplierlut_3x2_freq500_uid33_Barch. Importing module intmultiplierlut_3x2_freq500_uid38_Barch. Importing module intmultiplierlut_3x3_freq500_uid43_Barch. Importing module intmultiplierlut_3x2_freq500_uid48_Barch. Importing module intmultiplierlut_3x3_freq500_uid53_Barch. Importing module intmultiplierlut_3x3_freq500_uid58_Barch. Importing module intmultiplierlut_3x2_freq500_uid63_Barch. Importing module intmultiplierlut_3x3_freq500_uid68_Barch. Importing module intmultiplierlut_3x3_freq500_uid73_Barch. Importing module intmultiplierlut_3x3_freq500_uid78_Barch. Importing module intmultiplierlut_3x2_freq500_uid83_Barch. Importing module intmultiplierlut_3x3_freq500_uid88_Barch. Importing module intmultiplierlut_3x3_freq500_uid93_Barch. Importing module intmultiplierlut_3x3_freq500_uid98_Barch. Importing module intmultiplierlut_3x3_freq500_uid103_Barch. Importing module intmultiplierlut_3x3_freq500_uid108_Barch. Importing module intmultiplierlut_3x3_freq500_uid113_Barch. Importing module intmultiplierlut_3x3_freq500_uid118_Barch. Importing module intmultiplierlut_3x3_freq500_uid123_Barch. Importing module intmultiplierlut_3x3_freq500_uid128_Barch. Importing module intmultiplierlut_3x3_freq500_uid133_Barch. Importing module compressor_23_3_freq500_uid139_Barch. Importing module compressor_3_2_freq500_uid157_Barch. Importing module compressor_14_3_freq500_uid189_Barch. Importing module compressor_6_3_freq500_uid195_Barch. Importing module intadder_64_freq500_uid389_Barch. Importing module dspblock_25x18_freq500_uid16_Barch. Importing module multtable_freq500_uid20_Barch. Importing module multtable_freq500_uid25_Barch. Importing module multtable_freq500_uid30_Barch. Importing module multtable_freq500_uid35_Barch. Importing module multtable_freq500_uid40_Barch. Importing module multtable_freq500_uid45_Barch. Importing module multtable_freq500_uid50_Barch. Importing module multtable_freq500_uid55_Barch. Importing module multtable_freq500_uid60_Barch. Importing module multtable_freq500_uid65_Barch. Importing module multtable_freq500_uid70_Barch. Importing module multtable_freq500_uid75_Barch. Importing module multtable_freq500_uid80_Barch. Importing module multtable_freq500_uid85_Barch. Importing module multtable_freq500_uid90_Barch. Importing module multtable_freq500_uid95_Barch. Importing module multtable_freq500_uid100_Barch. Importing module multtable_freq500_uid105_Barch. Importing module multtable_freq500_uid110_Barch. Importing module multtable_freq500_uid115_Barch. Importing module multtable_freq500_uid120_Barch. Importing module multtable_freq500_uid125_Barch. Importing module multtable_freq500_uid130_Barch. Importing module multtable_freq500_uid135_Barch. 2. Executing SYNTH_LATTICE pass. 2.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\VLO'. Generating RTLIL representation for module `\VHI'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\DP16KD'. Replacing existing blackbox module `\FD1P3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:2.1-2.261. Generating RTLIL representation for module `\FD1P3AX'. Replacing existing blackbox module `\FD1P3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:3.1-3.261. Generating RTLIL representation for module `\FD1P3AY'. Replacing existing blackbox module `\FD1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:4.1-4.261. Generating RTLIL representation for module `\FD1P3BX'. Replacing existing blackbox module `\FD1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:5.1-5.261. Generating RTLIL representation for module `\FD1P3DX'. Replacing existing blackbox module `\FD1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:6.1-6.261. Generating RTLIL representation for module `\FD1P3IX'. Replacing existing blackbox module `\FD1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:7.1-7.261. Generating RTLIL representation for module `\FD1P3JX'. Replacing existing blackbox module `\FD1S3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:8.1-8.261. Generating RTLIL representation for module `\FD1S3AX'. Replacing existing blackbox module `\FD1S3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:9.1-9.261. Generating RTLIL representation for module `\FD1S3AY'. Replacing existing blackbox module `\FD1S3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:10.1-10.261. Generating RTLIL representation for module `\FD1S3BX'. Replacing existing blackbox module `\FD1S3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:11.1-11.261. Generating RTLIL representation for module `\FD1S3DX'. Replacing existing blackbox module `\FD1S3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:12.1-12.261. Generating RTLIL representation for module `\FD1S3IX'. Replacing existing blackbox module `\FD1S3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:13.1-13.261. Generating RTLIL representation for module `\FD1S3JX'. Replacing existing blackbox module `\IFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:26.1-26.301. Generating RTLIL representation for module `\IFS1P3BX'. Replacing existing blackbox module `\IFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:27.1-27.301. Generating RTLIL representation for module `\IFS1P3DX'. Replacing existing blackbox module `\IFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:28.1-28.301. Generating RTLIL representation for module `\IFS1P3IX'. Replacing existing blackbox module `\IFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:29.1-29.301. Generating RTLIL representation for module `\IFS1P3JX'. Replacing existing blackbox module `\OFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:31.1-31.302. Generating RTLIL representation for module `\OFS1P3BX'. Replacing existing blackbox module `\OFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:32.1-32.302. Generating RTLIL representation for module `\OFS1P3DX'. Replacing existing blackbox module `\OFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:33.1-33.302. Generating RTLIL representation for module `\OFS1P3IX'. Replacing existing blackbox module `\OFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:34.1-34.302. Generating RTLIL representation for module `\OFS1P3JX'. Replacing existing blackbox module `\IB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:2.1-2.157. Generating RTLIL representation for module `\IB'. Replacing existing blackbox module `\IBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:3.1-3.157. Generating RTLIL representation for module `\IBPU'. Replacing existing blackbox module `\IBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:4.1-4.157. Generating RTLIL representation for module `\IBPD'. Replacing existing blackbox module `\OB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:5.1-5.157. Generating RTLIL representation for module `\OB'. Replacing existing blackbox module `\OBZ' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:6.1-6.164. Generating RTLIL representation for module `\OBZ'. Replacing existing blackbox module `\OBZPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:7.1-7.164. Generating RTLIL representation for module `\OBZPU'. Replacing existing blackbox module `\OBZPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:8.1-8.164. Generating RTLIL representation for module `\OBZPD'. Replacing existing blackbox module `\OBCO' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:9.1-9.90. Generating RTLIL representation for module `\OBCO'. Replacing existing blackbox module `\BB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:10.1-10.179. Generating RTLIL representation for module `\BB'. Replacing existing blackbox module `\BBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:11.1-11.179. Generating RTLIL representation for module `\BBPU'. Replacing existing blackbox module `\BBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:12.1-12.179. Generating RTLIL representation for module `\BBPD'. Replacing existing blackbox module `\ILVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:13.1-13.139. Generating RTLIL representation for module `\ILVDS'. Replacing existing blackbox module `\OLVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:14.1-14.146. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 2.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DCUA'. Successfully finished Verilog frontend. 2.3. Executing HIERARCHY pass (managing design hierarchy). 2.3.1. Analyzing design hierarchy.. Top module: \top_flopoco_mul_we8_wf35_zynq7000_native_f500 Used module: \flopoco_mul_we8_wf35_zynq7000_native_f500_Barch Used module: \intadder_45_freq500_uid392_Barch Used module: \intmultiplier_36x36_72_freq500_uid5_Barch Used module: \intadder_64_freq500_uid389_Barch Used module: \compressor_14_3_freq500_uid189_Barch Used module: \compressor_23_3_freq500_uid139_Barch Used module: \compressor_3_2_freq500_uid157_Barch Used module: \compressor_6_3_freq500_uid195_Barch Used module: \intmultiplierlut_3x3_freq500_uid133_Barch Used module: \multtable_freq500_uid135_Barch Used module: \intmultiplierlut_3x3_freq500_uid128_Barch Used module: \multtable_freq500_uid130_Barch Used module: \intmultiplierlut_3x3_freq500_uid123_Barch Used module: \multtable_freq500_uid125_Barch Used module: \intmultiplierlut_3x3_freq500_uid118_Barch Used module: \multtable_freq500_uid120_Barch Used module: \intmultiplierlut_3x3_freq500_uid113_Barch Used module: \multtable_freq500_uid115_Barch Used module: \intmultiplierlut_3x3_freq500_uid108_Barch Used module: \multtable_freq500_uid110_Barch Used module: \intmultiplierlut_3x3_freq500_uid103_Barch Used module: \multtable_freq500_uid105_Barch Used module: \intmultiplierlut_3x3_freq500_uid98_Barch Used module: \multtable_freq500_uid100_Barch Used module: \intmultiplierlut_3x3_freq500_uid93_Barch Used module: \multtable_freq500_uid95_Barch Used module: \intmultiplierlut_3x3_freq500_uid88_Barch Used module: \multtable_freq500_uid90_Barch Used module: \intmultiplierlut_3x2_freq500_uid83_Barch Used module: \multtable_freq500_uid85_Barch Used module: \intmultiplierlut_3x3_freq500_uid78_Barch Used module: \multtable_freq500_uid80_Barch Used module: \intmultiplierlut_3x3_freq500_uid73_Barch Used module: \multtable_freq500_uid75_Barch Used module: \intmultiplierlut_3x3_freq500_uid68_Barch Used module: \multtable_freq500_uid70_Barch Used module: \intmultiplierlut_3x2_freq500_uid63_Barch Used module: \multtable_freq500_uid65_Barch Used module: \intmultiplierlut_3x3_freq500_uid58_Barch Used module: \multtable_freq500_uid60_Barch Used module: \intmultiplierlut_3x3_freq500_uid53_Barch Used module: \multtable_freq500_uid55_Barch Used module: \intmultiplierlut_3x2_freq500_uid48_Barch Used module: \multtable_freq500_uid50_Barch Used module: \intmultiplierlut_3x3_freq500_uid43_Barch Used module: \multtable_freq500_uid45_Barch Used module: \intmultiplierlut_3x2_freq500_uid38_Barch Used module: \multtable_freq500_uid40_Barch Used module: \intmultiplierlut_3x2_freq500_uid33_Barch Used module: \multtable_freq500_uid35_Barch Used module: \intmultiplierlut_3x2_freq500_uid28_Barch Used module: \multtable_freq500_uid30_Barch Used module: \intmultiplierlut_3x2_freq500_uid23_Barch Used module: \multtable_freq500_uid25_Barch Used module: \intmultiplierlut_3x2_freq500_uid18_Barch Used module: \multtable_freq500_uid20_Barch Used module: \intkaratsuba_16x24_order_0_freq500_uid14_Barch Used module: \dspblock_25x18_freq500_uid16_Barch Used module: \dspblock_24x17_freq500_uid12_Barch Used module: \dspblock_24x17_freq500_uid10_Barch 2.3.2. Analyzing design hierarchy.. Top module: \top_flopoco_mul_we8_wf35_zynq7000_native_f500 Used module: \flopoco_mul_we8_wf35_zynq7000_native_f500_Barch Used module: \intadder_45_freq500_uid392_Barch Used module: \intmultiplier_36x36_72_freq500_uid5_Barch Used module: \intadder_64_freq500_uid389_Barch Used module: \compressor_14_3_freq500_uid189_Barch Used module: \compressor_23_3_freq500_uid139_Barch Used module: \compressor_3_2_freq500_uid157_Barch Used module: \compressor_6_3_freq500_uid195_Barch Used module: \intmultiplierlut_3x3_freq500_uid133_Barch Used module: \multtable_freq500_uid135_Barch Used module: \intmultiplierlut_3x3_freq500_uid128_Barch Used module: \multtable_freq500_uid130_Barch Used module: \intmultiplierlut_3x3_freq500_uid123_Barch Used module: \multtable_freq500_uid125_Barch Used module: \intmultiplierlut_3x3_freq500_uid118_Barch Used module: \multtable_freq500_uid120_Barch Used module: \intmultiplierlut_3x3_freq500_uid113_Barch Used module: \multtable_freq500_uid115_Barch Used module: \intmultiplierlut_3x3_freq500_uid108_Barch Used module: \multtable_freq500_uid110_Barch Used module: \intmultiplierlut_3x3_freq500_uid103_Barch Used module: \multtable_freq500_uid105_Barch Used module: \intmultiplierlut_3x3_freq500_uid98_Barch Used module: \multtable_freq500_uid100_Barch Used module: \intmultiplierlut_3x3_freq500_uid93_Barch Used module: \multtable_freq500_uid95_Barch Used module: \intmultiplierlut_3x3_freq500_uid88_Barch Used module: \multtable_freq500_uid90_Barch Used module: \intmultiplierlut_3x2_freq500_uid83_Barch Used module: \multtable_freq500_uid85_Barch Used module: \intmultiplierlut_3x3_freq500_uid78_Barch Used module: \multtable_freq500_uid80_Barch Used module: \intmultiplierlut_3x3_freq500_uid73_Barch Used module: \multtable_freq500_uid75_Barch Used module: \intmultiplierlut_3x3_freq500_uid68_Barch Used module: \multtable_freq500_uid70_Barch Used module: \intmultiplierlut_3x2_freq500_uid63_Barch Used module: \multtable_freq500_uid65_Barch Used module: \intmultiplierlut_3x3_freq500_uid58_Barch Used module: \multtable_freq500_uid60_Barch Used module: \intmultiplierlut_3x3_freq500_uid53_Barch Used module: \multtable_freq500_uid55_Barch Used module: \intmultiplierlut_3x2_freq500_uid48_Barch Used module: \multtable_freq500_uid50_Barch Used module: \intmultiplierlut_3x3_freq500_uid43_Barch Used module: \multtable_freq500_uid45_Barch Used module: \intmultiplierlut_3x2_freq500_uid38_Barch Used module: \multtable_freq500_uid40_Barch Used module: \intmultiplierlut_3x2_freq500_uid33_Barch Used module: \multtable_freq500_uid35_Barch Used module: \intmultiplierlut_3x2_freq500_uid28_Barch Used module: \multtable_freq500_uid30_Barch Used module: \intmultiplierlut_3x2_freq500_uid23_Barch Used module: \multtable_freq500_uid25_Barch Used module: \intmultiplierlut_3x2_freq500_uid18_Barch Used module: \multtable_freq500_uid20_Barch Used module: \intkaratsuba_16x24_order_0_freq500_uid14_Barch Used module: \dspblock_25x18_freq500_uid16_Barch Used module: \dspblock_24x17_freq500_uid12_Barch Used module: \dspblock_24x17_freq500_uid10_Barch Removed 0 unused modules. 2.4. Executing PROC pass (convert processes to netlists). 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4.4. Executing PROC_INIT pass (extract init attributes). 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module multtable_freq500_uid135_Barch. Optimizing module multtable_freq500_uid130_Barch. Optimizing module multtable_freq500_uid125_Barch. Optimizing module multtable_freq500_uid120_Barch. Optimizing module multtable_freq500_uid115_Barch. Optimizing module multtable_freq500_uid110_Barch. Optimizing module multtable_freq500_uid105_Barch. Optimizing module multtable_freq500_uid100_Barch. Optimizing module multtable_freq500_uid95_Barch. Optimizing module multtable_freq500_uid90_Barch. Optimizing module multtable_freq500_uid85_Barch. Optimizing module multtable_freq500_uid80_Barch. Optimizing module multtable_freq500_uid75_Barch. Optimizing module multtable_freq500_uid70_Barch. Optimizing module multtable_freq500_uid65_Barch. Optimizing module multtable_freq500_uid60_Barch. Optimizing module multtable_freq500_uid55_Barch. Optimizing module multtable_freq500_uid50_Barch. Optimizing module multtable_freq500_uid45_Barch. Optimizing module multtable_freq500_uid40_Barch. Optimizing module multtable_freq500_uid35_Barch. Optimizing module multtable_freq500_uid30_Barch. Optimizing module multtable_freq500_uid25_Barch. Optimizing module multtable_freq500_uid20_Barch. Optimizing module dspblock_25x18_freq500_uid16_Barch. Optimizing module intadder_64_freq500_uid389_Barch. Optimizing module compressor_6_3_freq500_uid195_Barch. Optimizing module compressor_14_3_freq500_uid189_Barch. Optimizing module compressor_3_2_freq500_uid157_Barch. Optimizing module compressor_23_3_freq500_uid139_Barch. Optimizing module intmultiplierlut_3x3_freq500_uid133_Barch. Optimizing module intmultiplierlut_3x3_freq500_uid128_Barch. Optimizing module intmultiplierlut_3x3_freq500_uid123_Barch. Optimizing module intmultiplierlut_3x3_freq500_uid118_Barch. Optimizing module intmultiplierlut_3x3_freq500_uid113_Barch. Optimizing module intmultiplierlut_3x3_freq500_uid108_Barch. Optimizing module intmultiplierlut_3x3_freq500_uid103_Barch. Optimizing module intmultiplierlut_3x3_freq500_uid98_Barch. Optimizing module intmultiplierlut_3x3_freq500_uid93_Barch. Optimizing module intmultiplierlut_3x3_freq500_uid88_Barch. Optimizing module intmultiplierlut_3x2_freq500_uid83_Barch. Optimizing module intmultiplierlut_3x3_freq500_uid78_Barch. Optimizing module intmultiplierlut_3x3_freq500_uid73_Barch. Optimizing module intmultiplierlut_3x3_freq500_uid68_Barch. Optimizing module intmultiplierlut_3x2_freq500_uid63_Barch. Optimizing module intmultiplierlut_3x3_freq500_uid58_Barch. Optimizing module intmultiplierlut_3x3_freq500_uid53_Barch. Optimizing module intmultiplierlut_3x2_freq500_uid48_Barch. Optimizing module intmultiplierlut_3x3_freq500_uid43_Barch. Optimizing module intmultiplierlut_3x2_freq500_uid38_Barch. Optimizing module intmultiplierlut_3x2_freq500_uid33_Barch. Optimizing module intmultiplierlut_3x2_freq500_uid28_Barch. Optimizing module intmultiplierlut_3x2_freq500_uid23_Barch. Optimizing module intmultiplierlut_3x2_freq500_uid18_Barch. Optimizing module intkaratsuba_16x24_order_0_freq500_uid14_Barch. Optimizing module dspblock_24x17_freq500_uid12_Barch. Optimizing module dspblock_24x17_freq500_uid10_Barch. Optimizing module intadder_45_freq500_uid392_Barch. Optimizing module intmultiplier_36x36_72_freq500_uid5_Barch. Optimizing module flopoco_mul_we8_wf35_zynq7000_native_f500_Barch. Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.5. Executing CHECK pass (checking for obvious problems). Checking module multtable_freq500_uid135_Barch... Checking module multtable_freq500_uid130_Barch... Checking module multtable_freq500_uid125_Barch... Checking module multtable_freq500_uid120_Barch... Checking module multtable_freq500_uid115_Barch... Checking module multtable_freq500_uid110_Barch... Checking module multtable_freq500_uid105_Barch... Checking module multtable_freq500_uid100_Barch... Checking module multtable_freq500_uid95_Barch... Checking module multtable_freq500_uid90_Barch... Checking module multtable_freq500_uid85_Barch... Checking module multtable_freq500_uid80_Barch... Checking module multtable_freq500_uid75_Barch... Checking module multtable_freq500_uid70_Barch... Checking module multtable_freq500_uid65_Barch... Checking module multtable_freq500_uid60_Barch... Checking module multtable_freq500_uid55_Barch... Checking module multtable_freq500_uid50_Barch... Checking module multtable_freq500_uid45_Barch... Checking module multtable_freq500_uid40_Barch... Checking module multtable_freq500_uid35_Barch... Checking module multtable_freq500_uid30_Barch... Checking module multtable_freq500_uid25_Barch... Checking module multtable_freq500_uid20_Barch... Checking module dspblock_25x18_freq500_uid16_Barch... Checking module intadder_64_freq500_uid389_Barch... Checking module compressor_6_3_freq500_uid195_Barch... Checking module compressor_14_3_freq500_uid189_Barch... Checking module compressor_3_2_freq500_uid157_Barch... Checking module compressor_23_3_freq500_uid139_Barch... Checking module intmultiplierlut_3x3_freq500_uid133_Barch... Checking module intmultiplierlut_3x3_freq500_uid128_Barch... Checking module intmultiplierlut_3x3_freq500_uid123_Barch... Checking module intmultiplierlut_3x3_freq500_uid118_Barch... Checking module intmultiplierlut_3x3_freq500_uid113_Barch... Checking module intmultiplierlut_3x3_freq500_uid108_Barch... Checking module intmultiplierlut_3x3_freq500_uid103_Barch... Checking module intmultiplierlut_3x3_freq500_uid98_Barch... Checking module intmultiplierlut_3x3_freq500_uid93_Barch... Checking module intmultiplierlut_3x3_freq500_uid88_Barch... Checking module intmultiplierlut_3x2_freq500_uid83_Barch... Checking module intmultiplierlut_3x3_freq500_uid78_Barch... Checking module intmultiplierlut_3x3_freq500_uid73_Barch... Checking module intmultiplierlut_3x3_freq500_uid68_Barch... Checking module intmultiplierlut_3x2_freq500_uid63_Barch... Checking module intmultiplierlut_3x3_freq500_uid58_Barch... Checking module intmultiplierlut_3x3_freq500_uid53_Barch... Checking module intmultiplierlut_3x2_freq500_uid48_Barch... Checking module intmultiplierlut_3x3_freq500_uid43_Barch... Checking module intmultiplierlut_3x2_freq500_uid38_Barch... Checking module intmultiplierlut_3x2_freq500_uid33_Barch... Checking module intmultiplierlut_3x2_freq500_uid28_Barch... Checking module intmultiplierlut_3x2_freq500_uid23_Barch... Checking module intmultiplierlut_3x2_freq500_uid18_Barch... Checking module intkaratsuba_16x24_order_0_freq500_uid14_Barch... Checking module dspblock_24x17_freq500_uid12_Barch... Checking module dspblock_24x17_freq500_uid10_Barch... Checking module intadder_45_freq500_uid392_Barch... Checking module intmultiplier_36x36_72_freq500_uid5_Barch... Checking module flopoco_mul_we8_wf35_zynq7000_native_f500_Barch... Checking module top_flopoco_mul_we8_wf35_zynq7000_native_f500... Found and reported 0 problems. 2.6. Executing FLATTEN pass (flatten design). Deleting now unused module multtable_freq500_uid135_Barch. Deleting now unused module multtable_freq500_uid130_Barch. Deleting now unused module multtable_freq500_uid125_Barch. Deleting now unused module multtable_freq500_uid120_Barch. Deleting now unused module multtable_freq500_uid115_Barch. Deleting now unused module multtable_freq500_uid110_Barch. Deleting now unused module multtable_freq500_uid105_Barch. Deleting now unused module multtable_freq500_uid100_Barch. Deleting now unused module multtable_freq500_uid95_Barch. Deleting now unused module multtable_freq500_uid90_Barch. Deleting now unused module multtable_freq500_uid85_Barch. Deleting now unused module multtable_freq500_uid80_Barch. Deleting now unused module multtable_freq500_uid75_Barch. Deleting now unused module multtable_freq500_uid70_Barch. Deleting now unused module multtable_freq500_uid65_Barch. Deleting now unused module multtable_freq500_uid60_Barch. Deleting now unused module multtable_freq500_uid55_Barch. Deleting now unused module multtable_freq500_uid50_Barch. Deleting now unused module multtable_freq500_uid45_Barch. Deleting now unused module multtable_freq500_uid40_Barch. Deleting now unused module multtable_freq500_uid35_Barch. Deleting now unused module multtable_freq500_uid30_Barch. Deleting now unused module multtable_freq500_uid25_Barch. Deleting now unused module multtable_freq500_uid20_Barch. Deleting now unused module dspblock_25x18_freq500_uid16_Barch. Deleting now unused module intadder_64_freq500_uid389_Barch. Deleting now unused module compressor_6_3_freq500_uid195_Barch. Deleting now unused module compressor_14_3_freq500_uid189_Barch. Deleting now unused module compressor_3_2_freq500_uid157_Barch. Deleting now unused module compressor_23_3_freq500_uid139_Barch. Deleting now unused module intmultiplierlut_3x3_freq500_uid133_Barch. Deleting now unused module intmultiplierlut_3x3_freq500_uid128_Barch. Deleting now unused module intmultiplierlut_3x3_freq500_uid123_Barch. Deleting now unused module intmultiplierlut_3x3_freq500_uid118_Barch. Deleting now unused module intmultiplierlut_3x3_freq500_uid113_Barch. Deleting now unused module intmultiplierlut_3x3_freq500_uid108_Barch. Deleting now unused module intmultiplierlut_3x3_freq500_uid103_Barch. Deleting now unused module intmultiplierlut_3x3_freq500_uid98_Barch. Deleting now unused module intmultiplierlut_3x3_freq500_uid93_Barch. Deleting now unused module intmultiplierlut_3x3_freq500_uid88_Barch. Deleting now unused module intmultiplierlut_3x2_freq500_uid83_Barch. Deleting now unused module intmultiplierlut_3x3_freq500_uid78_Barch. Deleting now unused module intmultiplierlut_3x3_freq500_uid73_Barch. Deleting now unused module intmultiplierlut_3x3_freq500_uid68_Barch. Deleting now unused module intmultiplierlut_3x2_freq500_uid63_Barch. Deleting now unused module intmultiplierlut_3x3_freq500_uid58_Barch. Deleting now unused module intmultiplierlut_3x3_freq500_uid53_Barch. Deleting now unused module intmultiplierlut_3x2_freq500_uid48_Barch. Deleting now unused module intmultiplierlut_3x3_freq500_uid43_Barch. Deleting now unused module intmultiplierlut_3x2_freq500_uid38_Barch. Deleting now unused module intmultiplierlut_3x2_freq500_uid33_Barch. Deleting now unused module intmultiplierlut_3x2_freq500_uid28_Barch. Deleting now unused module intmultiplierlut_3x2_freq500_uid23_Barch. Deleting now unused module intmultiplierlut_3x2_freq500_uid18_Barch. Deleting now unused module intkaratsuba_16x24_order_0_freq500_uid14_Barch. Deleting now unused module dspblock_24x17_freq500_uid12_Barch. Deleting now unused module dspblock_24x17_freq500_uid10_Barch. Deleting now unused module intadder_45_freq500_uid392_Barch. Deleting now unused module intmultiplier_36x36_72_freq500_uid5_Barch. Deleting now unused module flopoco_mul_we8_wf35_zynq7000_native_f500_Barch. 2.7. Executing TRIBUF pass. 2.8. Executing DEMINOUT pass (demote inout ports to input or output). 2.9. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.10. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Removed 0 unused cells and 597 unused wires. 2.11. Executing CHECK pass (checking for obvious problems). Checking module top_flopoco_mul_we8_wf35_zynq7000_native_f500... Found and reported 0 problems. 2.12. Executing OPT pass (performing simple optimizations). 2.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6686 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6683 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6680 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6677 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6674 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6671 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6668 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6665 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6662 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6659 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6657 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6656 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 30 cells. 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid274.:2749. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid358.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid358.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid330.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid330.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid272.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid272.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid360.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid360.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid328.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid328.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid270.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid270.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid362.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid362.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid268.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid268.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid326.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid326.:2878. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid266.:2749. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid364.:2749. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid264.:2749. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid262.:2749. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid366.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid366.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid324.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid324.:2878. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid260.:2749. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid258.:2749. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid368.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid368.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid322.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid322.:2878. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid256.:2749. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid350.:2749. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid238.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid238.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid370.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid370.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid320.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid320.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid234.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid234.:2878. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid338.:2749. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid352.:2749. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid372.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid372.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid334.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid334.:2878. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid340.:2749. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid374.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid374.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid318.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid318.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid204.:3074. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid204.:3074. dead port 7/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid200.:2749. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid200.:2749. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid354.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid354.:2878. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid316.:2749. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid336.:2749. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid376.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid376.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid378.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid378.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid198.:3074. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid198.:3074. dead port 4/5 on $pmux \u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid312.:2777. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid380.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid380.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid196.:3074. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid182.:2749. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid382.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid382.:2878. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid180.:2749. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid178.:2749. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid308.:2749. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid332.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid332.:2878. dead port 4/5 on $pmux \u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid158.:2777. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid154.:2749. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid386.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid386.:2878. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid356.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid356.:2878. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid306.:2749. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid152.:2749. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid150.:2749. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid148.:2749. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid146.:2749. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid144.:2749. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid142.:2749. dead port 8/9 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid140.:2749. dead port 2/33 on $pmux \u_dut.significandmultiplication.t8_tile_3.tablemult.:3381. dead port 3/33 on $pmux \u_dut.significandmultiplication.t8_tile_3.tablemult.:3381. dead port 4/33 on $pmux \u_dut.significandmultiplication.t8_tile_3.tablemult.:3381. dead port 9/33 on $pmux \u_dut.significandmultiplication.t8_tile_3.tablemult.:3381. dead port 10/33 on $pmux \u_dut.significandmultiplication.t8_tile_3.tablemult.:3381. dead port 11/33 on $pmux \u_dut.significandmultiplication.t8_tile_3.tablemult.:3381. dead port 12/33 on $pmux \u_dut.significandmultiplication.t8_tile_3.tablemult.:3381. dead port 17/33 on $pmux \u_dut.significandmultiplication.t8_tile_3.tablemult.:3381. dead port 18/33 on $pmux \u_dut.significandmultiplication.t8_tile_3.tablemult.:3381. dead port 19/33 on $pmux \u_dut.significandmultiplication.t8_tile_3.tablemult.:3381. dead port 20/33 on $pmux \u_dut.significandmultiplication.t8_tile_3.tablemult.:3381. dead port 25/33 on $pmux \u_dut.significandmultiplication.t8_tile_3.tablemult.:3381. dead port 26/33 on $pmux \u_dut.significandmultiplication.t8_tile_3.tablemult.:3381. dead port 27/33 on $pmux \u_dut.significandmultiplication.t8_tile_3.tablemult.:3381. dead port 28/33 on $pmux \u_dut.significandmultiplication.t8_tile_3.tablemult.:3381. dead port 6/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid384.:2878. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid384.:2878. Removed 111 multiplexer ports. 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. New ctrl vector for $pmux cell \u_dut.:156: $flatten\u_dut.$auto$ghdl.cc:862:import_module$40 New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_26.tablemult.:7217: { $auto$opt_reduce.cc:135:opt_pmux$2484 $flatten\u_dut.\significandmultiplication.\t8_tile_26.\tablemult.$auto$ghdl.cc:862:import_module$1987 $auto$opt_reduce.cc:135:opt_pmux$2482 $auto$opt_reduce.cc:135:opt_pmux$2480 $auto$opt_reduce.cc:135:opt_pmux$2478 $auto$opt_reduce.cc:135:opt_pmux$2476 $auto$opt_reduce.cc:135:opt_pmux$2474 $auto$opt_reduce.cc:135:opt_pmux$2472 $auto$opt_reduce.cc:135:opt_pmux$2470 $auto$opt_reduce.cc:135:opt_pmux$2468 $auto$opt_reduce.cc:135:opt_pmux$2466 $auto$opt_reduce.cc:135:opt_pmux$2464 $flatten\u_dut.\significandmultiplication.\t8_tile_26.\tablemult.$auto$ghdl.cc:862:import_module$2005 $auto$opt_reduce.cc:135:opt_pmux$2462 $auto$opt_reduce.cc:135:opt_pmux$2460 $auto$opt_reduce.cc:135:opt_pmux$2458 $flatten\u_dut.\significandmultiplication.\t8_tile_26.\tablemult.$auto$ghdl.cc:862:import_module$2014 $auto$opt_reduce.cc:135:opt_pmux$2456 $auto$opt_reduce.cc:135:opt_pmux$2454 $auto$opt_reduce.cc:135:opt_pmux$2452 $flatten\u_dut.\significandmultiplication.\t8_tile_26.\tablemult.$auto$ghdl.cc:862:import_module$2023 $auto$opt_reduce.cc:135:opt_pmux$2450 $auto$opt_reduce.cc:135:opt_pmux$2448 $flatten\u_dut.\significandmultiplication.\t8_tile_26.\tablemult.$auto$ghdl.cc:862:import_module$2032 $auto$opt_reduce.cc:135:opt_pmux$2446 $flatten\u_dut.\significandmultiplication.\t8_tile_26.\tablemult.$auto$ghdl.cc:862:import_module$2041 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_25.tablemult.:7021: { $auto$opt_reduce.cc:135:opt_pmux$2524 $flatten\u_dut.\significandmultiplication.\t8_tile_25.\tablemult.$auto$ghdl.cc:862:import_module$1922 $auto$opt_reduce.cc:135:opt_pmux$2522 $auto$opt_reduce.cc:135:opt_pmux$2520 $auto$opt_reduce.cc:135:opt_pmux$2518 $auto$opt_reduce.cc:135:opt_pmux$2516 $auto$opt_reduce.cc:135:opt_pmux$2514 $auto$opt_reduce.cc:135:opt_pmux$2512 $auto$opt_reduce.cc:135:opt_pmux$2510 $auto$opt_reduce.cc:135:opt_pmux$2508 $auto$opt_reduce.cc:135:opt_pmux$2506 $auto$opt_reduce.cc:135:opt_pmux$2504 $flatten\u_dut.\significandmultiplication.\t8_tile_25.\tablemult.$auto$ghdl.cc:862:import_module$1940 $auto$opt_reduce.cc:135:opt_pmux$2502 $auto$opt_reduce.cc:135:opt_pmux$2500 $auto$opt_reduce.cc:135:opt_pmux$2498 $flatten\u_dut.\significandmultiplication.\t8_tile_25.\tablemult.$auto$ghdl.cc:862:import_module$1949 $auto$opt_reduce.cc:135:opt_pmux$2496 $auto$opt_reduce.cc:135:opt_pmux$2494 $auto$opt_reduce.cc:135:opt_pmux$2492 $flatten\u_dut.\significandmultiplication.\t8_tile_25.\tablemult.$auto$ghdl.cc:862:import_module$1958 $auto$opt_reduce.cc:135:opt_pmux$2490 $auto$opt_reduce.cc:135:opt_pmux$2488 $flatten\u_dut.\significandmultiplication.\t8_tile_25.\tablemult.$auto$ghdl.cc:862:import_module$1967 $auto$opt_reduce.cc:135:opt_pmux$2486 $flatten\u_dut.\significandmultiplication.\t8_tile_25.\tablemult.$auto$ghdl.cc:862:import_module$1976 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_24.tablemult.:6825: { $auto$opt_reduce.cc:135:opt_pmux$2564 $flatten\u_dut.\significandmultiplication.\t8_tile_24.\tablemult.$auto$ghdl.cc:862:import_module$1857 $auto$opt_reduce.cc:135:opt_pmux$2562 $auto$opt_reduce.cc:135:opt_pmux$2560 $auto$opt_reduce.cc:135:opt_pmux$2558 $auto$opt_reduce.cc:135:opt_pmux$2556 $auto$opt_reduce.cc:135:opt_pmux$2554 $auto$opt_reduce.cc:135:opt_pmux$2552 $auto$opt_reduce.cc:135:opt_pmux$2550 $auto$opt_reduce.cc:135:opt_pmux$2548 $auto$opt_reduce.cc:135:opt_pmux$2546 $auto$opt_reduce.cc:135:opt_pmux$2544 $flatten\u_dut.\significandmultiplication.\t8_tile_24.\tablemult.$auto$ghdl.cc:862:import_module$1875 $auto$opt_reduce.cc:135:opt_pmux$2542 $auto$opt_reduce.cc:135:opt_pmux$2540 $auto$opt_reduce.cc:135:opt_pmux$2538 $flatten\u_dut.\significandmultiplication.\t8_tile_24.\tablemult.$auto$ghdl.cc:862:import_module$1884 $auto$opt_reduce.cc:135:opt_pmux$2536 $auto$opt_reduce.cc:135:opt_pmux$2534 $auto$opt_reduce.cc:135:opt_pmux$2532 $flatten\u_dut.\significandmultiplication.\t8_tile_24.\tablemult.$auto$ghdl.cc:862:import_module$1893 $auto$opt_reduce.cc:135:opt_pmux$2530 $auto$opt_reduce.cc:135:opt_pmux$2528 $flatten\u_dut.\significandmultiplication.\t8_tile_24.\tablemult.$auto$ghdl.cc:862:import_module$1902 $auto$opt_reduce.cc:135:opt_pmux$2526 $flatten\u_dut.\significandmultiplication.\t8_tile_24.\tablemult.$auto$ghdl.cc:862:import_module$1911 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_23.tablemult.:6629: { $auto$opt_reduce.cc:135:opt_pmux$2604 $flatten\u_dut.\significandmultiplication.\t8_tile_23.\tablemult.$auto$ghdl.cc:862:import_module$1792 $auto$opt_reduce.cc:135:opt_pmux$2602 $auto$opt_reduce.cc:135:opt_pmux$2600 $auto$opt_reduce.cc:135:opt_pmux$2598 $auto$opt_reduce.cc:135:opt_pmux$2596 $auto$opt_reduce.cc:135:opt_pmux$2594 $auto$opt_reduce.cc:135:opt_pmux$2592 $auto$opt_reduce.cc:135:opt_pmux$2590 $auto$opt_reduce.cc:135:opt_pmux$2588 $auto$opt_reduce.cc:135:opt_pmux$2586 $auto$opt_reduce.cc:135:opt_pmux$2584 $flatten\u_dut.\significandmultiplication.\t8_tile_23.\tablemult.$auto$ghdl.cc:862:import_module$1810 $auto$opt_reduce.cc:135:opt_pmux$2582 $auto$opt_reduce.cc:135:opt_pmux$2580 $auto$opt_reduce.cc:135:opt_pmux$2578 $flatten\u_dut.\significandmultiplication.\t8_tile_23.\tablemult.$auto$ghdl.cc:862:import_module$1819 $auto$opt_reduce.cc:135:opt_pmux$2576 $auto$opt_reduce.cc:135:opt_pmux$2574 $auto$opt_reduce.cc:135:opt_pmux$2572 $flatten\u_dut.\significandmultiplication.\t8_tile_23.\tablemult.$auto$ghdl.cc:862:import_module$1828 $auto$opt_reduce.cc:135:opt_pmux$2570 $auto$opt_reduce.cc:135:opt_pmux$2568 $flatten\u_dut.\significandmultiplication.\t8_tile_23.\tablemult.$auto$ghdl.cc:862:import_module$1837 $auto$opt_reduce.cc:135:opt_pmux$2566 $flatten\u_dut.\significandmultiplication.\t8_tile_23.\tablemult.$auto$ghdl.cc:862:import_module$1846 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_22.tablemult.:6433: { $auto$opt_reduce.cc:135:opt_pmux$2644 $flatten\u_dut.\significandmultiplication.\t8_tile_22.\tablemult.$auto$ghdl.cc:862:import_module$1727 $auto$opt_reduce.cc:135:opt_pmux$2642 $auto$opt_reduce.cc:135:opt_pmux$2640 $auto$opt_reduce.cc:135:opt_pmux$2638 $auto$opt_reduce.cc:135:opt_pmux$2636 $auto$opt_reduce.cc:135:opt_pmux$2634 $auto$opt_reduce.cc:135:opt_pmux$2632 $auto$opt_reduce.cc:135:opt_pmux$2630 $auto$opt_reduce.cc:135:opt_pmux$2628 $auto$opt_reduce.cc:135:opt_pmux$2626 $auto$opt_reduce.cc:135:opt_pmux$2624 $flatten\u_dut.\significandmultiplication.\t8_tile_22.\tablemult.$auto$ghdl.cc:862:import_module$1745 $auto$opt_reduce.cc:135:opt_pmux$2622 $auto$opt_reduce.cc:135:opt_pmux$2620 $auto$opt_reduce.cc:135:opt_pmux$2618 $flatten\u_dut.\significandmultiplication.\t8_tile_22.\tablemult.$auto$ghdl.cc:862:import_module$1754 $auto$opt_reduce.cc:135:opt_pmux$2616 $auto$opt_reduce.cc:135:opt_pmux$2614 $auto$opt_reduce.cc:135:opt_pmux$2612 $flatten\u_dut.\significandmultiplication.\t8_tile_22.\tablemult.$auto$ghdl.cc:862:import_module$1763 $auto$opt_reduce.cc:135:opt_pmux$2610 $auto$opt_reduce.cc:135:opt_pmux$2608 $flatten\u_dut.\significandmultiplication.\t8_tile_22.\tablemult.$auto$ghdl.cc:862:import_module$1772 $auto$opt_reduce.cc:135:opt_pmux$2606 $flatten\u_dut.\significandmultiplication.\t8_tile_22.\tablemult.$auto$ghdl.cc:862:import_module$1781 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_21.tablemult.:6237: { $auto$opt_reduce.cc:135:opt_pmux$2684 $flatten\u_dut.\significandmultiplication.\t8_tile_21.\tablemult.$auto$ghdl.cc:862:import_module$1662 $auto$opt_reduce.cc:135:opt_pmux$2682 $auto$opt_reduce.cc:135:opt_pmux$2680 $auto$opt_reduce.cc:135:opt_pmux$2678 $auto$opt_reduce.cc:135:opt_pmux$2676 $auto$opt_reduce.cc:135:opt_pmux$2674 $auto$opt_reduce.cc:135:opt_pmux$2672 $auto$opt_reduce.cc:135:opt_pmux$2670 $auto$opt_reduce.cc:135:opt_pmux$2668 $auto$opt_reduce.cc:135:opt_pmux$2666 $auto$opt_reduce.cc:135:opt_pmux$2664 $flatten\u_dut.\significandmultiplication.\t8_tile_21.\tablemult.$auto$ghdl.cc:862:import_module$1680 $auto$opt_reduce.cc:135:opt_pmux$2662 $auto$opt_reduce.cc:135:opt_pmux$2660 $auto$opt_reduce.cc:135:opt_pmux$2658 $flatten\u_dut.\significandmultiplication.\t8_tile_21.\tablemult.$auto$ghdl.cc:862:import_module$1689 $auto$opt_reduce.cc:135:opt_pmux$2656 $auto$opt_reduce.cc:135:opt_pmux$2654 $auto$opt_reduce.cc:135:opt_pmux$2652 $flatten\u_dut.\significandmultiplication.\t8_tile_21.\tablemult.$auto$ghdl.cc:862:import_module$1698 $auto$opt_reduce.cc:135:opt_pmux$2650 $auto$opt_reduce.cc:135:opt_pmux$2648 $flatten\u_dut.\significandmultiplication.\t8_tile_21.\tablemult.$auto$ghdl.cc:862:import_module$1707 $auto$opt_reduce.cc:135:opt_pmux$2646 $flatten\u_dut.\significandmultiplication.\t8_tile_21.\tablemult.$auto$ghdl.cc:862:import_module$1716 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_20.tablemult.:6041: { $auto$opt_reduce.cc:135:opt_pmux$2724 $flatten\u_dut.\significandmultiplication.\t8_tile_20.\tablemult.$auto$ghdl.cc:862:import_module$1597 $auto$opt_reduce.cc:135:opt_pmux$2722 $auto$opt_reduce.cc:135:opt_pmux$2720 $auto$opt_reduce.cc:135:opt_pmux$2718 $auto$opt_reduce.cc:135:opt_pmux$2716 $auto$opt_reduce.cc:135:opt_pmux$2714 $auto$opt_reduce.cc:135:opt_pmux$2712 $auto$opt_reduce.cc:135:opt_pmux$2710 $auto$opt_reduce.cc:135:opt_pmux$2708 $auto$opt_reduce.cc:135:opt_pmux$2706 $auto$opt_reduce.cc:135:opt_pmux$2704 $flatten\u_dut.\significandmultiplication.\t8_tile_20.\tablemult.$auto$ghdl.cc:862:import_module$1615 $auto$opt_reduce.cc:135:opt_pmux$2702 $auto$opt_reduce.cc:135:opt_pmux$2700 $auto$opt_reduce.cc:135:opt_pmux$2698 $flatten\u_dut.\significandmultiplication.\t8_tile_20.\tablemult.$auto$ghdl.cc:862:import_module$1624 $auto$opt_reduce.cc:135:opt_pmux$2696 $auto$opt_reduce.cc:135:opt_pmux$2694 $auto$opt_reduce.cc:135:opt_pmux$2692 $flatten\u_dut.\significandmultiplication.\t8_tile_20.\tablemult.$auto$ghdl.cc:862:import_module$1633 $auto$opt_reduce.cc:135:opt_pmux$2690 $auto$opt_reduce.cc:135:opt_pmux$2688 $flatten\u_dut.\significandmultiplication.\t8_tile_20.\tablemult.$auto$ghdl.cc:862:import_module$1642 $auto$opt_reduce.cc:135:opt_pmux$2686 $flatten\u_dut.\significandmultiplication.\t8_tile_20.\tablemult.$auto$ghdl.cc:862:import_module$1651 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_19.tablemult.:5845: { $auto$opt_reduce.cc:135:opt_pmux$2764 $flatten\u_dut.\significandmultiplication.\t8_tile_19.\tablemult.$auto$ghdl.cc:862:import_module$1532 $auto$opt_reduce.cc:135:opt_pmux$2762 $auto$opt_reduce.cc:135:opt_pmux$2760 $auto$opt_reduce.cc:135:opt_pmux$2758 $auto$opt_reduce.cc:135:opt_pmux$2756 $auto$opt_reduce.cc:135:opt_pmux$2754 $auto$opt_reduce.cc:135:opt_pmux$2752 $auto$opt_reduce.cc:135:opt_pmux$2750 $auto$opt_reduce.cc:135:opt_pmux$2748 $auto$opt_reduce.cc:135:opt_pmux$2746 $auto$opt_reduce.cc:135:opt_pmux$2744 $flatten\u_dut.\significandmultiplication.\t8_tile_19.\tablemult.$auto$ghdl.cc:862:import_module$1550 $auto$opt_reduce.cc:135:opt_pmux$2742 $auto$opt_reduce.cc:135:opt_pmux$2740 $auto$opt_reduce.cc:135:opt_pmux$2738 $flatten\u_dut.\significandmultiplication.\t8_tile_19.\tablemult.$auto$ghdl.cc:862:import_module$1559 $auto$opt_reduce.cc:135:opt_pmux$2736 $auto$opt_reduce.cc:135:opt_pmux$2734 $auto$opt_reduce.cc:135:opt_pmux$2732 $flatten\u_dut.\significandmultiplication.\t8_tile_19.\tablemult.$auto$ghdl.cc:862:import_module$1568 $auto$opt_reduce.cc:135:opt_pmux$2730 $auto$opt_reduce.cc:135:opt_pmux$2728 $flatten\u_dut.\significandmultiplication.\t8_tile_19.\tablemult.$auto$ghdl.cc:862:import_module$1577 $auto$opt_reduce.cc:135:opt_pmux$2726 $flatten\u_dut.\significandmultiplication.\t8_tile_19.\tablemult.$auto$ghdl.cc:862:import_module$1586 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_18.tablemult.:5649: { $auto$opt_reduce.cc:135:opt_pmux$2804 $flatten\u_dut.\significandmultiplication.\t8_tile_18.\tablemult.$auto$ghdl.cc:862:import_module$1467 $auto$opt_reduce.cc:135:opt_pmux$2802 $auto$opt_reduce.cc:135:opt_pmux$2800 $auto$opt_reduce.cc:135:opt_pmux$2798 $auto$opt_reduce.cc:135:opt_pmux$2796 $auto$opt_reduce.cc:135:opt_pmux$2794 $auto$opt_reduce.cc:135:opt_pmux$2792 $auto$opt_reduce.cc:135:opt_pmux$2790 $auto$opt_reduce.cc:135:opt_pmux$2788 $auto$opt_reduce.cc:135:opt_pmux$2786 $auto$opt_reduce.cc:135:opt_pmux$2784 $flatten\u_dut.\significandmultiplication.\t8_tile_18.\tablemult.$auto$ghdl.cc:862:import_module$1485 $auto$opt_reduce.cc:135:opt_pmux$2782 $auto$opt_reduce.cc:135:opt_pmux$2780 $auto$opt_reduce.cc:135:opt_pmux$2778 $flatten\u_dut.\significandmultiplication.\t8_tile_18.\tablemult.$auto$ghdl.cc:862:import_module$1494 $auto$opt_reduce.cc:135:opt_pmux$2776 $auto$opt_reduce.cc:135:opt_pmux$2774 $auto$opt_reduce.cc:135:opt_pmux$2772 $flatten\u_dut.\significandmultiplication.\t8_tile_18.\tablemult.$auto$ghdl.cc:862:import_module$1503 $auto$opt_reduce.cc:135:opt_pmux$2770 $auto$opt_reduce.cc:135:opt_pmux$2768 $flatten\u_dut.\significandmultiplication.\t8_tile_18.\tablemult.$auto$ghdl.cc:862:import_module$1512 $auto$opt_reduce.cc:135:opt_pmux$2766 $flatten\u_dut.\significandmultiplication.\t8_tile_18.\tablemult.$auto$ghdl.cc:862:import_module$1521 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_17.tablemult.:5453: { $auto$opt_reduce.cc:135:opt_pmux$2844 $flatten\u_dut.\significandmultiplication.\t8_tile_17.\tablemult.$auto$ghdl.cc:862:import_module$1402 $auto$opt_reduce.cc:135:opt_pmux$2842 $auto$opt_reduce.cc:135:opt_pmux$2840 $auto$opt_reduce.cc:135:opt_pmux$2838 $auto$opt_reduce.cc:135:opt_pmux$2836 $auto$opt_reduce.cc:135:opt_pmux$2834 $auto$opt_reduce.cc:135:opt_pmux$2832 $auto$opt_reduce.cc:135:opt_pmux$2830 $auto$opt_reduce.cc:135:opt_pmux$2828 $auto$opt_reduce.cc:135:opt_pmux$2826 $auto$opt_reduce.cc:135:opt_pmux$2824 $flatten\u_dut.\significandmultiplication.\t8_tile_17.\tablemult.$auto$ghdl.cc:862:import_module$1420 $auto$opt_reduce.cc:135:opt_pmux$2822 $auto$opt_reduce.cc:135:opt_pmux$2820 $auto$opt_reduce.cc:135:opt_pmux$2818 $flatten\u_dut.\significandmultiplication.\t8_tile_17.\tablemult.$auto$ghdl.cc:862:import_module$1429 $auto$opt_reduce.cc:135:opt_pmux$2816 $auto$opt_reduce.cc:135:opt_pmux$2814 $auto$opt_reduce.cc:135:opt_pmux$2812 $flatten\u_dut.\significandmultiplication.\t8_tile_17.\tablemult.$auto$ghdl.cc:862:import_module$1438 $auto$opt_reduce.cc:135:opt_pmux$2810 $auto$opt_reduce.cc:135:opt_pmux$2808 $flatten\u_dut.\significandmultiplication.\t8_tile_17.\tablemult.$auto$ghdl.cc:862:import_module$1447 $auto$opt_reduce.cc:135:opt_pmux$2806 $flatten\u_dut.\significandmultiplication.\t8_tile_17.\tablemult.$auto$ghdl.cc:862:import_module$1456 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_16.tablemult.:5257: { $auto$opt_reduce.cc:135:opt_pmux$2856 $flatten\u_dut.\significandmultiplication.\t8_tile_16.\tablemult.$auto$ghdl.cc:862:import_module$1369 $auto$opt_reduce.cc:135:opt_pmux$2854 $auto$opt_reduce.cc:135:opt_pmux$2852 $auto$opt_reduce.cc:135:opt_pmux$2850 $flatten\u_dut.\significandmultiplication.\t8_tile_16.\tablemult.$auto$ghdl.cc:862:import_module$1373 $auto$opt_reduce.cc:135:opt_pmux$2848 $flatten\u_dut.\significandmultiplication.\t8_tile_16.\tablemult.$auto$ghdl.cc:862:import_module$1375 $flatten\u_dut.\significandmultiplication.\t8_tile_16.\tablemult.$auto$ghdl.cc:862:import_module$1380 $flatten\u_dut.\significandmultiplication.\t8_tile_16.\tablemult.$auto$ghdl.cc:862:import_module$1381 $auto$opt_reduce.cc:135:opt_pmux$2846 $flatten\u_dut.\significandmultiplication.\t8_tile_16.\tablemult.$auto$ghdl.cc:862:import_module$1383 $flatten\u_dut.\significandmultiplication.\t8_tile_16.\tablemult.$auto$ghdl.cc:862:import_module$1387 $flatten\u_dut.\significandmultiplication.\t8_tile_16.\tablemult.$auto$ghdl.cc:862:import_module$1389 $flatten\u_dut.\significandmultiplication.\t8_tile_16.\tablemult.$auto$ghdl.cc:862:import_module$1390 $flatten\u_dut.\significandmultiplication.\t8_tile_16.\tablemult.$auto$ghdl.cc:862:import_module$1391 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_15.tablemult.:5157: { $auto$opt_reduce.cc:135:opt_pmux$2896 $flatten\u_dut.\significandmultiplication.\t8_tile_15.\tablemult.$auto$ghdl.cc:862:import_module$1304 $auto$opt_reduce.cc:135:opt_pmux$2894 $auto$opt_reduce.cc:135:opt_pmux$2892 $auto$opt_reduce.cc:135:opt_pmux$2890 $auto$opt_reduce.cc:135:opt_pmux$2888 $auto$opt_reduce.cc:135:opt_pmux$2886 $auto$opt_reduce.cc:135:opt_pmux$2884 $auto$opt_reduce.cc:135:opt_pmux$2882 $auto$opt_reduce.cc:135:opt_pmux$2880 $auto$opt_reduce.cc:135:opt_pmux$2878 $auto$opt_reduce.cc:135:opt_pmux$2876 $flatten\u_dut.\significandmultiplication.\t8_tile_15.\tablemult.$auto$ghdl.cc:862:import_module$1322 $auto$opt_reduce.cc:135:opt_pmux$2874 $auto$opt_reduce.cc:135:opt_pmux$2872 $auto$opt_reduce.cc:135:opt_pmux$2870 $flatten\u_dut.\significandmultiplication.\t8_tile_15.\tablemult.$auto$ghdl.cc:862:import_module$1331 $auto$opt_reduce.cc:135:opt_pmux$2868 $auto$opt_reduce.cc:135:opt_pmux$2866 $auto$opt_reduce.cc:135:opt_pmux$2864 $flatten\u_dut.\significandmultiplication.\t8_tile_15.\tablemult.$auto$ghdl.cc:862:import_module$1340 $auto$opt_reduce.cc:135:opt_pmux$2862 $auto$opt_reduce.cc:135:opt_pmux$2860 $flatten\u_dut.\significandmultiplication.\t8_tile_15.\tablemult.$auto$ghdl.cc:862:import_module$1349 $auto$opt_reduce.cc:135:opt_pmux$2858 $flatten\u_dut.\significandmultiplication.\t8_tile_15.\tablemult.$auto$ghdl.cc:862:import_module$1358 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_14.tablemult.:4961: { $auto$opt_reduce.cc:135:opt_pmux$2936 $flatten\u_dut.\significandmultiplication.\t8_tile_14.\tablemult.$auto$ghdl.cc:862:import_module$1239 $auto$opt_reduce.cc:135:opt_pmux$2934 $auto$opt_reduce.cc:135:opt_pmux$2932 $auto$opt_reduce.cc:135:opt_pmux$2930 $auto$opt_reduce.cc:135:opt_pmux$2928 $auto$opt_reduce.cc:135:opt_pmux$2926 $auto$opt_reduce.cc:135:opt_pmux$2924 $auto$opt_reduce.cc:135:opt_pmux$2922 $auto$opt_reduce.cc:135:opt_pmux$2920 $auto$opt_reduce.cc:135:opt_pmux$2918 $auto$opt_reduce.cc:135:opt_pmux$2916 $flatten\u_dut.\significandmultiplication.\t8_tile_14.\tablemult.$auto$ghdl.cc:862:import_module$1257 $auto$opt_reduce.cc:135:opt_pmux$2914 $auto$opt_reduce.cc:135:opt_pmux$2912 $auto$opt_reduce.cc:135:opt_pmux$2910 $flatten\u_dut.\significandmultiplication.\t8_tile_14.\tablemult.$auto$ghdl.cc:862:import_module$1266 $auto$opt_reduce.cc:135:opt_pmux$2908 $auto$opt_reduce.cc:135:opt_pmux$2906 $auto$opt_reduce.cc:135:opt_pmux$2904 $flatten\u_dut.\significandmultiplication.\t8_tile_14.\tablemult.$auto$ghdl.cc:862:import_module$1275 $auto$opt_reduce.cc:135:opt_pmux$2902 $auto$opt_reduce.cc:135:opt_pmux$2900 $flatten\u_dut.\significandmultiplication.\t8_tile_14.\tablemult.$auto$ghdl.cc:862:import_module$1284 $auto$opt_reduce.cc:135:opt_pmux$2898 $flatten\u_dut.\significandmultiplication.\t8_tile_14.\tablemult.$auto$ghdl.cc:862:import_module$1293 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_13.tablemult.:4765: { $auto$opt_reduce.cc:135:opt_pmux$2976 $flatten\u_dut.\significandmultiplication.\t8_tile_13.\tablemult.$auto$ghdl.cc:862:import_module$1174 $auto$opt_reduce.cc:135:opt_pmux$2974 $auto$opt_reduce.cc:135:opt_pmux$2972 $auto$opt_reduce.cc:135:opt_pmux$2970 $auto$opt_reduce.cc:135:opt_pmux$2968 $auto$opt_reduce.cc:135:opt_pmux$2966 $auto$opt_reduce.cc:135:opt_pmux$2964 $auto$opt_reduce.cc:135:opt_pmux$2962 $auto$opt_reduce.cc:135:opt_pmux$2960 $auto$opt_reduce.cc:135:opt_pmux$2958 $auto$opt_reduce.cc:135:opt_pmux$2956 $flatten\u_dut.\significandmultiplication.\t8_tile_13.\tablemult.$auto$ghdl.cc:862:import_module$1192 $auto$opt_reduce.cc:135:opt_pmux$2954 $auto$opt_reduce.cc:135:opt_pmux$2952 $auto$opt_reduce.cc:135:opt_pmux$2950 $flatten\u_dut.\significandmultiplication.\t8_tile_13.\tablemult.$auto$ghdl.cc:862:import_module$1201 $auto$opt_reduce.cc:135:opt_pmux$2948 $auto$opt_reduce.cc:135:opt_pmux$2946 $auto$opt_reduce.cc:135:opt_pmux$2944 $flatten\u_dut.\significandmultiplication.\t8_tile_13.\tablemult.$auto$ghdl.cc:862:import_module$1210 $auto$opt_reduce.cc:135:opt_pmux$2942 $auto$opt_reduce.cc:135:opt_pmux$2940 $flatten\u_dut.\significandmultiplication.\t8_tile_13.\tablemult.$auto$ghdl.cc:862:import_module$1219 $auto$opt_reduce.cc:135:opt_pmux$2938 $flatten\u_dut.\significandmultiplication.\t8_tile_13.\tablemult.$auto$ghdl.cc:862:import_module$1228 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_12.tablemult.:4569: { $auto$opt_reduce.cc:135:opt_pmux$2988 $flatten\u_dut.\significandmultiplication.\t8_tile_12.\tablemult.$auto$ghdl.cc:862:import_module$1141 $auto$opt_reduce.cc:135:opt_pmux$2986 $auto$opt_reduce.cc:135:opt_pmux$2984 $auto$opt_reduce.cc:135:opt_pmux$2982 $flatten\u_dut.\significandmultiplication.\t8_tile_12.\tablemult.$auto$ghdl.cc:862:import_module$1145 $auto$opt_reduce.cc:135:opt_pmux$2980 $flatten\u_dut.\significandmultiplication.\t8_tile_12.\tablemult.$auto$ghdl.cc:862:import_module$1147 $flatten\u_dut.\significandmultiplication.\t8_tile_12.\tablemult.$auto$ghdl.cc:862:import_module$1152 $flatten\u_dut.\significandmultiplication.\t8_tile_12.\tablemult.$auto$ghdl.cc:862:import_module$1153 $auto$opt_reduce.cc:135:opt_pmux$2978 $flatten\u_dut.\significandmultiplication.\t8_tile_12.\tablemult.$auto$ghdl.cc:862:import_module$1155 $flatten\u_dut.\significandmultiplication.\t8_tile_12.\tablemult.$auto$ghdl.cc:862:import_module$1159 $flatten\u_dut.\significandmultiplication.\t8_tile_12.\tablemult.$auto$ghdl.cc:862:import_module$1161 $flatten\u_dut.\significandmultiplication.\t8_tile_12.\tablemult.$auto$ghdl.cc:862:import_module$1162 $flatten\u_dut.\significandmultiplication.\t8_tile_12.\tablemult.$auto$ghdl.cc:862:import_module$1163 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_11.tablemult.:4469: { $auto$opt_reduce.cc:135:opt_pmux$3028 $flatten\u_dut.\significandmultiplication.\t8_tile_11.\tablemult.$auto$ghdl.cc:862:import_module$1076 $auto$opt_reduce.cc:135:opt_pmux$3026 $auto$opt_reduce.cc:135:opt_pmux$3024 $auto$opt_reduce.cc:135:opt_pmux$3022 $auto$opt_reduce.cc:135:opt_pmux$3020 $auto$opt_reduce.cc:135:opt_pmux$3018 $auto$opt_reduce.cc:135:opt_pmux$3016 $auto$opt_reduce.cc:135:opt_pmux$3014 $auto$opt_reduce.cc:135:opt_pmux$3012 $auto$opt_reduce.cc:135:opt_pmux$3010 $auto$opt_reduce.cc:135:opt_pmux$3008 $flatten\u_dut.\significandmultiplication.\t8_tile_11.\tablemult.$auto$ghdl.cc:862:import_module$1094 $auto$opt_reduce.cc:135:opt_pmux$3006 $auto$opt_reduce.cc:135:opt_pmux$3004 $auto$opt_reduce.cc:135:opt_pmux$3002 $flatten\u_dut.\significandmultiplication.\t8_tile_11.\tablemult.$auto$ghdl.cc:862:import_module$1103 $auto$opt_reduce.cc:135:opt_pmux$3000 $auto$opt_reduce.cc:135:opt_pmux$2998 $auto$opt_reduce.cc:135:opt_pmux$2996 $flatten\u_dut.\significandmultiplication.\t8_tile_11.\tablemult.$auto$ghdl.cc:862:import_module$1112 $auto$opt_reduce.cc:135:opt_pmux$2994 $auto$opt_reduce.cc:135:opt_pmux$2992 $flatten\u_dut.\significandmultiplication.\t8_tile_11.\tablemult.$auto$ghdl.cc:862:import_module$1121 $auto$opt_reduce.cc:135:opt_pmux$2990 $flatten\u_dut.\significandmultiplication.\t8_tile_11.\tablemult.$auto$ghdl.cc:862:import_module$1130 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_10.tablemult.:4273: { $auto$opt_reduce.cc:135:opt_pmux$3068 $flatten\u_dut.\significandmultiplication.\t8_tile_10.\tablemult.$auto$ghdl.cc:862:import_module$1011 $auto$opt_reduce.cc:135:opt_pmux$3066 $auto$opt_reduce.cc:135:opt_pmux$3064 $auto$opt_reduce.cc:135:opt_pmux$3062 $auto$opt_reduce.cc:135:opt_pmux$3060 $auto$opt_reduce.cc:135:opt_pmux$3058 $auto$opt_reduce.cc:135:opt_pmux$3056 $auto$opt_reduce.cc:135:opt_pmux$3054 $auto$opt_reduce.cc:135:opt_pmux$3052 $auto$opt_reduce.cc:135:opt_pmux$3050 $auto$opt_reduce.cc:135:opt_pmux$3048 $flatten\u_dut.\significandmultiplication.\t8_tile_10.\tablemult.$auto$ghdl.cc:862:import_module$1029 $auto$opt_reduce.cc:135:opt_pmux$3046 $auto$opt_reduce.cc:135:opt_pmux$3044 $auto$opt_reduce.cc:135:opt_pmux$3042 $flatten\u_dut.\significandmultiplication.\t8_tile_10.\tablemult.$auto$ghdl.cc:862:import_module$1038 $auto$opt_reduce.cc:135:opt_pmux$3040 $auto$opt_reduce.cc:135:opt_pmux$3038 $auto$opt_reduce.cc:135:opt_pmux$3036 $flatten\u_dut.\significandmultiplication.\t8_tile_10.\tablemult.$auto$ghdl.cc:862:import_module$1047 $auto$opt_reduce.cc:135:opt_pmux$3034 $auto$opt_reduce.cc:135:opt_pmux$3032 $flatten\u_dut.\significandmultiplication.\t8_tile_10.\tablemult.$auto$ghdl.cc:862:import_module$1056 $auto$opt_reduce.cc:135:opt_pmux$3030 $flatten\u_dut.\significandmultiplication.\t8_tile_10.\tablemult.$auto$ghdl.cc:862:import_module$1065 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_9.tablemult.:4077: { $auto$opt_reduce.cc:135:opt_pmux$3080 $flatten\u_dut.\significandmultiplication.\t8_tile_9.\tablemult.$auto$ghdl.cc:862:import_module$978 $auto$opt_reduce.cc:135:opt_pmux$3078 $auto$opt_reduce.cc:135:opt_pmux$3076 $auto$opt_reduce.cc:135:opt_pmux$3074 $flatten\u_dut.\significandmultiplication.\t8_tile_9.\tablemult.$auto$ghdl.cc:862:import_module$982 $auto$opt_reduce.cc:135:opt_pmux$3072 $flatten\u_dut.\significandmultiplication.\t8_tile_9.\tablemult.$auto$ghdl.cc:862:import_module$984 $flatten\u_dut.\significandmultiplication.\t8_tile_9.\tablemult.$auto$ghdl.cc:862:import_module$989 $flatten\u_dut.\significandmultiplication.\t8_tile_9.\tablemult.$auto$ghdl.cc:862:import_module$990 $auto$opt_reduce.cc:135:opt_pmux$3070 $flatten\u_dut.\significandmultiplication.\t8_tile_9.\tablemult.$auto$ghdl.cc:862:import_module$992 $flatten\u_dut.\significandmultiplication.\t8_tile_9.\tablemult.$auto$ghdl.cc:862:import_module$996 $flatten\u_dut.\significandmultiplication.\t8_tile_9.\tablemult.$auto$ghdl.cc:862:import_module$998 $flatten\u_dut.\significandmultiplication.\t8_tile_9.\tablemult.$auto$ghdl.cc:862:import_module$999 $flatten\u_dut.\significandmultiplication.\t8_tile_9.\tablemult.$auto$ghdl.cc:862:import_module$1000 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_8.tablemult.:3977: { $auto$opt_reduce.cc:135:opt_pmux$3120 $flatten\u_dut.\significandmultiplication.\t8_tile_8.\tablemult.$auto$ghdl.cc:862:import_module$913 $auto$opt_reduce.cc:135:opt_pmux$3118 $auto$opt_reduce.cc:135:opt_pmux$3116 $auto$opt_reduce.cc:135:opt_pmux$3114 $auto$opt_reduce.cc:135:opt_pmux$3112 $auto$opt_reduce.cc:135:opt_pmux$3110 $auto$opt_reduce.cc:135:opt_pmux$3108 $auto$opt_reduce.cc:135:opt_pmux$3106 $auto$opt_reduce.cc:135:opt_pmux$3104 $auto$opt_reduce.cc:135:opt_pmux$3102 $auto$opt_reduce.cc:135:opt_pmux$3100 $flatten\u_dut.\significandmultiplication.\t8_tile_8.\tablemult.$auto$ghdl.cc:862:import_module$931 $auto$opt_reduce.cc:135:opt_pmux$3098 $auto$opt_reduce.cc:135:opt_pmux$3096 $auto$opt_reduce.cc:135:opt_pmux$3094 $flatten\u_dut.\significandmultiplication.\t8_tile_8.\tablemult.$auto$ghdl.cc:862:import_module$940 $auto$opt_reduce.cc:135:opt_pmux$3092 $auto$opt_reduce.cc:135:opt_pmux$3090 $auto$opt_reduce.cc:135:opt_pmux$3088 $flatten\u_dut.\significandmultiplication.\t8_tile_8.\tablemult.$auto$ghdl.cc:862:import_module$949 $auto$opt_reduce.cc:135:opt_pmux$3086 $auto$opt_reduce.cc:135:opt_pmux$3084 $flatten\u_dut.\significandmultiplication.\t8_tile_8.\tablemult.$auto$ghdl.cc:862:import_module$958 $auto$opt_reduce.cc:135:opt_pmux$3082 $flatten\u_dut.\significandmultiplication.\t8_tile_8.\tablemult.$auto$ghdl.cc:862:import_module$967 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_7.tablemult.:3781: { $auto$opt_reduce.cc:135:opt_pmux$3132 $flatten\u_dut.\significandmultiplication.\t8_tile_7.\tablemult.$auto$ghdl.cc:862:import_module$880 $auto$opt_reduce.cc:135:opt_pmux$3130 $auto$opt_reduce.cc:135:opt_pmux$3128 $auto$opt_reduce.cc:135:opt_pmux$3126 $flatten\u_dut.\significandmultiplication.\t8_tile_7.\tablemult.$auto$ghdl.cc:862:import_module$884 $auto$opt_reduce.cc:135:opt_pmux$3124 $flatten\u_dut.\significandmultiplication.\t8_tile_7.\tablemult.$auto$ghdl.cc:862:import_module$886 $flatten\u_dut.\significandmultiplication.\t8_tile_7.\tablemult.$auto$ghdl.cc:862:import_module$891 $flatten\u_dut.\significandmultiplication.\t8_tile_7.\tablemult.$auto$ghdl.cc:862:import_module$892 $auto$opt_reduce.cc:135:opt_pmux$3122 $flatten\u_dut.\significandmultiplication.\t8_tile_7.\tablemult.$auto$ghdl.cc:862:import_module$894 $flatten\u_dut.\significandmultiplication.\t8_tile_7.\tablemult.$auto$ghdl.cc:862:import_module$898 $flatten\u_dut.\significandmultiplication.\t8_tile_7.\tablemult.$auto$ghdl.cc:862:import_module$900 $flatten\u_dut.\significandmultiplication.\t8_tile_7.\tablemult.$auto$ghdl.cc:862:import_module$901 $flatten\u_dut.\significandmultiplication.\t8_tile_7.\tablemult.$auto$ghdl.cc:862:import_module$902 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_6.tablemult.:3681: { $auto$opt_reduce.cc:135:opt_pmux$3144 $flatten\u_dut.\significandmultiplication.\t8_tile_6.\tablemult.$auto$ghdl.cc:862:import_module$847 $auto$opt_reduce.cc:135:opt_pmux$3142 $auto$opt_reduce.cc:135:opt_pmux$3140 $auto$opt_reduce.cc:135:opt_pmux$3138 $flatten\u_dut.\significandmultiplication.\t8_tile_6.\tablemult.$auto$ghdl.cc:862:import_module$851 $auto$opt_reduce.cc:135:opt_pmux$3136 $flatten\u_dut.\significandmultiplication.\t8_tile_6.\tablemult.$auto$ghdl.cc:862:import_module$853 $flatten\u_dut.\significandmultiplication.\t8_tile_6.\tablemult.$auto$ghdl.cc:862:import_module$858 $flatten\u_dut.\significandmultiplication.\t8_tile_6.\tablemult.$auto$ghdl.cc:862:import_module$859 $auto$opt_reduce.cc:135:opt_pmux$3134 $flatten\u_dut.\significandmultiplication.\t8_tile_6.\tablemult.$auto$ghdl.cc:862:import_module$861 $flatten\u_dut.\significandmultiplication.\t8_tile_6.\tablemult.$auto$ghdl.cc:862:import_module$865 $flatten\u_dut.\significandmultiplication.\t8_tile_6.\tablemult.$auto$ghdl.cc:862:import_module$867 $flatten\u_dut.\significandmultiplication.\t8_tile_6.\tablemult.$auto$ghdl.cc:862:import_module$868 $flatten\u_dut.\significandmultiplication.\t8_tile_6.\tablemult.$auto$ghdl.cc:862:import_module$869 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_5.tablemult.:3581: { $auto$opt_reduce.cc:135:opt_pmux$3156 $flatten\u_dut.\significandmultiplication.\t8_tile_5.\tablemult.$auto$ghdl.cc:862:import_module$814 $auto$opt_reduce.cc:135:opt_pmux$3154 $auto$opt_reduce.cc:135:opt_pmux$3152 $auto$opt_reduce.cc:135:opt_pmux$3150 $flatten\u_dut.\significandmultiplication.\t8_tile_5.\tablemult.$auto$ghdl.cc:862:import_module$818 $auto$opt_reduce.cc:135:opt_pmux$3148 $flatten\u_dut.\significandmultiplication.\t8_tile_5.\tablemult.$auto$ghdl.cc:862:import_module$820 $flatten\u_dut.\significandmultiplication.\t8_tile_5.\tablemult.$auto$ghdl.cc:862:import_module$825 $flatten\u_dut.\significandmultiplication.\t8_tile_5.\tablemult.$auto$ghdl.cc:862:import_module$826 $auto$opt_reduce.cc:135:opt_pmux$3146 $flatten\u_dut.\significandmultiplication.\t8_tile_5.\tablemult.$auto$ghdl.cc:862:import_module$828 $flatten\u_dut.\significandmultiplication.\t8_tile_5.\tablemult.$auto$ghdl.cc:862:import_module$832 $flatten\u_dut.\significandmultiplication.\t8_tile_5.\tablemult.$auto$ghdl.cc:862:import_module$834 $flatten\u_dut.\significandmultiplication.\t8_tile_5.\tablemult.$auto$ghdl.cc:862:import_module$835 $flatten\u_dut.\significandmultiplication.\t8_tile_5.\tablemult.$auto$ghdl.cc:862:import_module$836 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_4.tablemult.:3481: { $auto$opt_reduce.cc:135:opt_pmux$3168 $flatten\u_dut.\significandmultiplication.\t8_tile_4.\tablemult.$auto$ghdl.cc:862:import_module$781 $auto$opt_reduce.cc:135:opt_pmux$3166 $auto$opt_reduce.cc:135:opt_pmux$3164 $auto$opt_reduce.cc:135:opt_pmux$3162 $flatten\u_dut.\significandmultiplication.\t8_tile_4.\tablemult.$auto$ghdl.cc:862:import_module$785 $auto$opt_reduce.cc:135:opt_pmux$3160 $flatten\u_dut.\significandmultiplication.\t8_tile_4.\tablemult.$auto$ghdl.cc:862:import_module$787 $flatten\u_dut.\significandmultiplication.\t8_tile_4.\tablemult.$auto$ghdl.cc:862:import_module$792 $flatten\u_dut.\significandmultiplication.\t8_tile_4.\tablemult.$auto$ghdl.cc:862:import_module$793 $auto$opt_reduce.cc:135:opt_pmux$3158 $flatten\u_dut.\significandmultiplication.\t8_tile_4.\tablemult.$auto$ghdl.cc:862:import_module$795 $flatten\u_dut.\significandmultiplication.\t8_tile_4.\tablemult.$auto$ghdl.cc:862:import_module$799 $flatten\u_dut.\significandmultiplication.\t8_tile_4.\tablemult.$auto$ghdl.cc:862:import_module$801 $flatten\u_dut.\significandmultiplication.\t8_tile_4.\tablemult.$auto$ghdl.cc:862:import_module$802 $flatten\u_dut.\significandmultiplication.\t8_tile_4.\tablemult.$auto$ghdl.cc:862:import_module$803 } New ctrl vector for $pmux cell \u_dut.significandmultiplication.t8_tile_3.tablemult.:3381: { $auto$opt_reduce.cc:135:opt_pmux$3172 $flatten\u_dut.\significandmultiplication.\t8_tile_3.\tablemult.$auto$ghdl.cc:862:import_module$751 $flatten\u_dut.\significandmultiplication.\t8_tile_3.\tablemult.$auto$ghdl.cc:862:import_module$752 $flatten\u_dut.\significandmultiplication.\t8_tile_3.\tablemult.$auto$ghdl.cc:862:import_module$753 $flatten\u_dut.\significandmultiplication.\t8_tile_3.\tablemult.$auto$ghdl.cc:862:import_module$754 $flatten\u_dut.\significandmultiplication.\t8_tile_3.\tablemult.$auto$ghdl.cc:862:import_module$759 $flatten\u_dut.\significandmultiplication.\t8_tile_3.\tablemult.$auto$ghdl.cc:862:import_module$760 $auto$opt_reduce.cc:135:opt_pmux$3170 $flatten\u_dut.\significandmultiplication.\t8_tile_3.\tablemult.$auto$ghdl.cc:862:import_module$762 $flatten\u_dut.\significandmultiplication.\t8_tile_3.\tablemult.$auto$ghdl.cc:862:import_module$768 $flatten\u_dut.\significandmultiplication.\t8_tile_3.\tablemult.$auto$ghdl.cc:862:import_module$769 $flatten\u_dut.\significandmultiplication.\t8_tile_3.\tablemult.$auto$ghdl.cc:862:import_module$770 } Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 25 changes. 2.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 7020 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.12.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3272 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3272 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3272 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3272 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3272 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3272 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3272 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3272 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3272 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3272 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3266 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3259 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3259 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3259 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3259 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3259 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3259 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3259 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3254 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3247 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3247 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3247 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3247 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3247 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3247 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3247 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3243 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3236 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3236 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3236 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3236 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3236 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3236 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3236 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3233 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3226 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3226 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3226 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3226 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3226 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3226 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3224 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3216 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3217 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3217 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3217 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3214 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 1-bit at position 0 on u_dut.:174 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 1-bit at position 1 on u_dut.:174 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 1-bit at position 2 on u_dut.:174 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 1-bit at position 3 on u_dut.:174 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 1-bit at position 4 on u_dut.:174 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 1-bit at position 5 on u_dut.:174 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 1-bit at position 6 on u_dut.:174 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.:174 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.:174 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.:174 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2501 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2501 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2496 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2482 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2482 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.roundingadder.:2482 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.roundingadder.:2482 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.roundingadder.:2482 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.roundingadder.:2482 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.roundingadder.:2482 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.roundingadder.:2482 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.roundingadder.:2482 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.roundingadder.:2482 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.roundingadder.:2482 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2482 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2478 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2461 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2445 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2430 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Removed 0 unused cells and 2495 unused wires. 2.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.9. Rerunning OPT passes. (Maybe there is more to do..) 2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 7015 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.12.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3273 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3273 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3273 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3273 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3273 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3273 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3273 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3273 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3273 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3273 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3267 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3260 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3260 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3260 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3260 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3260 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3260 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3260 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3255 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3248 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3248 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3248 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3248 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3248 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3248 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3248 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3244 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3234 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3237 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3237 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3237 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3237 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3237 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3237 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3237 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3227 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3227 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3227 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3227 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3227 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3227 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3225 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3215 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2502 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2502 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2497 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2483 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2483 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.roundingadder.:2483 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.roundingadder.:2483 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.roundingadder.:2483 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.roundingadder.:2483 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.roundingadder.:2483 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.roundingadder.:2483 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.roundingadder.:2483 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.roundingadder.:2483 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.roundingadder.:2483 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2483 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2479 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2462 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2446 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. 2.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.16. Rerunning OPT passes. (Maybe there is more to do..) 2.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.12.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 7011 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.12.20. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3274 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3274 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3274 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3274 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3274 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3274 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3274 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3274 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3274 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3274 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3268 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3261 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3261 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3261 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3261 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3261 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3261 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3261 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3256 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3249 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3249 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3249 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3249 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3249 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3249 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3249 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3245 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3235 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3238 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3238 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3238 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3238 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3238 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3238 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3238 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2503 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2503 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2498 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2484 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2484 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.roundingadder.:2484 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.roundingadder.:2484 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.roundingadder.:2484 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.roundingadder.:2484 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.roundingadder.:2484 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.roundingadder.:2484 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.roundingadder.:2484 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.roundingadder.:2484 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.roundingadder.:2484 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2484 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2480 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2463 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Removed 0 unused cells and 1 unused wires. 2.12.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.23. Rerunning OPT passes. (Maybe there is more to do..) 2.12.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.12.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 7007 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.12.27. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3275 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3275 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3275 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3275 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3275 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3275 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3275 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3275 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3275 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3275 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3269 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3257 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3262 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3262 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3262 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3262 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3262 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3262 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3262 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3250 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3250 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3250 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3250 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3250 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3250 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3250 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3246 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2504 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2504 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2499 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2485 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2485 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.roundingadder.:2485 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.roundingadder.:2485 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.roundingadder.:2485 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.roundingadder.:2485 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.roundingadder.:2485 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.roundingadder.:2485 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.roundingadder.:2485 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.roundingadder.:2485 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.roundingadder.:2485 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2485 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2481 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. 2.12.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.30. Rerunning OPT passes. (Maybe there is more to do..) 2.12.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.12.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 7004 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.12.34. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3276 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3276 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3276 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3276 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3276 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3276 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3276 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3276 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3276 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3276 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3263 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3263 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3263 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3263 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3263 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3263 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3263 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3270 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3258 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2505 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2505 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2500 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2486 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2486 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.roundingadder.:2486 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.roundingadder.:2486 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.roundingadder.:2486 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.roundingadder.:2486 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.roundingadder.:2486 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.roundingadder.:2486 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.roundingadder.:2486 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.roundingadder.:2486 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.roundingadder.:2486 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2486 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. 2.12.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.37. Rerunning OPT passes. (Maybe there is more to do..) 2.12.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.12.40. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 7001 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.12.41. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3277 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3277 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3277 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3277 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3277 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3277 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3277 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3277 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3277 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3277 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.significandmultiplication.bitheapfinaladd_bh7.:3271 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2506 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2506 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2487 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2487 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.roundingadder.:2487 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.roundingadder.:2487 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.roundingadder.:2487 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.roundingadder.:2487 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.roundingadder.:2487 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.roundingadder.:2487 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.roundingadder.:2487 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.roundingadder.:2487 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.roundingadder.:2487 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2487 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.42. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. 2.12.43. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.44. Rerunning OPT passes. (Maybe there is more to do..) 2.12.45. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.46. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.12.47. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6998 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.12.48. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.roundingadder.:2507 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2507 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2488 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2488 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.roundingadder.:2488 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.roundingadder.:2488 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.roundingadder.:2488 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.roundingadder.:2488 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.roundingadder.:2488 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.roundingadder.:2488 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.roundingadder.:2488 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.roundingadder.:2488 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.roundingadder.:2488 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2488 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.49. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Removed 0 unused cells and 1 unused wires. 2.12.50. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.51. Rerunning OPT passes. (Maybe there is more to do..) 2.12.52. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.53. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.12.54. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6995 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.12.55. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.roundingadder.:2508 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2508 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2489 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2489 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.roundingadder.:2489 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.roundingadder.:2489 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.roundingadder.:2489 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.roundingadder.:2489 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.roundingadder.:2489 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.roundingadder.:2489 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.roundingadder.:2489 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.roundingadder.:2489 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.roundingadder.:2489 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2489 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.56. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. 2.12.57. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.58. Rerunning OPT passes. (Maybe there is more to do..) 2.12.59. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.60. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.12.61. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6993 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.12.62. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.roundingadder.:2509 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2509 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2490 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2490 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.roundingadder.:2490 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.roundingadder.:2490 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.roundingadder.:2490 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.roundingadder.:2490 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.roundingadder.:2490 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.roundingadder.:2490 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.roundingadder.:2490 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.roundingadder.:2490 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.roundingadder.:2490 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2490 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.63. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. 2.12.64. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.65. Rerunning OPT passes. (Maybe there is more to do..) 2.12.66. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.67. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.12.68. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6991 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.12.69. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.roundingadder.:2510 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2510 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2491 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2491 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.roundingadder.:2491 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.roundingadder.:2491 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.roundingadder.:2491 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.roundingadder.:2491 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.roundingadder.:2491 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.roundingadder.:2491 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.roundingadder.:2491 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.roundingadder.:2491 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.roundingadder.:2491 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2491 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.70. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Removed 0 unused cells and 1 unused wires. 2.12.71. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.72. Rerunning OPT passes. (Maybe there is more to do..) 2.12.73. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.74. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.12.75. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6988 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.12.76. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.roundingadder.:2511 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2511 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2492 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2492 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.roundingadder.:2492 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.roundingadder.:2492 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.roundingadder.:2492 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.roundingadder.:2492 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.roundingadder.:2492 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.roundingadder.:2492 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.roundingadder.:2492 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.roundingadder.:2492 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.roundingadder.:2492 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2492 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.77. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Removed 0 unused cells and 1 unused wires. 2.12.78. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.79. Rerunning OPT passes. (Maybe there is more to do..) 2.12.80. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.81. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.12.82. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6985 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.12.83. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.roundingadder.:2512 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2512 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 0 on u_dut.roundingadder.:2493 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2493 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 2 on u_dut.roundingadder.:2493 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 3 on u_dut.roundingadder.:2493 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 4 on u_dut.roundingadder.:2493 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 5 on u_dut.roundingadder.:2493 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 6 on u_dut.roundingadder.:2493 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 7 on u_dut.roundingadder.:2493 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 8 on u_dut.roundingadder.:2493 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 9 on u_dut.roundingadder.:2493 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 10 on u_dut.roundingadder.:2493 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 11 on u_dut.roundingadder.:2493 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.84. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Removed 0 unused cells and 1 unused wires. 2.12.85. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.86. Rerunning OPT passes. (Maybe there is more to do..) 2.12.87. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.88. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.12.89. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6982 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.12.90. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.roundingadder.:2513 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. Setting constant 0-bit at position 1 on u_dut.roundingadder.:2513 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.91. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Removed 0 unused cells and 1 unused wires. 2.12.92. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.93. Rerunning OPT passes. (Maybe there is more to do..) 2.12.94. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.95. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.12.96. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6980 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.12.97. Executing OPT_DFF pass (perform DFF optimizations). 2.12.98. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Removed 0 unused cells and 1 unused wires. 2.12.99. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.100. Rerunning OPT passes. (Maybe there is more to do..) 2.12.101. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.102. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.12.103. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6979 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.12.104. Executing OPT_DFF pass (perform DFF optimizations). 2.12.105. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. 2.12.106. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.12.107. Finished fast OPT passes. (There is nothing left to do.) 2.13. Executing FSM pass (extract and optimize FSM). 2.13.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid334_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid332_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid330_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid328_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid326_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid324_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid322_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid320_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid318_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid316_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid314_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_bh7_uid312_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid310_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid308_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid306_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid304_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid302_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid300_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid298_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid296_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid294_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid292_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_bh7_uid290_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid288_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid286_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid284_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid282_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid280_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid278_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid276_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid274_out0 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.exc_d1 as FSM state register: Users of register don't seem to benefit from recoding. 2.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. 2.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2.14. Executing OPT pass (performing simple optimizations). 2.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6979 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6979 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.14.6. Executing OPT_DFF pass (perform DFF optimizations). 2.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. 2.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.14.9. Finished fast OPT passes. (There is nothing left to do.) 2.15. Executing WREDUCE pass (reducing word size of cells). Removed top 1 bits (of 12) from port A of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.roundingadder.:2379 ($add). Removed top 11 bits (of 12) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.roundingadder.:2379 ($add). Removed top 1 bits (of 12) from port A of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.roundingadder.:2390 ($add). Removed top 11 bits (of 12) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.roundingadder.:2390 ($add). Removed top 1 bits (of 12) from port A of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.roundingadder.:2401 ($add). Removed top 11 bits (of 12) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.roundingadder.:2401 ($add). Removed top 1 bits (of 12) from port A of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.roundingadder.:2412 ($add). Removed top 11 bits (of 12) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.roundingadder.:2412 ($add). Removed top 1 bits (of 2) from port A of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.roundingadder.:2423 ($add). Removed top 1 bits (of 2) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.roundingadder.:2423 ($add). Removed top 1 bits (of 2) from port Y of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.roundingadder.:2423 ($add). Removed top 17 bits (of 41) from port A of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_1.:2521 ($mul). Removed top 24 bits (of 41) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_1.:2521 ($mul). Removed top 18 bits (of 43) from port A of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_2.dsp0_0.:3281 ($mul). Removed top 26 bits (of 39) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_2.dsp0_0.:3281 ($mul). Converting cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_2.dsp0_0.:3281 ($mul) from signed to unsigned. Removed top 2 bits (of 39) from port Y of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_2.dsp0_0.:3281 ($mul). Removed top 1 bits (of 25) from port A of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_2.dsp0_0.:3281 ($mul). Removed top 1 bits (of 13) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_2.dsp0_0.:3281 ($mul). Removed top 1 bits (of 37) from port Y of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_2.dsp0_0.:3281 ($mul). Removed top 1 bits (of 12) from port A of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.bitheapfinaladd_bh7.:3150 ($add). Removed top 1 bits (of 12) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.bitheapfinaladd_bh7.:3150 ($add). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_3.tablemult.:3300 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_3.tablemult.:3303 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_3.tablemult.:3306 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_3.tablemult.:3321 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_3.tablemult.:3324 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_3.tablemult.:3327 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_3.tablemult.:3330 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_4.tablemult.:3388 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_4.tablemult.:3391 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_4.tablemult.:3394 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_4.tablemult.:3397 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_4.tablemult.:3400 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_4.tablemult.:3403 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_4.tablemult.:3406 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_4.tablemult.:3409 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_4.tablemult.:3412 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_4.tablemult.:3415 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_4.tablemult.:3418 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_4.tablemult.:3421 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_4.tablemult.:3424 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_4.tablemult.:3427 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_4.tablemult.:3430 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_5.tablemult.:3488 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_5.tablemult.:3491 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_5.tablemult.:3494 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_5.tablemult.:3497 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_5.tablemult.:3500 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_5.tablemult.:3503 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_5.tablemult.:3506 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_5.tablemult.:3509 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_5.tablemult.:3512 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_5.tablemult.:3515 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_5.tablemult.:3518 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_5.tablemult.:3521 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_5.tablemult.:3524 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_5.tablemult.:3527 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_5.tablemult.:3530 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_6.tablemult.:3588 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_6.tablemult.:3591 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_6.tablemult.:3594 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_6.tablemult.:3597 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_6.tablemult.:3600 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_6.tablemult.:3603 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_6.tablemult.:3606 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_6.tablemult.:3609 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_6.tablemult.:3612 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_6.tablemult.:3615 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_6.tablemult.:3618 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_6.tablemult.:3621 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_6.tablemult.:3624 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_6.tablemult.:3627 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_6.tablemult.:3630 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_7.tablemult.:3688 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_7.tablemult.:3691 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_7.tablemult.:3694 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_7.tablemult.:3697 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_7.tablemult.:3700 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_7.tablemult.:3703 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_7.tablemult.:3706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_7.tablemult.:3709 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_7.tablemult.:3712 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_7.tablemult.:3715 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_7.tablemult.:3718 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_7.tablemult.:3721 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_7.tablemult.:3724 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_7.tablemult.:3727 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_7.tablemult.:3730 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3788 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3791 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3794 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3797 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3800 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3803 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3806 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3809 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3812 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3815 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3818 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3821 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3824 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3827 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3830 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3833 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3836 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3839 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3842 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3845 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3848 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3851 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3854 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3857 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3860 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3863 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3866 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3869 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3872 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3875 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_8.tablemult.:3878 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_9.tablemult.:3984 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_9.tablemult.:3987 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_9.tablemult.:3990 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_9.tablemult.:3993 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_9.tablemult.:3996 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_9.tablemult.:3999 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_9.tablemult.:4002 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_9.tablemult.:4005 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_9.tablemult.:4008 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_9.tablemult.:4011 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_9.tablemult.:4014 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_9.tablemult.:4017 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_9.tablemult.:4020 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_9.tablemult.:4023 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_9.tablemult.:4026 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4084 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4087 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4090 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4093 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4096 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4099 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4102 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4105 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4108 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4111 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4114 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4117 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4120 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4123 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4126 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4129 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4132 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4135 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4138 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4141 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4144 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4147 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4150 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4153 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4156 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4159 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4162 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4165 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4168 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4171 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_10.tablemult.:4174 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4280 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4283 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4286 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4289 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4292 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4295 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4298 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4301 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4304 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4307 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4310 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4313 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4316 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4319 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4322 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4325 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4328 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4331 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4334 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4337 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4340 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4343 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4346 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4349 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4352 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4355 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4358 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4361 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4364 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4367 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_11.tablemult.:4370 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_12.tablemult.:4476 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_12.tablemult.:4479 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_12.tablemult.:4482 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_12.tablemult.:4485 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_12.tablemult.:4488 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_12.tablemult.:4491 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_12.tablemult.:4494 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_12.tablemult.:4497 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_12.tablemult.:4500 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_12.tablemult.:4503 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_12.tablemult.:4506 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_12.tablemult.:4509 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_12.tablemult.:4512 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_12.tablemult.:4515 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_12.tablemult.:4518 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4576 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4579 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4582 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4585 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4588 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4591 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4594 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4597 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4600 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4603 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4606 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4609 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4612 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4615 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4618 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4621 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4624 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4627 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4630 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4633 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4636 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4639 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4642 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4645 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4648 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4651 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4654 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4657 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4660 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4663 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_13.tablemult.:4666 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4772 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4775 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4778 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4781 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4784 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4787 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4790 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4793 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4796 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4799 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4802 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4805 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4808 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4811 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4814 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4817 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4820 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4823 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4826 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4829 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4832 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4835 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4838 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4841 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4844 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4847 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4850 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4853 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4856 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4859 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_14.tablemult.:4862 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:4968 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:4971 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:4974 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:4977 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:4980 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:4983 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:4986 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:4989 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:4992 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:4995 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:4998 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5001 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5004 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5007 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5010 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5013 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5016 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5019 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5022 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5025 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5028 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5031 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5034 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5037 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5040 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5043 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5046 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5049 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5052 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5055 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_15.tablemult.:5058 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_16.tablemult.:5164 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_16.tablemult.:5167 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_16.tablemult.:5170 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_16.tablemult.:5173 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_16.tablemult.:5176 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_16.tablemult.:5179 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_16.tablemult.:5182 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_16.tablemult.:5185 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_16.tablemult.:5188 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_16.tablemult.:5191 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_16.tablemult.:5194 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_16.tablemult.:5197 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_16.tablemult.:5200 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_16.tablemult.:5203 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_16.tablemult.:5206 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5264 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5267 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5270 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5273 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5276 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5279 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5282 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5285 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5288 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5291 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5294 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5297 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5300 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5303 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5306 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5309 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5312 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5315 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5318 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5321 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5324 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5327 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5330 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5333 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5336 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5339 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5342 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5345 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5348 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5351 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_17.tablemult.:5354 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5460 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5463 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5466 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5469 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5472 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5475 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5478 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5481 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5484 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5487 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5490 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5493 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5496 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5499 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5502 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5505 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5508 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5511 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5514 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5517 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5520 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5523 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5526 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5529 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5532 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5535 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5538 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5541 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5544 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5547 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_18.tablemult.:5550 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5656 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5659 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5662 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5665 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5668 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5671 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5674 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5677 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5680 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5683 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5686 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5689 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5692 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5695 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5698 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5701 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5704 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5707 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5710 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5713 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5716 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5719 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5722 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5725 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5728 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5731 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5734 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5737 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5740 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5743 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_19.tablemult.:5746 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5852 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5855 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5858 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5861 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5864 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5867 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5870 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5873 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5876 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5879 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5882 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5885 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5888 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5891 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5894 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5897 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5900 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5903 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5906 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5909 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5912 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5915 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5918 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5921 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5924 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5927 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5930 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5933 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5936 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5939 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_20.tablemult.:5942 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6048 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6051 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6054 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6057 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6060 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6063 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6066 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6069 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6072 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6075 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6078 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6081 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6084 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6087 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6090 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6093 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6096 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6099 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6102 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6105 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6108 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6111 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6114 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6117 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6120 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6123 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6126 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6129 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6132 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6135 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_21.tablemult.:6138 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6244 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6247 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6250 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6253 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6256 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6259 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6262 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6265 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6268 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6271 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6274 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6277 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6280 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6283 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6286 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6289 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6292 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6295 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6298 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6301 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6304 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6307 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6310 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6313 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6316 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6319 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6322 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6325 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6328 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6331 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_22.tablemult.:6334 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6440 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6443 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6446 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6449 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6452 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6455 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6458 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6461 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6464 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6467 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6470 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6473 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6476 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6479 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6482 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6485 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6488 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6491 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6494 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6497 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6500 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6503 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6506 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6509 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6512 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6515 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6518 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6521 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6524 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6527 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_23.tablemult.:6530 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6636 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6639 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6642 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6645 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6648 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6651 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6654 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6657 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6660 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6663 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6666 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6669 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6672 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6675 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6678 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6681 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6684 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6687 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6690 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6693 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6696 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6699 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6702 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6705 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6708 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6711 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6714 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6717 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6720 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6723 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_24.tablemult.:6726 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6832 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6835 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6838 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6841 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6844 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6847 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6850 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6853 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6856 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6859 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6862 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6865 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6868 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6871 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6874 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6877 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6880 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6883 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6886 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6889 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6892 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6895 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6898 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6901 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6904 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6907 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6910 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6913 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6916 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6919 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_25.tablemult.:6922 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7028 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7031 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7034 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7037 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7040 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7043 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7046 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7049 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7052 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7055 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7058 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7061 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7064 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7067 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7070 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7073 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7076 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7079 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7082 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7085 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7088 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7091 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7094 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7097 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7100 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7103 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7106 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7109 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7112 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7115 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_26.tablemult.:7118 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid140.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid140.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid140.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid140.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid140.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid140.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid140.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid142.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid142.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid142.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid142.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid142.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid142.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid142.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid144.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid144.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid144.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid144.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid144.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid144.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid144.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid146.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid146.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid146.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid146.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid146.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid146.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid146.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid148.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid148.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid148.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid148.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid148.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid148.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid148.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid150.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid150.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid150.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid150.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid150.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid150.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid150.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid152.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid152.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid152.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid152.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid152.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid152.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid152.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid154.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid154.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid154.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid154.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid154.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid154.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid154.:2658 ($eq). Removed top 1 bits (of 2) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid158.:2758 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid160.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid160.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid160.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid160.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid160.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid160.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid160.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid160.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid160.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid160.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid160.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid160.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid160.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid160.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid160.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid162.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid162.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid162.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid162.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid162.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid162.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid162.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid162.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid162.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid162.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid162.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid162.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid162.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid162.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid162.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid164.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid164.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid164.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid164.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid164.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid164.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid164.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid164.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid164.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid164.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid164.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid164.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid164.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid164.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid164.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid166.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid166.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid166.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid166.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid166.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid166.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid166.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid166.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid166.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid166.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid166.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid166.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid166.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid166.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid166.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid168.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid168.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid168.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid168.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid168.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid168.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid168.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid168.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid168.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid168.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid168.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid168.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid168.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid168.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid168.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid170.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid170.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid170.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid170.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid170.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid170.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid170.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid170.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid170.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid170.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid170.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid170.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid170.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid170.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid170.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid172.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid172.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid172.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid172.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid172.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid172.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid172.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid172.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid172.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid172.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid172.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid172.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid172.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid172.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid172.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid174.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid174.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid174.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid174.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid174.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid174.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid174.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid174.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid174.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid174.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid174.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid174.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid174.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid174.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid174.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid176.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid176.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid176.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid176.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid176.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid176.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid176.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid176.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid176.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid176.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid176.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid176.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid176.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid176.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid176.:2656 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid178.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid178.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid178.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid178.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid178.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid178.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid178.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid180.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid180.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid180.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid180.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid180.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid180.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid180.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid182.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid182.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid182.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid182.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid182.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid182.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid182.:2658 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid184.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid184.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid184.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid184.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid184.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid184.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid184.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid184.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid184.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid184.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid184.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid184.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid184.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid184.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid184.:2656 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid186.:2765 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid186.:2758 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid186.:2756 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid190.:2842 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid190.:2826 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid190.:2823 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid190.:2820 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid190.:2818 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid190.:2811 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid190.:2808 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid190.:2805 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid190.:2802 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid190.:2799 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid190.:2797 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid190.:2793 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid190.:2790 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid190.:2787 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid190.:2785 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid192.:2765 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid192.:2758 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid192.:2756 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid196.:3008 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid196.:2956 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid196.:2953 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid196.:2950 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid196.:2948 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid196.:2917 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid196.:2914 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid196.:2911 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid196.:2908 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid196.:2905 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid196.:2903 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid196.:2893 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid196.:2890 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid196.:2887 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid196.:2885 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid198.:2956 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid198.:2917 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid198.:2914 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid198.:2908 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid198.:2893 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid198.:2890 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid198.:2887 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid200.:2680 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid200.:2670 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid200.:2667 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid200.:2665 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid200.:2661 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid200.:2658 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid200.:2656 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:3053 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:3019 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:3016 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:3013 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:3010 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:3008 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2974 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2971 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2968 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2965 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2962 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2959 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2956 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2953 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2950 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2948 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2929 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2926 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2923 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2920 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2917 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2914 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2911 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2908 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2905 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2903 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2896 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2893 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2890 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2887 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid202.:2885 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid204.:2956 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid204.:2917 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid204.:2914 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid204.:2908 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid204.:2893 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid204.:2890 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid204.:2887 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid206.:2765 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid206.:2758 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid206.:2756 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:3053 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:3019 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:3016 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:3013 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:3010 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:3008 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2974 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2971 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2968 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2965 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2962 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2959 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2956 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2953 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2950 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2948 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2929 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2926 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2923 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2920 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2917 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2914 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2911 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2908 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2905 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2903 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2896 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2893 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2890 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2887 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid208.:2885 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid210.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid210.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid210.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid210.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid210.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid210.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid210.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid210.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid210.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid210.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid210.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid210.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid210.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid210.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid210.:2656 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:3053 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:3019 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:3016 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:3013 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:3010 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:3008 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2974 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2971 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2968 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2965 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2962 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2959 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2956 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2953 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2950 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2948 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2929 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2926 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2923 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2920 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2917 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2914 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2911 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2908 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2905 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2903 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2896 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2893 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2890 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2887 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid212.:2885 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:3053 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:3019 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:3016 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:3013 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:3010 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:3008 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2974 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2971 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2968 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2965 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2962 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2959 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2956 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2953 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2950 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2948 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2929 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2926 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2923 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2920 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2917 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2914 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2911 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2908 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2905 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2903 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2896 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2893 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2890 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2887 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid214.:2885 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid216.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid216.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid216.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid216.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid216.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid216.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid216.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid216.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid216.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid216.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid216.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid216.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid216.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid216.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid216.:2656 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:3053 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:3019 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:3016 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:3013 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:3010 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:3008 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2974 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2971 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2968 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2965 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2962 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2959 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2956 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2953 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2950 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2948 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2929 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2926 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2923 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2920 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2917 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2914 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2911 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2908 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2905 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2903 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2896 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2893 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2890 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2887 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid218.:2885 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:3053 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:3019 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:3016 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:3013 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:3010 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:3008 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2974 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2971 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2968 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2965 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2962 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2959 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2956 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2953 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2950 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2948 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2929 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2926 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2923 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2920 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2917 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2914 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2911 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2908 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2905 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2903 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2896 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2893 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2890 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2887 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid220.:2885 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid222.:2765 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid222.:2758 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid222.:2756 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:3053 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:3019 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:3016 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:3013 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:3010 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:3008 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2974 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2971 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2968 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2965 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2962 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2959 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2956 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2953 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2950 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2948 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2929 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2926 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2923 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2920 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2917 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2914 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2911 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2908 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2905 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2903 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2896 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2893 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2890 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2887 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid224.:2885 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:3053 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:3019 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:3016 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:3013 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:3010 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:3008 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2974 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2971 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2968 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2965 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2962 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2959 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2956 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2953 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2950 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2948 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2929 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2926 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2923 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2920 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2917 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2914 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2911 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2908 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2905 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2903 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2896 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2893 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2890 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2887 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid226.:2885 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:3053 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:3019 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:3016 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:3013 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:3010 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:3008 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2974 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2971 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2968 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2965 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2962 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2959 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2956 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2953 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2950 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2948 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2929 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2926 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2923 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2920 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2917 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2914 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2911 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2908 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2905 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2903 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2896 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2893 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2890 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2887 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid228.:2885 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:3053 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:3019 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:3016 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:3013 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:3010 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:3008 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2974 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2971 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2968 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2965 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2962 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2959 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2956 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2953 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2950 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2948 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2929 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2926 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2923 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2920 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2917 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2914 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2911 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2908 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2905 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2903 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2896 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2893 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2890 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2887 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_6_3_freq500_uid195_uid230.:2885 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid232.:2842 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid232.:2826 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid232.:2823 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid232.:2820 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid232.:2818 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid232.:2811 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid232.:2808 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid232.:2805 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid232.:2802 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid232.:2799 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid232.:2797 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid232.:2793 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid232.:2790 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid232.:2787 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid232.:2785 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid234.:2818 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid234.:2802 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid234.:2799 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid234.:2797 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid234.:2790 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid234.:2787 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid234.:2785 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid236.:2765 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid236.:2758 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid236.:2756 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid238.:2818 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid238.:2802 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid238.:2799 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid238.:2797 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid238.:2790 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid238.:2787 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid238.:2785 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid240.:2765 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid240.:2758 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid240.:2756 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid242.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid242.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid242.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid242.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid242.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid242.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid242.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid242.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid242.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid242.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid242.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid242.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid242.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid242.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid242.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid244.:2842 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid244.:2826 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid244.:2823 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid244.:2820 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid244.:2818 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid244.:2811 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid244.:2808 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid244.:2805 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid244.:2802 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid244.:2799 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid244.:2797 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid244.:2793 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid244.:2790 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid244.:2787 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid244.:2785 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid246.:2842 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid246.:2826 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid246.:2823 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid246.:2820 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid246.:2818 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid246.:2811 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid246.:2808 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid246.:2805 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid246.:2802 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid246.:2799 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid246.:2797 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid246.:2793 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid246.:2790 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid246.:2787 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid246.:2785 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid248.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid248.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid248.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid248.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid248.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid248.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid248.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid248.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid248.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid248.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid248.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid248.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid248.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid248.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid248.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid250.:2842 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid250.:2826 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid250.:2823 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid250.:2820 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid250.:2818 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid250.:2811 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid250.:2808 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid250.:2805 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid250.:2802 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid250.:2799 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid250.:2797 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid250.:2793 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid250.:2790 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid250.:2787 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid250.:2785 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid252.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid252.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid252.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid252.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid252.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid252.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid252.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid252.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid252.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid252.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid252.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid252.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid252.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid252.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid252.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid254.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid254.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid254.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid254.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid254.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid254.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid254.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid254.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid254.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid254.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid254.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid254.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid254.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid254.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid254.:2656 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid256.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid256.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid256.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid256.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid256.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid256.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid256.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid258.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid258.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid258.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid258.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid258.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid258.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid258.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid260.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid260.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid260.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid260.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid260.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid260.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid260.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid262.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid262.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid262.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid262.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid262.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid262.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid262.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid264.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid264.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid264.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid264.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid264.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid264.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid264.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid266.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid266.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid266.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid266.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid266.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid266.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid266.:2658 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid268.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid268.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid268.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid270.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid270.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid270.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid272.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid272.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid272.:2790 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid274.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid274.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid274.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid274.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid274.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid274.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid274.:2658 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid276.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid276.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid276.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid276.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid276.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid276.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid276.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid276.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid276.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid276.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid276.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid276.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid276.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid276.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid276.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid278.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid278.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid278.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid278.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid278.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid278.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid278.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid278.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid278.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid278.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid278.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid278.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid278.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid278.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid278.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid280.:2842 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid280.:2826 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid280.:2823 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid280.:2820 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid280.:2818 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid280.:2811 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid280.:2808 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid280.:2805 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid280.:2802 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid280.:2799 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid280.:2797 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid280.:2793 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid280.:2790 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid280.:2787 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid280.:2785 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid282.:2842 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid282.:2826 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid282.:2823 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid282.:2820 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid282.:2818 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid282.:2811 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid282.:2808 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid282.:2805 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid282.:2802 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid282.:2799 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid282.:2797 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid282.:2793 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid282.:2790 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid282.:2787 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid282.:2785 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid284.:2842 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid284.:2826 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid284.:2823 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid284.:2820 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid284.:2818 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid284.:2811 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid284.:2808 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid284.:2805 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid284.:2802 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid284.:2799 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid284.:2797 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid284.:2793 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid284.:2790 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid284.:2787 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid284.:2785 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid286.:2842 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid286.:2826 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid286.:2823 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid286.:2820 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid286.:2818 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid286.:2811 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid286.:2808 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid286.:2805 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid286.:2802 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid286.:2799 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid286.:2797 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid286.:2793 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid286.:2790 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid286.:2787 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid286.:2785 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid288.:2842 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid288.:2826 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid288.:2823 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid288.:2820 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid288.:2818 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid288.:2811 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid288.:2808 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid288.:2805 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid288.:2802 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid288.:2799 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid288.:2797 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid288.:2793 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid288.:2790 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid288.:2787 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid288.:2785 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid290.:2765 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid290.:2758 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid290.:2756 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid292.:2842 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid292.:2826 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid292.:2823 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid292.:2820 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid292.:2818 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid292.:2811 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid292.:2808 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid292.:2805 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid292.:2802 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid292.:2799 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid292.:2797 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid292.:2793 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid292.:2790 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid292.:2787 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid292.:2785 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid294.:2842 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid294.:2826 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid294.:2823 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid294.:2820 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid294.:2818 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid294.:2811 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid294.:2808 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid294.:2805 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid294.:2802 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid294.:2799 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid294.:2797 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid294.:2793 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid294.:2790 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid294.:2787 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid294.:2785 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid296.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid296.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid296.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid296.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid296.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid296.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid296.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid296.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid296.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid296.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid296.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid296.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid296.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid296.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid296.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid298.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid298.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid298.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid298.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid298.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid298.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid298.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid298.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid298.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid298.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid298.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid298.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid298.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid298.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid298.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid300.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid300.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid300.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid300.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid300.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid300.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid300.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid300.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid300.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid300.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid300.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid300.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid300.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid300.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid300.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid302.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid302.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid302.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid302.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid302.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid302.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid302.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid302.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid302.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid302.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid302.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid302.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid302.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid302.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid302.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid304.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid304.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid304.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid304.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid304.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid304.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid304.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid304.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid304.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid304.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid304.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid304.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid304.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid304.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid304.:2656 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid306.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid306.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid306.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid306.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid306.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid306.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid306.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid308.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid308.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid308.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid308.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid308.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid308.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid308.:2658 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid310.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid310.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid310.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid310.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid310.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid310.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid310.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid310.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid310.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid310.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid310.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid310.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid310.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid310.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid310.:2656 ($eq). Removed top 1 bits (of 2) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_3_2_freq500_uid157_uid312.:2758 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid314.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid314.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid314.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid314.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid314.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid314.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid314.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid314.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid314.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid314.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid314.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid314.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid314.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid314.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid314.:2656 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid316.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid316.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid316.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid316.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid316.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid316.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid316.:2658 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid318.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid318.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid318.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid320.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid320.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid320.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid322.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid322.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid322.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid324.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid324.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid324.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid326.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid326.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid326.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid328.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid328.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid328.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid330.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid330.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid330.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid332.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid332.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid332.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid334.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid334.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid334.:2790 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid336.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid336.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid336.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid336.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid336.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid336.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid336.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid338.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid338.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid338.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid338.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid338.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid338.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid338.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid340.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid340.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid340.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid340.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid340.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid340.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid340.:2658 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid342.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid342.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid342.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid342.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid342.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid342.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid342.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid342.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid342.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid342.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid342.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid342.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid342.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid342.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid342.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid344.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid344.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid344.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid344.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid344.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid344.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid344.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid344.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid344.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid344.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid344.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid344.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid344.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid344.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid344.:2656 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid346.:2842 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid346.:2826 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid346.:2823 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid346.:2820 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid346.:2818 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid346.:2811 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid346.:2808 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid346.:2805 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid346.:2802 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid346.:2799 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid346.:2797 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid346.:2793 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid346.:2790 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid346.:2787 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid346.:2785 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid348.:2722 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid348.:2706 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid348.:2703 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid348.:2701 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid348.:2688 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid348.:2685 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid348.:2682 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid348.:2680 ($eq). Removed top 1 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid348.:2673 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid348.:2670 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid348.:2667 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid348.:2665 ($eq). Removed top 2 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid348.:2661 ($eq). Removed top 3 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid348.:2658 ($eq). Removed top 4 bits (of 5) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid348.:2656 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid350.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid350.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid350.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid350.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid350.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid350.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid350.:2658 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid352.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid352.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid352.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid352.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid352.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid352.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid352.:2658 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid354.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid354.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid354.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid356.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid356.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid356.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid358.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid358.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid358.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid360.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid360.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid360.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid362.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid362.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid362.:2790 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid364.:2706 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid364.:2688 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid364.:2685 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid364.:2673 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid364.:2670 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid364.:2661 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid364.:2658 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid366.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid366.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid366.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid368.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid368.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid368.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid370.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid370.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid370.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid372.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid372.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid372.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid374.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid374.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid374.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid376.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid376.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid376.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid378.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid378.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid378.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid380.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid380.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid380.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid382.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid382.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid382.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid384.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid384.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid384.:2790 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid386.:2811 ($eq). Removed top 1 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid386.:2793 ($eq). Removed top 2 bits (of 3) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.compressor_14_3_freq500_uid189_uid386.:2790 ($eq). Removed top 1 bits (of 10) from port A of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.bitheapfinaladd_bh7.:3207 ($add). Removed top 9 bits (of 10) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.bitheapfinaladd_bh7.:3207 ($add). Removed top 1 bits (of 10) from port Y of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.bitheapfinaladd_bh7.:3207 ($add). Removed top 11 bits (of 12) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.bitheapfinaladd_bh7.:3196 ($add). Removed top 1 bits (of 12) from port A of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.bitheapfinaladd_bh7.:3194 ($add). Removed top 2 bits (of 12) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.bitheapfinaladd_bh7.:3194 ($add). Removed top 11 bits (of 12) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.bitheapfinaladd_bh7.:3185 ($add). Removed top 1 bits (of 12) from port A of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.bitheapfinaladd_bh7.:3183 ($add). Removed top 2 bits (of 12) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.bitheapfinaladd_bh7.:3183 ($add). Removed top 11 bits (of 12) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.bitheapfinaladd_bh7.:3174 ($add). Removed top 1 bits (of 12) from port A of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.bitheapfinaladd_bh7.:3172 ($add). Removed top 2 bits (of 12) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.bitheapfinaladd_bh7.:3172 ($add). Removed top 11 bits (of 12) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.bitheapfinaladd_bh7.:3163 ($add). Removed top 1 bits (of 12) from port A of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.bitheapfinaladd_bh7.:3161 ($add). Removed top 2 bits (of 12) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.bitheapfinaladd_bh7.:3161 ($add). Removed top 1 bits (of 72) from FF cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.:181 ($dff). Removed top 1 bits (of 2) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.:138 ($eq). Removed top 9 bits (of 10) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.:105 ($add). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.:92 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.:89 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.:85 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.:82 ($eq). Removed top 17 bits (of 41) from port A of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_0.:2517 ($mul). Removed top 24 bits (of 41) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.significandmultiplication.t8_tile_0.:2517 ($mul). Removed top 3 bits (of 10) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.:65 ($sub). Removed top 2 bits (of 10) from port A of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.:63 ($add). Removed top 2 bits (of 10) from port B of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.:63 ($add). Removed top 1 bits (of 10) from port Y of cell top_flopoco_mul_we8_wf35_zynq7000_native_f500.u_dut.:63 ($add). 2.16. Executing PEEPOPT pass (run peephole optimizers). 2.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. 2.18. Executing SHARE pass (SAT-based resource sharing). 2.19. Executing TECHMAP pass (map to technology primitives). 2.19.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 2.19.2. Continuing TECHMAP pass. No more expansions possible. 2.20. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Removed 0 unused cells and 15 unused wires. 2.22. Executing TECHMAP pass (map to technology primitives). 2.22.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 2.22.2. Continuing TECHMAP pass. Using template $paramod$d35279ebcd7e33461b6b6e1e57c525aa6ce5e31a\_80_mul for cells of type $mul. Using template $paramod$3e5ed51ec64a1521336d6a6183035577ec6541a2\_80_mul for cells of type $mul. Using template $paramod$6faeec65ba76cc5a49de556987790b31f0bf76e5\_80_mul for cells of type $__mul. Using template $paramod$7ad493862d67ec9b3d22282c42f544cd2ef4f196\_80_mul for cells of type $__mul. Using template $paramod$7d6ed1c768e7a930de2ac607f8ecf4f7587f47ba\_80_mul for cells of type $__mul. Using template $paramod$b3a00f966456c73946c43b4e56a53f61cc75f64e\_80_mul for cells of type $__mul. No more expansions possible. 2.23. Executing TECHMAP pass (map to technology primitives). 2.23.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. Generating RTLIL representation for module `$__MUL18X18'. Successfully finished Verilog frontend. 2.23.2. Continuing TECHMAP pass. Using template $paramod$1655538e8d6189641ab1cf369460d2906d76490d$__MUL18X18 for cells of type $__MUL18X18. Using template $paramod$fe40a425568926b0164c524e57bf5a0b343ac3df$__MUL18X18 for cells of type $__MUL18X18. Using template $paramod$defc2ba75df36033a101f83fe9d84132170e679f$__MUL18X18 for cells of type $__MUL18X18. Using template $paramod$9d7a499a58894ca056949ac2ac48840a19fd6e4d$__MUL18X18 for cells of type $__MUL18X18. No more expansions possible. 2.24. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top_flopoco_mul_we8_wf35_zynq7000_native_f500: creating $macc model for $techmap\u_dut.significandmultiplication.t8_tile_0.:2517.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$3228 ($add). creating $macc model for $techmap\u_dut.significandmultiplication.t8_tile_2.dsp0_0.:3281.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$3232 ($add). creating $macc model for $techmap\u_dut.significandmultiplication.t8_tile_1.:2521.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$3228 ($add). creating $macc model for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3196 ($add). creating $macc model for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3194 ($add). creating $macc model for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3207 ($add). creating $macc model for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3185 ($add). creating $macc model for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3161 ($add). creating $macc model for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3163 ($add). creating $macc model for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3172 ($add). creating $macc model for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3174 ($add). creating $macc model for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3183 ($add). creating $macc model for u_dut.:105 ($add). creating $macc model for u_dut.:65 ($sub). creating $macc model for u_dut.:63 ($add). creating $macc model for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3150 ($add). creating $macc model for u_dut.roundingadder.:2423 ($add). creating $macc model for u_dut.roundingadder.:2412 ($add). creating $macc model for u_dut.roundingadder.:2401 ($add). creating $macc model for u_dut.roundingadder.:2390 ($add). creating $macc model for u_dut.roundingadder.:2379 ($add). merging $macc model for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3172 into u_dut.significandmultiplication.bitheapfinaladd_bh7.:3174. merging $macc model for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3161 into u_dut.significandmultiplication.bitheapfinaladd_bh7.:3163. merging $macc model for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3183 into u_dut.significandmultiplication.bitheapfinaladd_bh7.:3185. merging $macc model for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3194 into u_dut.significandmultiplication.bitheapfinaladd_bh7.:3196. creating $alu model for $macc u_dut.roundingadder.:2423. creating $alu model for $macc u_dut.significandmultiplication.bitheapfinaladd_bh7.:3150. creating $alu model for $macc u_dut.:63. creating $alu model for $macc u_dut.:65. creating $alu model for $macc u_dut.:105. creating $alu model for $macc u_dut.roundingadder.:2390. creating $alu model for $macc u_dut.significandmultiplication.bitheapfinaladd_bh7.:3174. creating $alu model for $macc u_dut.roundingadder.:2412. creating $alu model for $macc u_dut.significandmultiplication.bitheapfinaladd_bh7.:3163. creating $alu model for $macc u_dut.roundingadder.:2401. creating $alu model for $macc u_dut.significandmultiplication.bitheapfinaladd_bh7.:3185. creating $alu model for $macc u_dut.significandmultiplication.bitheapfinaladd_bh7.:3207. creating $alu model for $macc u_dut.roundingadder.:2379. creating $alu model for $macc u_dut.significandmultiplication.bitheapfinaladd_bh7.:3196. creating $alu model for $macc $techmap\u_dut.significandmultiplication.t8_tile_1.:2521.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$3228. creating $alu model for $macc $techmap\u_dut.significandmultiplication.t8_tile_2.dsp0_0.:3281.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$3232. creating $alu model for $macc $techmap\u_dut.significandmultiplication.t8_tile_0.:2517.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$3228. creating $alu cell for $techmap\u_dut.significandmultiplication.t8_tile_0.:2517.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$3228: $auto$alumacc.cc:512:replace_alu$3245 creating $alu cell for $techmap\u_dut.significandmultiplication.t8_tile_2.dsp0_0.:3281.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$3232: $auto$alumacc.cc:512:replace_alu$3248 creating $alu cell for $techmap\u_dut.significandmultiplication.t8_tile_1.:2521.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$3228: $auto$alumacc.cc:512:replace_alu$3251 creating $alu cell for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3196: $auto$alumacc.cc:512:replace_alu$3254 creating $alu cell for u_dut.roundingadder.:2379: $auto$alumacc.cc:512:replace_alu$3257 creating $alu cell for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3207: $auto$alumacc.cc:512:replace_alu$3260 creating $alu cell for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3185: $auto$alumacc.cc:512:replace_alu$3263 creating $alu cell for u_dut.roundingadder.:2401: $auto$alumacc.cc:512:replace_alu$3266 creating $alu cell for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3163: $auto$alumacc.cc:512:replace_alu$3269 creating $alu cell for u_dut.roundingadder.:2412: $auto$alumacc.cc:512:replace_alu$3272 creating $alu cell for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3174: $auto$alumacc.cc:512:replace_alu$3275 creating $alu cell for u_dut.roundingadder.:2390: $auto$alumacc.cc:512:replace_alu$3278 creating $alu cell for u_dut.:105: $auto$alumacc.cc:512:replace_alu$3281 creating $alu cell for u_dut.:65: $auto$alumacc.cc:512:replace_alu$3284 creating $alu cell for u_dut.:63: $auto$alumacc.cc:512:replace_alu$3287 creating $alu cell for u_dut.significandmultiplication.bitheapfinaladd_bh7.:3150: $auto$alumacc.cc:512:replace_alu$3290 creating $alu cell for u_dut.roundingadder.:2423: $auto$alumacc.cc:512:replace_alu$3293 created 17 $alu and 0 $macc cells. 2.25. Executing OPT pass (performing simple optimizations). 2.25.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.25.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6970 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 7/8 on $pmux \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_uid266.:2749. Removed 1 multiplexer ports. 2.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.25.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6970 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.25.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 9 on u_dut.:173 ($dff) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Removed 4 unused cells and 52 unused wires. 2.25.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.25.9. Rerunning OPT passes. (Maybe there is more to do..) 2.25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.25.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6966 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.25.13. Executing OPT_DFF pass (perform DFF optimizations). 2.25.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. 2.25.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.25.16. Finished fast OPT passes. (There is nothing left to do.) 2.26. Executing MEMORY pass. 2.26.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 2.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 2.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 2.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 2.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 2.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. 2.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 2.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. 2.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2.27. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. 2.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). 2.29. Executing TECHMAP pass (map to technology primitives). 2.29.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 2.29.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v' to AST representation. Generating RTLIL representation for module `$__DP16KD_'. Generating RTLIL representation for module `$__PDPW16KD_'. Successfully finished Verilog frontend. 2.29.3. Continuing TECHMAP pass. No more expansions possible. 2.30. Executing OPT pass (performing simple optimizations). 2.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6965 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.30.3. Executing OPT_DFF pass (perform DFF optimizations). 2.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Removed 466 unused cells and 467 unused wires. 2.30.5. Finished fast OPT passes. 2.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 2.32. Executing OPT pass (performing simple optimizations). 2.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6499 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Consolidated identical input bits for $mux cell \u_dut.:109: Old ports: A={ \u_dut.sigprod_d1 [69:0] 2'00 }, B={ \u_dut.sigprod_d1 [70:0] 1'0 }, Y=\u_dut.sigprodext New ports: A={ \u_dut.sigprod_d1 [69:0] 1'0 }, B=\u_dut.sigprod_d1 [70:0], Y=\u_dut.sigprodext [71:1] New connections: \u_dut.sigprodext [0] = 1'0 Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 1 changes. 2.32.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6499 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.32.6. Executing OPT_DFF pass (perform DFF optimizations). 2.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. 2.32.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.32.9. Rerunning OPT passes. (Maybe there is more to do..) 2.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500. Performed a total of 0 changes. 2.32.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 6499 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.32.13. Executing OPT_DFF pass (perform DFF optimizations). 2.32.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. 2.32.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.32.16. Finished fast OPT passes. (There is nothing left to do.) 2.33. Executing TECHMAP pass (map to technology primitives). 2.33.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 2.33.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. Generating RTLIL representation for module `\_80_ccu2c_alu'. Successfully finished Verilog frontend. 2.33.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $dff. Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu. Using template $paramod$546f3f62de618651dd3a8b3f9e661fb34b30a603\_80_ccu2c_alu for cells of type $alu. Using template $paramod$4ccbe221165818e15f326ddee3d1183c7924e12f\_80_ccu2c_alu for cells of type $alu. Using template $paramod$94b2d39efe5cee36393111e3a7a149e3dba7e8c5\_80_ccu2c_alu for cells of type $alu. Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ccu2c_alu for cells of type $alu. Using template $paramod$754650b284649a026620fc6856e5b6886cbfe794\_80_ccu2c_alu for cells of type $alu. Using template $paramod$92a1f7a016bf58d33db5a47145e66dde1cbc3210\_80_ccu2c_alu for cells of type $alu. Using template $paramod$9503ccbdaa0d43eea34db1a74a4be1091d99b327\_80_ccu2c_alu for cells of type $alu. Using template $paramod$448756c9a9dfaa49080ce4b90c6cc182883e181f\_80_ccu2c_alu for cells of type $alu. Using template $paramod$12350b8c8422a70d10b7db4eaae1202a7148b784\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $pmux. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $xor. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000001 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu. Using extmapper simplemap for cells of type $pos. Using extmapper simplemap for cells of type $logic_or. Using extmapper simplemap for cells of type $logic_and. No more expansions possible. 2.34. Executing OPT pass (performing simple optimizations). 2.34.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.34.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 35249 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 24288 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 18415 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 16783 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 18466 cells. 2.34.3. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:337:slice$4137 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$84902, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.y_0_d1 [10], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6108 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$34547, Q = \u_dut.significandmultiplication.bh7_w0_0_d1, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6109 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$34627, Q = \u_dut.significandmultiplication.bh7_w1_0_d1, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6110 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$34707, Q = \u_dut.significandmultiplication.bh7_w2_0_d1, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6111 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$44012, Q = \u_dut.significandmultiplication.bh7_w3_3_d1, rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6112 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$44782, Q = \u_dut.significandmultiplication.bh7_w7_5_d1, rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6113 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$45519, Q = \u_dut.significandmultiplication.bh7_w9_8_d1, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6114 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$51848, Q = \u_dut.significandmultiplication.bh7_w16_11_d1, rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6115 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$56705, Q = \u_dut.significandmultiplication.bh7_w19_8_d1, rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6116 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$59441, Q = \u_dut.significandmultiplication.bh7_w21_6_d1, rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6117 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$62177, Q = \u_dut.significandmultiplication.bh7_w23_5_d1, rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6118 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$68032, Q = \u_dut.significandmultiplication.bh7_w39_5_d1, rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6119 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$69606, Q = \u_dut.significandmultiplication.bh7_w52_3_d1, rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6122 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$70028, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid274_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6125 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$70328, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid276_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6128 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$70973, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid278_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6131 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$71608, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid280_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6134 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$72244, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid282_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6137 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$72880, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid284_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6140 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$73516, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid286_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6143 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$74152, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid288_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6145 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$74743, Q = \u_dut.significandmultiplication.compressor_3_2_freq500_uid157_bh7_uid290_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6148 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$74896, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid292_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6151 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$75532, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid294_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6154 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$76178, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid296_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6157 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$76823, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid298_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6160 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$77468, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid300_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6163 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$78113, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid302_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6166 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$78758, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid304_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6169 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$79393, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid306_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6172 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$79683, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid308_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6175 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$79983, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid310_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6180 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$80665, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid314_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6183 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$81300, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid316_out0 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6219 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$82721, Q = \u_dut.significandmultiplication.tmp_bitheapresult_bh7_7_d1 [7], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$89239 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$89611, Q = \u_dut.exc_d1 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4148 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$85500, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_0_d1 [10], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4159 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$86981, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_1_d1 [10], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4165 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$86967, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.y_1_d1 [9], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4176 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$87783, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_2_d1 [10], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4192 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$88423, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_3_d1 [10], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4129 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$82742, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.y_0_d1 [0], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4130 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$83032, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.y_0_d1 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4131 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$83322, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.y_0_d1 [4], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4132 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$83598, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.y_0_d1 [5], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4133 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$83622, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.y_0_d1 [6], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4134 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$84243, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.y_0_d1 [7], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4135 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$84267, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.y_0_d1 [8], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4136 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$84881, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.y_0_d1 [9], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4138 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$82990, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_0_d1 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4139 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$83011, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_0_d1 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4140 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$83280, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_0_d1 [2], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4141 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$83301, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_0_d1 [3], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4142 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$83574, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_0_d1 [4], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4144 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$84219, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_0_d1 [6], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4146 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$84860, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_0_d1 [8], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4150 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$86141, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_1_d1 [1], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4151 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$86162, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_1_d1 [2], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4152 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$86431, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_1_d1 [3], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4153 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$86452, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_1_d1 [4], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4154 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$86473, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_1_d1 [5], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4155 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$86725, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_1_d1 [6], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4157 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$86853, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_1_d1 [8], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4160 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$85524, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.y_1_d1 [0], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4161 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$85548, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.y_1_d1 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4162 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$86183, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.y_1_d1 [3], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4163 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$86711, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.y_1_d1 [5], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4164 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$86839, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.y_1_d1 [7], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4167 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$87109, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_2_d1 [1], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4168 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$87223, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_2_d1 [2], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4169 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$87237, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_2_d1 [3], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4170 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$87361, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_2_d1 [4], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4171 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$87382, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_2_d1 [5], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4173 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$87641, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_2_d1 [7], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4174 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$87655, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_2_d1 [8], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4175 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$87769, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_2_d1 [9], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4177 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$87095, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.y_2_d1 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4180 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$87403, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.y_2_d1 [6], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$4183 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$87897, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_3_d1 [1], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4184 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$87911, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_3_d1 [2], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4185 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$88025, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_3_d1 [3], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4186 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$88039, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_3_d1 [4], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4187 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$88153, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_3_d1 [5], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4188 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$88167, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_3_d1 [6], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4189 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$88281, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_3_d1 [7], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4190 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$88295, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_3_d1 [8], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4191 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$88409, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_3_d1 [9], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4198 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$88537, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_4_d1 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4199 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$88551, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_4_d1 [1], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4201 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$88665, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_4_d1 [3], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4202 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$88679, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_4_d1 [4], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4203 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$88793, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_4_d1 [5], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4204 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$88807, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_4_d1 [6], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4205 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$88921, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_4_d1 [7], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$4206 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$88935, Q = \u_dut.significandmultiplication.bitheapfinaladd_bh7.x_4_d1 [8], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6120 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$69986, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid274_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6121 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$70007, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid274_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6123 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$70280, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid276_out0 [0], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6124 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$70304, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid276_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6126 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$70925, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid278_out0 [0], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6127 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$70949, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid278_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6129 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$71566, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid280_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6130 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$71587, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid280_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6132 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$72202, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid282_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6133 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$72223, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid282_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6135 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$72838, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid284_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6136 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$72859, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid284_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6138 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$73474, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid286_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6139 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$73495, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid286_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6141 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$74110, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid288_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6142 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$74131, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid288_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6144 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$74732, Q = \u_dut.significandmultiplication.compressor_3_2_freq500_uid157_bh7_uid290_out0 [0], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6146 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$74854, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid292_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6147 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$74875, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid292_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6149 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$75490, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid294_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6150 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$75511, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid294_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6152 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$76130, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid296_out0 [0], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6153 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$76154, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid296_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6155 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$76775, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid298_out0 [0], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6156 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$76799, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid298_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6158 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$77420, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid300_out0 [0], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6159 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$77444, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid300_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6161 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$78065, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid302_out0 [0], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6162 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$78089, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid302_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6164 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$78710, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid304_out0 [0], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6165 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$78734, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid304_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6167 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$79351, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid306_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6168 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$79372, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid306_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6170 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$79641, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid308_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6171 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$79662, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid308_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6173 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$79935, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid310_out0 [0], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6174 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$79959, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid310_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6176 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$80556, Q = \u_dut.significandmultiplication.compressor_3_2_freq500_uid157_bh7_uid312_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6178 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$80617, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid314_out0 [0], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6179 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$80641, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid314_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6181 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$81258, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid316_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6182 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$81279, Q = \u_dut.significandmultiplication.compressor_23_3_freq500_uid139_bh7_uid316_out0 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$6184 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$81538, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid318_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6185 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$81552, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid318_out0 [1], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6187 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$81666, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid320_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6188 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$81680, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid320_out0 [1], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6190 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$81794, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid322_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6191 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$81808, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid322_out0 [1], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6193 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$81922, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid324_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6194 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$81936, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid324_out0 [1], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6196 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$82050, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid326_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6197 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$82064, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid326_out0 [1], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6199 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$82178, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid328_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6200 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$82192, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid328_out0 [1], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6202 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$82306, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid330_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6203 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$82320, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid330_out0 [1], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6205 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$82434, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid332_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6206 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$82448, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid332_out0 [1], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6208 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$82562, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid334_out0 [0], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6209 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$82576, Q = \u_dut.significandmultiplication.compressor_14_3_freq500_uid189_bh7_uid334_out0 [1], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$6218 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$82700, Q = \u_dut.significandmultiplication.tmp_bitheapresult_bh7_7_d1 [6], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$89238 ($_DFF_P_) from module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (D = $auto$simplemap.cc:189:logic_reduce$89600, Q = \u_dut.exc_d1 [0], rval = 1'1). 2.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Removed 651 unused cells and 27853 unused wires. 2.34.5. Rerunning OPT passes. (Removed registers in this run.) 2.34.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.34.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 16132 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 0 cells. 2.34.8. Executing OPT_DFF pass (perform DFF optimizations). 2.34.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. 2.34.10. Finished fast OPT passes. 2.35. Executing ABC pass (technology mapping using ABC). 2.35.1. Summary of detected clock domains: 177 cells in clk={ }, en={ }, arst={ }, srst={ } 190 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$34468 302 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$43989 463 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$44741 408 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$45484 694 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$51786 718 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$56643 523 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$59379 471 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$62115 318 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$67991 129 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$rtlil.cc:3492:NotGate$92325 19 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$86954 52 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$82970 52 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$83260 83 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$83551 83 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$84196 82 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$84840 51 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$86411 82 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$85477 51 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$86121 19 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$86698 19 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$86826 19 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$87210 19 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$87628 19 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$87756 19 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$87082 51 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$87341 19 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$87884 19 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$88012 19 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$88140 19 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$88268 19 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$88396 19 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$88524 19 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$88652 19 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$88780 19 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$88908 90 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$69966 297 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$70257 229 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$70902 269 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$71546 581 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$72182 460 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$72818 404 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$73454 492 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$74090 521 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$74722 384 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$74834 441 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$75470 353 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$76107 390 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$76752 313 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$77397 274 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$78042 281 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$78687 436 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$79331 340 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$79621 322 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$79912 615 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$80550 211 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$80594 178 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$81238 113 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$81525 227 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$81653 227 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$81781 218 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$81909 196 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$82037 67 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$82165 65 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$82293 122 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$82421 48 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$82549 52 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$82680 22 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$89590 1610 cells in clk=\clk, en={ }, arst={ }, srst={ } 2.35.2. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 2.35.3. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$34468 2.35.3.1. Executed ABC. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 2.35.4. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$43989 2.35.5. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$44741 2.35.6. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$45484 2.35.7. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$51786 2.35.8. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$56643 2.35.9. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$59379 2.35.10. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$62115 2.35.11. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$67991 2.35.12. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$rtlil.cc:3492:NotGate$92325 2.35.13. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$86954 2.35.14. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$82970 2.35.15. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$83260 2.35.16. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$83551 2.35.17. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$84196 2.35.17.1. Executed ABC. Extracted 190 gates and 205 wires to a netlist network with 15 inputs and 13 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.17.2. Re-integrating ABC results. ABC RESULTS: AND cells: 53 ABC RESULTS: ANDNOT cells: 5 ABC RESULTS: BUF cells: 3 ABC RESULTS: DFF cells: 3 ABC RESULTS: NAND cells: 12 ABC RESULTS: NOR cells: 5 ABC RESULTS: NOT cells: 4 ABC RESULTS: OR cells: 51 ABC RESULTS: ORNOT cells: 4 ABC RESULTS: internal signals: 177 ABC RESULTS: input signals: 15 ABC RESULTS: output signals: 13 Removing temp directory. 2.35.18. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$84840 2.35.18.1. Executed ABC. Extracted 302 gates and 357 wires to a netlist network with 54 inputs and 29 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.18.2. Re-integrating ABC results. ABC RESULTS: AND cells: 42 ABC RESULTS: ANDNOT cells: 8 ABC RESULTS: DFF cells: 1 ABC RESULTS: MUX cells: 3 ABC RESULTS: NAND cells: 27 ABC RESULTS: NOR cells: 19 ABC RESULTS: NOT cells: 7 ABC RESULTS: OR cells: 53 ABC RESULTS: ORNOT cells: 1 ABC RESULTS: XOR cells: 1 ABC RESULTS: internal signals: 274 ABC RESULTS: input signals: 54 ABC RESULTS: output signals: 29 Removing temp directory. 2.35.19. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$86411 2.35.19.1. Executed ABC. Extracted 463 gates and 540 wires to a netlist network with 76 inputs and 67 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.19.2. Re-integrating ABC results. ABC RESULTS: AND cells: 58 ABC RESULTS: ANDNOT cells: 10 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 1 ABC RESULTS: MUX cells: 2 ABC RESULTS: NAND cells: 43 ABC RESULTS: NOR cells: 34 ABC RESULTS: NOT cells: 10 ABC RESULTS: OR cells: 114 ABC RESULTS: ORNOT cells: 2 ABC RESULTS: XNOR cells: 2 ABC RESULTS: internal signals: 397 ABC RESULTS: input signals: 76 ABC RESULTS: output signals: 67 Removing temp directory. 2.35.20. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$85477 2.35.21. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$86121 2.35.22. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$86698 2.35.23. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$86826 2.35.24. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$87210 2.35.25. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$87628 2.35.26. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$87756 2.35.27. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$87082 2.35.28. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$87341 2.35.29. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$87884 2.35.30. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$88012 2.35.31. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$88140 2.35.32. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$88268 2.35.33. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$88396 2.35.34. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$88524 2.35.35. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$88652 2.35.36. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$88780 2.35.37. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$88908 2.35.38. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$69966 2.35.39. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$70257 2.35.39.1. Executed ABC. Extracted 408 gates and 487 wires to a netlist network with 78 inputs and 65 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.39.2. Re-integrating ABC results. ABC RESULTS: AND cells: 40 ABC RESULTS: ANDNOT cells: 11 ABC RESULTS: DFF cells: 1 ABC RESULTS: MUX cells: 4 ABC RESULTS: NAND cells: 30 ABC RESULTS: NOR cells: 30 ABC RESULTS: NOT cells: 7 ABC RESULTS: OR cells: 102 ABC RESULTS: ORNOT cells: 3 ABC RESULTS: XNOR cells: 1 ABC RESULTS: XOR cells: 1 ABC RESULTS: internal signals: 344 ABC RESULTS: input signals: 78 ABC RESULTS: output signals: 65 Removing temp directory. 2.35.40. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$70902 2.35.41. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$71546 2.35.42. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$72182 2.35.43. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$72818 2.35.44. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$73454 2.35.45. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$74090 2.35.46. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$74722 2.35.47. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$74834 2.35.48. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$75470 2.35.49. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$76107 2.35.50. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$76752 2.35.51. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$77397 2.35.52. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$78042 2.35.53. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$78687 2.35.54. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$79331 2.35.55. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$79621 2.35.56. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$79912 2.35.57. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$80550 2.35.58. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$80594 2.35.58.1. Executed ABC. Extracted 694 gates and 795 wires to a netlist network with 100 inputs and 86 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 46 ABC RESULTS: ANDNOT cells: 17 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 1 ABC RESULTS: MUX cells: 2 ABC RESULTS: NAND cells: 76 ABC RESULTS: NOR cells: 40 ABC RESULTS: NOT cells: 11 ABC RESULTS: OR cells: 138 ABC RESULTS: ORNOT cells: 3 ABC RESULTS: XNOR cells: 2 ABC RESULTS: XOR cells: 1 ABC RESULTS: internal signals: 609 ABC RESULTS: input signals: 100 ABC RESULTS: output signals: 86 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 718 gates and 820 wires to a netlist network with 100 inputs and 129 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 50 ABC RESULTS: ANDNOT cells: 21 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 1 ABC RESULTS: MUX cells: 1 ABC RESULTS: NAND cells: 73 ABC RESULTS: NOR cells: 46 ABC RESULTS: NOT cells: 16 ABC RESULTS: OR cells: 170 ABC RESULTS: ORNOT cells: 4 ABC RESULTS: XNOR cells: 2 ABC RESULTS: XOR cells: 3 ABC RESULTS: internal signals: 591 ABC RESULTS: input signals: 100 ABC RESULTS: output signals: 129 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 523 gates and 596 wires to a netlist network with 71 inputs and 69 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 31 ABC RESULTS: ANDNOT cells: 5 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 1 ABC RESULTS: MUX cells: 1 ABC RESULTS: NAND cells: 57 ABC RESULTS: NOR cells: 29 ABC RESULTS: NOT cells: 8 ABC RESULTS: OR cells: 91 ABC RESULTS: ORNOT cells: 3 ABC RESULTS: XNOR cells: 1 ABC RESULTS: XOR cells: 2 ABC RESULTS: internal signals: 456 ABC RESULTS: input signals: 71 ABC RESULTS: output signals: 69 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 471 gates and 542 wires to a netlist network with 69 inputs and 66 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 10> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 45 ABC RESULTS: ANDNOT cells: 10 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 1 ABC RESULTS: MUX cells: 6 ABC RESULTS: NAND cells: 32 ABC RESULTS: NOR cells: 22 ABC RESULTS: NOT cells: 17 ABC RESULTS: OR cells: 69 ABC RESULTS: ORNOT cells: 5 ABC RESULTS: XNOR cells: 3 ABC RESULTS: XOR cells: 2 ABC RESULTS: internal signals: 407 ABC RESULTS: input signals: 69 ABC RESULTS: output signals: 66 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 308 gates and 322 wires to a netlist network with 13 inputs and 16 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 10> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 21 ABC RESULTS: ANDNOT cells: 7 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 1 ABC RESULTS: MUX cells: 5 ABC RESULTS: NAND cells: 31 ABC RESULTS: NOR cells: 6 ABC RESULTS: NOT cells: 3 ABC RESULTS: OR cells: 6 ABC RESULTS: ORNOT cells: 4 ABC RESULTS: XOR cells: 2 ABC RESULTS: internal signals: 293 ABC RESULTS: input signals: 13 ABC RESULTS: output signals: 16 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 123 gates and 140 wires to a netlist network with 15 inputs and 17 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 10> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 10 ABC RESULTS: ANDNOT cells: 4 ABC RESULTS: DFF cells: 1 ABC RESULTS: MUX cells: 1 ABC RESULTS: NAND cells: 5 ABC RESULTS: NOR cells: 1 ABC RESULTS: NOT cells: 6 ABC RESULTS: OR cells: 6 ABC RESULTS: ORNOT cells: 4 ABC RESULTS: XOR cells: 2 ABC RESULTS: internal signals: 108 ABC RESULTS: input signals: 15 ABC RESULTS: output signals: 17 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 19 gates and 27 wires to a netlist network with 8 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 10> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 3 ABC RESULTS: OR cells: 3 ABC RESULTS: internal signals: 16 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 51 gates and 61 wires to a netlist network with 10 inputs and 4 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 19> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 3 ABC RESULTS: NAND cells: 8 ABC RESULTS: NOR cells: 4 ABC RESULTS: NOT cells: 3 ABC RESULTS: OR cells: 1 ABC RESULTS: ORNOT cells: 1 ABC RESULTS: internal signals: 47 ABC RESULTS: input signals: 10 ABC RESULTS: output signals: 4 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 51 gates and 61 wires to a netlist network with 10 inputs and 4 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 19> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 3 ABC RESULTS: NAND cells: 8 ABC RESULTS: NOR cells: 4 ABC RESULTS: NOT cells: 3 ABC RESULTS: OR cells: 1 ABC RESULTS: ORNOT cells: 1 ABC RESULTS: internal signals: 47 ABC RESULTS: input signals: 10 ABC RESULTS: output signals: 4 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 82 gates and 114 wires to a netlist network with 32 inputs and 4 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 19> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 32 ABC RESULTS: DFF cells: 3 ABC RESULTS: NAND cells: 1 ABC RESULTS: NOT cells: 3 ABC RESULTS: OR cells: 5 ABC RESULTS: internal signals: 78 ABC RESULTS: input signals: 32 ABC RESULTS: output signals: 4 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 82 gates and 114 wires to a netlist network with 32 inputs and 4 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 28> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 32 ABC RESULTS: DFF cells: 3 ABC RESULTS: NAND cells: 1 ABC RESULTS: NOT cells: 3 ABC RESULTS: OR cells: 5 ABC RESULTS: internal signals: 78 ABC RESULTS: input signals: 32 ABC RESULTS: output signals: 4 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 81 gates and 113 wires to a netlist network with 32 inputs and 4 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 28> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 30 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 3 ABC RESULTS: NAND cells: 2 ABC RESULTS: NOT cells: 2 ABC RESULTS: OR cells: 4 ABC RESULTS: internal signals: 77 ABC RESULTS: input signals: 32 ABC RESULTS: output signals: 4 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 51 gates and 61 wires to a netlist network with 10 inputs and 4 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 28> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 3 ABC RESULTS: NAND cells: 8 ABC RESULTS: NOR cells: 4 ABC RESULTS: NOT cells: 3 ABC RESULTS: OR cells: 1 ABC RESULTS: ORNOT cells: 1 ABC RESULTS: internal signals: 47 ABC RESULTS: input signals: 10 ABC RESULTS: output signals: 4 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 82 gates and 114 wires to a netlist network with 32 inputs and 4 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 37> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 32 ABC RESULTS: DFF cells: 3 ABC RESULTS: NAND cells: 1 ABC RESULTS: NOT cells: 3 ABC RESULTS: OR cells: 5 ABC RESULTS: internal signals: 78 ABC RESULTS: input signals: 32 ABC RESULTS: output signals: 4 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 51 gates and 61 wires to a netlist network with 10 inputs and 4 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 19> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 3 ABC RESULTS: NAND cells: 8 ABC RESULTS: NOR cells: 4 ABC RESULTS: NOT cells: 3 ABC RESULTS: OR cells: 1 ABC RESULTS: ORNOT cells: 1 ABC RESULTS: internal signals: 47 ABC RESULTS: input signals: 10 ABC RESULTS: output signals: 4 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 19 gates and 27 wires to a netlist network with 8 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 28> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 3 ABC RESULTS: OR cells: 3 ABC RESULTS: internal signals: 16 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 19 gates and 27 wires to a netlist network with 8 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 37> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 3 ABC RESULTS: OR cells: 3 ABC RESULTS: internal signals: 16 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 19 gates and 27 wires to a netlist network with 8 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 37> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 3 ABC RESULTS: OR cells: 3 ABC RESULTS: internal signals: 16 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 19 gates and 27 wires to a netlist network with 8 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 46> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 3 ABC RESULTS: OR cells: 3 ABC RESULTS: internal signals: 16 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 19 gates and 27 wires to a netlist network with 8 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 46> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 3 ABC RESULTS: OR cells: 3 ABC RESULTS: internal signals: 16 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 19 gates and 27 wires to a netlist network with 8 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 46> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 3 ABC RESULTS: OR cells: 3 ABC RESULTS: internal signals: 16 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 51 gates and 61 wires to a netlist network with 10 inputs and 4 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 55> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 3 ABC RESULTS: NAND cells: 8 ABC RESULTS: NOR cells: 4 ABC RESULTS: NOT cells: 3 ABC RESULTS: OR cells: 1 ABC RESULTS: ORNOT cells: 1 ABC RESULTS: internal signals: 47 ABC RESULTS: input signals: 10 ABC RESULTS: output signals: 4 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 19 gates and 27 wires to a netlist network with 8 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 55> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 3 ABC RESULTS: OR cells: 3 ABC RESULTS: internal signals: 16 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 19 gates and 27 wires to a netlist network with 8 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 64> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 3 ABC RESULTS: OR cells: 3 ABC RESULTS: internal signals: 16 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 19 gates and 27 wires to a netlist network with 8 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 37> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 3 ABC RESULTS: OR cells: 3 ABC RESULTS: internal signals: 16 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 19 gates and 27 wires to a netlist network with 8 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 64> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 3 ABC RESULTS: OR cells: 3 ABC RESULTS: internal signals: 16 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 19 gates and 27 wires to a netlist network with 8 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 10> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 3 ABC RESULTS: OR cells: 3 ABC RESULTS: internal signals: 16 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 19 gates and 27 wires to a netlist network with 8 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 73> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 3 ABC RESULTS: OR cells: 3 ABC RESULTS: internal signals: 16 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 19 gates and 27 wires to a netlist network with 8 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 55> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 3 ABC RESULTS: OR cells: 3 ABC RESULTS: internal signals: 16 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 19 gates and 27 wires to a netlist network with 8 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 82> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 3 ABC RESULTS: OR cells: 3 ABC RESULTS: internal signals: 16 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 19 gates and 27 wires to a netlist network with 8 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 64> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 3 ABC RESULTS: OR cells: 3 ABC RESULTS: internal signals: 16 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 90 gates and 117 wires to a netlist network with 25 inputs and 10 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 91> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: Abc_NtkRetimeInitialValues(): The problem is unsatisfiable. DC latch values are used. ABC: + strash ABC: + &get -n ABC: Warning: 5 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 8 ABC RESULTS: ANDNOT cells: 4 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 5 ABC RESULTS: MUX cells: 1 ABC RESULTS: NAND cells: 4 ABC RESULTS: NOR cells: 6 ABC RESULTS: NOT cells: 3 ABC RESULTS: OR cells: 7 ABC RESULTS: ORNOT cells: 2 ABC RESULTS: XOR cells: 1 ABC RESULTS: internal signals: 82 ABC RESULTS: input signals: 25 ABC RESULTS: output signals: 10 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 297 gates and 354 wires to a netlist network with 55 inputs and 36 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 46> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 24 ABC RESULTS: ANDNOT cells: 6 ABC RESULTS: BUF cells: 3 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 1 ABC RESULTS: NAND cells: 28 ABC RESULTS: NOR cells: 19 ABC RESULTS: NOT cells: 5 ABC RESULTS: OR cells: 55 ABC RESULTS: ORNOT cells: 9 ABC RESULTS: XOR cells: 1 ABC RESULTS: internal signals: 263 ABC RESULTS: input signals: 55 ABC RESULTS: output signals: 36 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 229 gates and 293 wires to a netlist network with 62 inputs and 25 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 73> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 21 ABC RESULTS: ANDNOT cells: 5 ABC RESULTS: BUF cells: 3 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 5 ABC RESULTS: NAND cells: 31 ABC RESULTS: NOR cells: 19 ABC RESULTS: NOT cells: 9 ABC RESULTS: OR cells: 14 ABC RESULTS: ORNOT cells: 8 ABC RESULTS: XNOR cells: 1 ABC RESULTS: internal signals: 206 ABC RESULTS: input signals: 62 ABC RESULTS: output signals: 25 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 269 gates and 330 wires to a netlist network with 59 inputs and 39 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 73> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 23 ABC RESULTS: ANDNOT cells: 3 ABC RESULTS: BUF cells: 3 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 4 ABC RESULTS: NAND cells: 19 ABC RESULTS: NOR cells: 7 ABC RESULTS: NOT cells: 5 ABC RESULTS: OR cells: 23 ABC RESULTS: ORNOT cells: 16 ABC RESULTS: XNOR cells: 1 ABC RESULTS: internal signals: 232 ABC RESULTS: input signals: 59 ABC RESULTS: output signals: 39 Removing temp directory. 2.35.58.1. Executed ABC. Extracted 581 gates and 741 wires to a netlist network with 158 inputs and 78 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 100> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.58.2. Re-integrating ABC results. ABC RESULTS: AND cells: 66 ABC RESULTS: ANDNOT cells: 12 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 4 ABC RESULTS: NAND cells: 56 ABC RESULTS: NOR cells: 37 ABC RESULTS: NOT cells: 23 ABC RESULTS: OR cells: 83 ABC RESULTS: ORNOT cells: 13 ABC RESULTS: XNOR cells: 2 ABC RESULTS: internal signals: 505 ABC RESULTS: input signals: 158 ABC RESULTS: output signals: 78 Removing temp directory. 2.35.59. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$81238 2.35.59.1. Executed ABC. Extracted 460 gates and 554 wires to a netlist network with 92 inputs and 68 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 19> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.59.2. Re-integrating ABC results. ABC RESULTS: AND cells: 47 ABC RESULTS: ANDNOT cells: 9 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 2 ABC RESULTS: NAND cells: 41 ABC RESULTS: NOR cells: 23 ABC RESULTS: NOT cells: 14 ABC RESULTS: OR cells: 90 ABC RESULTS: ORNOT cells: 8 ABC RESULTS: XNOR cells: 1 ABC RESULTS: internal signals: 394 ABC RESULTS: input signals: 92 ABC RESULTS: output signals: 68 Removing temp directory. 2.35.59.1. Executed ABC. Extracted 404 gates and 528 wires to a netlist network with 122 inputs and 74 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 109> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.59.2. Re-integrating ABC results. ABC RESULTS: AND cells: 42 ABC RESULTS: ANDNOT cells: 6 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 2 ABC RESULTS: NAND cells: 30 ABC RESULTS: NOR cells: 23 ABC RESULTS: NOT cells: 12 ABC RESULTS: OR cells: 78 ABC RESULTS: ORNOT cells: 10 ABC RESULTS: internal signals: 332 ABC RESULTS: input signals: 122 ABC RESULTS: output signals: 74 Removing temp directory. 2.35.60. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$81525 2.35.61. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$81653 2.35.62. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$81781 2.35.63. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$81909 2.35.64. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$82037 2.35.65. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$82165 2.35.65.1. Executed ABC. Extracted 492 gates and 605 wires to a netlist network with 111 inputs and 56 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 10> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.65.2. Re-integrating ABC results. ABC RESULTS: AND cells: 63 ABC RESULTS: ANDNOT cells: 4 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 3 ABC RESULTS: NAND cells: 44 ABC RESULTS: NOR cells: 17 ABC RESULTS: NOT cells: 14 ABC RESULTS: OR cells: 37 ABC RESULTS: ORNOT cells: 13 ABC RESULTS: XNOR cells: 1 ABC RESULTS: internal signals: 438 ABC RESULTS: input signals: 111 ABC RESULTS: output signals: 56 Removing temp directory. 2.35.66. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$82293 2.35.67. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$82421 2.35.68. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$82549 2.35.69. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$82680 2.35.70. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$89590 2.35.70.1. Executed ABC. Extracted 521 gates and 634 wires to a netlist network with 111 inputs and 127 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 82> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: Abc_NtkRetimeInitialValues(): The problem is unsatisfiable. DC latch values are used. ABC: + strash ABC: + &get -n ABC: Warning: 4 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.70.2. Re-integrating ABC results. ABC RESULTS: AND cells: 56 ABC RESULTS: ANDNOT cells: 16 ABC RESULTS: DFF cells: 4 ABC RESULTS: MUX cells: 2 ABC RESULTS: NAND cells: 61 ABC RESULTS: NOR cells: 51 ABC RESULTS: NOT cells: 23 ABC RESULTS: OR cells: 96 ABC RESULTS: ORNOT cells: 27 ABC RESULTS: internal signals: 396 ABC RESULTS: input signals: 111 ABC RESULTS: output signals: 127 Removing temp directory. 2.35.70.1. Executed ABC. Extracted 384 gates and 459 wires to a netlist network with 73 inputs and 62 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 55> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: Abc_NtkRetimeInitialValues(): The problem is unsatisfiable. DC latch values are used. ABC: + strash ABC: + &get -n ABC: Warning: 7 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.70.2. Re-integrating ABC results. ABC RESULTS: AND cells: 32 ABC RESULTS: ANDNOT cells: 7 ABC RESULTS: DFF cells: 7 ABC RESULTS: MUX cells: 2 ABC RESULTS: NAND cells: 28 ABC RESULTS: NOR cells: 17 ABC RESULTS: NOT cells: 12 ABC RESULTS: OR cells: 78 ABC RESULTS: ORNOT cells: 6 ABC RESULTS: internal signals: 324 ABC RESULTS: input signals: 73 ABC RESULTS: output signals: 62 Removing temp directory. 2.35.70.1. Executed ABC. Extracted 441 gates and 550 wires to a netlist network with 107 inputs and 73 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 118> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.70.2. Re-integrating ABC results. ABC RESULTS: AND cells: 53 ABC RESULTS: ANDNOT cells: 4 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 2 ABC RESULTS: NAND cells: 33 ABC RESULTS: NOR cells: 16 ABC RESULTS: NOT cells: 17 ABC RESULTS: OR cells: 75 ABC RESULTS: ORNOT cells: 9 ABC RESULTS: internal signals: 370 ABC RESULTS: input signals: 107 ABC RESULTS: output signals: 73 Removing temp directory. 2.35.70.1. Executed ABC. Extracted 353 gates and 428 wires to a netlist network with 73 inputs and 31 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 82> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.70.2. Re-integrating ABC results. ABC RESULTS: AND cells: 47 ABC RESULTS: ANDNOT cells: 5 ABC RESULTS: BUF cells: 3 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 1 ABC RESULTS: NAND cells: 30 ABC RESULTS: NOR cells: 13 ABC RESULTS: NOT cells: 7 ABC RESULTS: OR cells: 26 ABC RESULTS: ORNOT cells: 8 ABC RESULTS: internal signals: 324 ABC RESULTS: input signals: 73 ABC RESULTS: output signals: 31 Removing temp directory. 2.35.70.1. Executed ABC. Extracted 390 gates and 465 wires to a netlist network with 73 inputs and 42 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 127> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.70.2. Re-integrating ABC results. ABC RESULTS: AND cells: 52 ABC RESULTS: ANDNOT cells: 9 ABC RESULTS: BUF cells: 3 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 1 ABC RESULTS: NAND cells: 45 ABC RESULTS: NOR cells: 15 ABC RESULTS: NOT cells: 15 ABC RESULTS: OR cells: 22 ABC RESULTS: ORNOT cells: 8 ABC RESULTS: internal signals: 350 ABC RESULTS: input signals: 73 ABC RESULTS: output signals: 42 Removing temp directory. 2.35.71. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. Found matching posedge clock domain: \clk 2.35.71.1. Executed ABC. Extracted 313 gates and 360 wires to a netlist network with 45 inputs and 35 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 10> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 36 ABC RESULTS: ANDNOT cells: 4 ABC RESULTS: BUF cells: 3 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 2 ABC RESULTS: NAND cells: 31 ABC RESULTS: NOR cells: 5 ABC RESULTS: NOT cells: 13 ABC RESULTS: OR cells: 22 ABC RESULTS: ORNOT cells: 8 ABC RESULTS: XNOR cells: 2 ABC RESULTS: internal signals: 280 ABC RESULTS: input signals: 45 ABC RESULTS: output signals: 35 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 274 gates and 319 wires to a netlist network with 43 inputs and 27 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 64> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 20 ABC RESULTS: ANDNOT cells: 5 ABC RESULTS: BUF cells: 3 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 4 ABC RESULTS: NAND cells: 22 ABC RESULTS: NOR cells: 11 ABC RESULTS: NOT cells: 6 ABC RESULTS: OR cells: 13 ABC RESULTS: ORNOT cells: 18 ABC RESULTS: XNOR cells: 3 ABC RESULTS: XOR cells: 1 ABC RESULTS: internal signals: 249 ABC RESULTS: input signals: 43 ABC RESULTS: output signals: 27 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 281 gates and 338 wires to a netlist network with 55 inputs and 43 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 28> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 27 ABC RESULTS: ANDNOT cells: 11 ABC RESULTS: BUF cells: 3 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 4 ABC RESULTS: NAND cells: 28 ABC RESULTS: NOR cells: 6 ABC RESULTS: NOT cells: 12 ABC RESULTS: OR cells: 33 ABC RESULTS: ORNOT cells: 8 ABC RESULTS: XNOR cells: 3 ABC RESULTS: internal signals: 240 ABC RESULTS: input signals: 55 ABC RESULTS: output signals: 43 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 436 gates and 503 wires to a netlist network with 65 inputs and 53 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 91> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: Abc_NtkRetimeInitialValues(): The problem is unsatisfiable. DC latch values are used. ABC: + strash ABC: + &get -n ABC: Warning: 5 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 43 ABC RESULTS: ANDNOT cells: 10 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 5 ABC RESULTS: MUX cells: 5 ABC RESULTS: NAND cells: 40 ABC RESULTS: NOR cells: 9 ABC RESULTS: NOT cells: 14 ABC RESULTS: OR cells: 34 ABC RESULTS: ORNOT cells: 13 ABC RESULTS: XNOR cells: 1 ABC RESULTS: XOR cells: 3 ABC RESULTS: internal signals: 385 ABC RESULTS: input signals: 65 ABC RESULTS: output signals: 53 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 340 gates and 420 wires to a netlist network with 78 inputs and 61 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 136> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: Abc_NtkRetimeInitialValues(): The problem is unsatisfiable. DC latch values are used. ABC: + strash ABC: + &get -n ABC: Warning: 5 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 47 ABC RESULTS: ANDNOT cells: 10 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 5 ABC RESULTS: NAND cells: 28 ABC RESULTS: NOR cells: 19 ABC RESULTS: NOT cells: 15 ABC RESULTS: OR cells: 36 ABC RESULTS: ORNOT cells: 12 ABC RESULTS: XNOR cells: 2 ABC RESULTS: XOR cells: 2 ABC RESULTS: internal signals: 281 ABC RESULTS: input signals: 78 ABC RESULTS: output signals: 61 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 322 gates and 385 wires to a netlist network with 61 inputs and 39 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 73> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 32 ABC RESULTS: ANDNOT cells: 10 ABC RESULTS: BUF cells: 3 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 3 ABC RESULTS: NAND cells: 27 ABC RESULTS: NOR cells: 10 ABC RESULTS: NOT cells: 10 ABC RESULTS: OR cells: 22 ABC RESULTS: ORNOT cells: 17 ABC RESULTS: XNOR cells: 1 ABC RESULTS: internal signals: 285 ABC RESULTS: input signals: 61 ABC RESULTS: output signals: 39 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 615 gates and 652 wires to a netlist network with 35 inputs and 33 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 37> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 36 ABC RESULTS: ANDNOT cells: 13 ABC RESULTS: DFF cells: 2 ABC RESULTS: MUX cells: 8 ABC RESULTS: NAND cells: 59 ABC RESULTS: NOR cells: 15 ABC RESULTS: NOT cells: 12 ABC RESULTS: OR cells: 29 ABC RESULTS: ORNOT cells: 10 ABC RESULTS: XNOR cells: 2 ABC RESULTS: XOR cells: 1 ABC RESULTS: internal signals: 584 ABC RESULTS: input signals: 35 ABC RESULTS: output signals: 33 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 211 gates and 249 wires to a netlist network with 36 inputs and 18 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 19> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 13 ABC RESULTS: ANDNOT cells: 4 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 4 ABC RESULTS: NAND cells: 17 ABC RESULTS: NOR cells: 6 ABC RESULTS: NOT cells: 4 ABC RESULTS: OR cells: 16 ABC RESULTS: ORNOT cells: 10 ABC RESULTS: internal signals: 195 ABC RESULTS: input signals: 36 ABC RESULTS: output signals: 18 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 178 gates and 210 wires to a netlist network with 30 inputs and 36 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 100> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: Abc_NtkRetimeInitialValues(): The problem is unsatisfiable. DC latch values are used. ABC: + strash ABC: + &get -n ABC: Warning: 5 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 12 ABC RESULTS: ANDNOT cells: 7 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 5 ABC RESULTS: NAND cells: 10 ABC RESULTS: NOR cells: 13 ABC RESULTS: NOT cells: 8 ABC RESULTS: OR cells: 21 ABC RESULTS: ORNOT cells: 11 ABC RESULTS: XNOR cells: 1 ABC RESULTS: internal signals: 144 ABC RESULTS: input signals: 30 ABC RESULTS: output signals: 36 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 112 gates and 134 wires to a netlist network with 20 inputs and 11 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 82> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 6 ABC RESULTS: ANDNOT cells: 2 ABC RESULTS: DFF cells: 4 ABC RESULTS: MUX cells: 1 ABC RESULTS: NAND cells: 4 ABC RESULTS: NOR cells: 3 ABC RESULTS: NOT cells: 2 ABC RESULTS: OR cells: 6 ABC RESULTS: ORNOT cells: 3 ABC RESULTS: XOR cells: 4 ABC RESULTS: internal signals: 103 ABC RESULTS: input signals: 20 ABC RESULTS: output signals: 11 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 226 gates and 249 wires to a netlist network with 21 inputs and 20 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 145> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 19 ABC RESULTS: ANDNOT cells: 8 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 3 ABC RESULTS: NAND cells: 24 ABC RESULTS: NOR cells: 5 ABC RESULTS: NOT cells: 5 ABC RESULTS: OR cells: 5 ABC RESULTS: ORNOT cells: 7 ABC RESULTS: XOR cells: 3 ABC RESULTS: internal signals: 208 ABC RESULTS: input signals: 21 ABC RESULTS: output signals: 20 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 226 gates and 249 wires to a netlist network with 21 inputs and 20 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 109> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 19 ABC RESULTS: ANDNOT cells: 8 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 3 ABC RESULTS: NAND cells: 24 ABC RESULTS: NOR cells: 5 ABC RESULTS: NOT cells: 5 ABC RESULTS: OR cells: 5 ABC RESULTS: ORNOT cells: 7 ABC RESULTS: XOR cells: 3 ABC RESULTS: internal signals: 208 ABC RESULTS: input signals: 21 ABC RESULTS: output signals: 20 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 217 gates and 236 wires to a netlist network with 17 inputs and 18 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 91> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 17 ABC RESULTS: ANDNOT cells: 7 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 3 ABC RESULTS: NAND cells: 22 ABC RESULTS: NOR cells: 6 ABC RESULTS: NOT cells: 3 ABC RESULTS: OR cells: 3 ABC RESULTS: ORNOT cells: 7 ABC RESULTS: XOR cells: 4 ABC RESULTS: internal signals: 201 ABC RESULTS: input signals: 17 ABC RESULTS: output signals: 18 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 196 gates and 212 wires to a netlist network with 14 inputs and 15 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 28> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 11 ABC RESULTS: ANDNOT cells: 4 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 4 ABC RESULTS: NAND cells: 28 ABC RESULTS: NOR cells: 6 ABC RESULTS: NOT cells: 2 ABC RESULTS: OR cells: 4 ABC RESULTS: ORNOT cells: 5 ABC RESULTS: XOR cells: 2 ABC RESULTS: internal signals: 183 ABC RESULTS: input signals: 14 ABC RESULTS: output signals: 15 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 67 gates and 86 wires to a netlist network with 17 inputs and 16 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 91> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 5 ABC RESULTS: ANDNOT cells: 1 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 1 ABC RESULTS: NAND cells: 4 ABC RESULTS: NOR cells: 2 ABC RESULTS: NOT cells: 3 ABC RESULTS: OR cells: 7 ABC RESULTS: ORNOT cells: 6 ABC RESULTS: XOR cells: 1 ABC RESULTS: internal signals: 53 ABC RESULTS: input signals: 17 ABC RESULTS: output signals: 16 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 65 gates and 85 wires to a netlist network with 18 inputs and 13 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 100> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 4 ABC RESULTS: ANDNOT cells: 3 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 1 ABC RESULTS: NAND cells: 7 ABC RESULTS: NOR cells: 3 ABC RESULTS: NOT cells: 2 ABC RESULTS: OR cells: 6 ABC RESULTS: ORNOT cells: 1 ABC RESULTS: XNOR cells: 2 ABC RESULTS: internal signals: 54 ABC RESULTS: input signals: 18 ABC RESULTS: output signals: 13 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 121 gates and 141 wires to a netlist network with 18 inputs and 23 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 109> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 9 ABC RESULTS: ANDNOT cells: 3 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 3 ABC RESULTS: MUX cells: 2 ABC RESULTS: NAND cells: 11 ABC RESULTS: NOR cells: 3 ABC RESULTS: NOT cells: 5 ABC RESULTS: OR cells: 6 ABC RESULTS: ORNOT cells: 9 ABC RESULTS: XNOR cells: 2 ABC RESULTS: internal signals: 100 ABC RESULTS: input signals: 18 ABC RESULTS: output signals: 23 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 48 gates and 59 wires to a netlist network with 11 inputs and 12 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 154> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 1 ABC RESULTS: ANDNOT cells: 2 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 3 ABC RESULTS: NAND cells: 3 ABC RESULTS: NOR cells: 3 ABC RESULTS: NOT cells: 1 ABC RESULTS: OR cells: 4 ABC RESULTS: ORNOT cells: 4 ABC RESULTS: XNOR cells: 1 ABC RESULTS: internal signals: 36 ABC RESULTS: input signals: 11 ABC RESULTS: output signals: 12 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 51 gates and 61 wires to a netlist network with 10 inputs and 4 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 163> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 3 ABC RESULTS: NAND cells: 8 ABC RESULTS: NOR cells: 4 ABC RESULTS: NOT cells: 3 ABC RESULTS: OR cells: 1 ABC RESULTS: ORNOT cells: 1 ABC RESULTS: internal signals: 47 ABC RESULTS: input signals: 10 ABC RESULTS: output signals: 4 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 22 gates and 28 wires to a netlist network with 6 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 19> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 4 ABC RESULTS: NOT cells: 2 ABC RESULTS: OR cells: 3 ABC RESULTS: internal signals: 19 ABC RESULTS: input signals: 6 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.71.1. Executed ABC. Extracted 1524 gates and 1880 wires to a netlist network with 354 inputs and 571 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 46> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 1035 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.71.2. Re-integrating ABC results. ABC RESULTS: AND cells: 24 ABC RESULTS: ANDNOT cells: 28 ABC RESULTS: BUF cells: 1129 ABC RESULTS: DFF cells: 925 ABC RESULTS: MUX cells: 36 ABC RESULTS: NAND cells: 48 ABC RESULTS: NOR cells: 12 ABC RESULTS: NOT cells: 83 ABC RESULTS: OR cells: 124 ABC RESULTS: ORNOT cells: 74 ABC RESULTS: XNOR cells: 1 ABC RESULTS: XOR cells: 1 ABC RESULTS: internal signals: 955 ABC RESULTS: input signals: 354 ABC RESULTS: output signals: 571 Removing temp directory. Removing global temp directory. 2.36. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Removed 0 unused cells and 18582 unused wires. 2.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2.38. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 8515 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 8324 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Computing hashes of 8319 cells of `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Finding duplicate cells in `\top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Removed a total of 196 cells. 2.39. Executing TECHMAP pass (map to technology primitives). 2.39.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 2.39.2. Continuing TECHMAP pass. Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. No more expansions possible. 2.40. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2.42. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.43. Executing ATTRMVCP pass (move or copy attributes). 2.44. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_mul_we8_wf35_zynq7000_native_f500.. Removed 1 unused cells and 4816 unused wires. 2.45. Executing ABC pass (technology mapping using ABC). 2.45.1. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. 2.45.1.1. Executed ABC. Extracted 6912 gates and 7319 wires to a netlist network with 406 inputs and 342 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.45.1.2. Re-integrating ABC results. ABC RESULTS: AND cells: 1830 ABC RESULTS: ANDNOT cells: 203 ABC RESULTS: MUX cells: 131 ABC RESULTS: NAND cells: 1485 ABC RESULTS: NOR cells: 150 ABC RESULTS: NOT cells: 74 ABC RESULTS: OR cells: 304 ABC RESULTS: ORNOT cells: 118 ABC RESULTS: XNOR cells: 82 ABC RESULTS: XOR cells: 88 ABC RESULTS: internal signals: 6571 ABC RESULTS: input signals: 406 ABC RESULTS: output signals: 342 Removing temp directory. Removing global temp directory. 2.46. Executing TECHMAP pass (map to technology primitives). 2.46.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v' to AST representation. Generating RTLIL representation for module `$_DLATCH_N_'. Generating RTLIL representation for module `$_DLATCH_P_'. Successfully finished Verilog frontend. 2.46.2. Continuing TECHMAP pass. No more expansions possible. 2.47. Executing ABC pass (technology mapping using ABC). 2.47.1. Summary of detected clock domains: 5862 cells in clk={ }, en={ }, arst={ }, srst={ } 2.47.2. Extracting gate netlist of module `\top_flopoco_mul_we8_wf35_zynq7000_native_f500' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 2.47.2.1. Executed ABC. Extracted 4465 gates and 4871 wires to a netlist network with 406 inputs and 342 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_lut /lutdefs.txt ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + dress /input.blif ABC: Total number of equiv classes = 657. ABC: Participating nodes from both networks = 1355. ABC: Participating nodes from the first network = 670. ( 99.26 % of nodes) ABC: Participating nodes from the second network = 685. ( 101.48 % of nodes) ABC: Node pairs (any polarity) = 670. ( 99.26 % of names can be moved) ABC: Node pairs (same polarity) = 518. ( 76.74 % of names can be moved) ABC: Total runtime = 0.14 sec ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.47.2.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 674 ABC RESULTS: internal signals: 4123 ABC RESULTS: input signals: 406 ABC RESULTS: output signals: 342 Removing temp directory. Removing global temp directory. Removed 0 unused cells and 12210 unused wires. 2.48. Executing TECHMAP pass (map to technology primitives). 2.48.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `$lut'. Successfully finished Verilog frontend. 2.48.2. Continuing TECHMAP pass. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$f50a1a210321a8d591d1a926dc046dfdda3eaeab$lut for cells of type $lut. Using template $paramod$deba17538f4cd4af4a7f03bc51507e8ef8b1d7d8$lut for cells of type $lut. Using template $paramod$51dd9d980e2e816ade7f4829e694ca2759d5e823$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. Using template $paramod$48b9149c902e7e516cf34337513f383002b838c7$lut for cells of type $lut. Using template $paramod$1adac8989f9f55cd9c12f68b1dd8a8ba77e74055$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut. Using template $paramod$7c57228df39eed5240de04995e61ac6a2ad834e4$lut for cells of type $lut. Using template $paramod$113844ddc8f6bcaae9d7d3c32b96ad83b783cb3e$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$595b4955041ceff09e28d600fe79275c24ba9878$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010111 for cells of type $lut. Using template $paramod$acf49cb7bd2805dee4b4ebb218aa5924b1be7704$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101011 for cells of type $lut. Using template $paramod$f3d8a27542e35a0eb9c8a06ad1f28e6d9fdbe0f0$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut. Using template $paramod$36ccabff5423ebb9d7a637744a8699d3f3b21f76$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101001 for cells of type $lut. Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2$lut for cells of type $lut. Using template $paramod$9310ffc2b81cb181335197d3558836067aa78d43$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101000 for cells of type $lut. Using template $paramod$e0c6aeec674d20c1f8fe6b5c58bd6a13a51e9dde$lut for cells of type $lut. Using template $paramod$50b99034fbf984a51c265442496081454147f31e$lut for cells of type $lut. Using template $paramod$e17d82cdc2d9cf251fcb5d47576318090a06bf34$lut for cells of type $lut. Using template $paramod$1843b3c15f2447d117e2d5de9b00f791ef5f9fa3$lut for cells of type $lut. Using template $paramod$cb92beff9eab733e7181d891fbc8c3950b9abc0a$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut. Using template $paramod$a15fd389a2f54cb7b94707b25934d226e68d9e2e$lut for cells of type $lut. Using template $paramod$da2f95476331ffa2143f8212db8aff730de806a0$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$5964dec528c7ded1ee9f528024feacf1107270a1$lut for cells of type $lut. Using template $paramod$066a4c918778f74dfb285a33b9a524349042d5f8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$3f0e8292451e9400c60c392c92c8f3239380a41c$lut for cells of type $lut. Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee$lut for cells of type $lut. Using template $paramod$03e751189a48273cdb0479f44cbfa8356973311d$lut for cells of type $lut. Using template $paramod$8739428f557620f5f998575cc0a2e67c61366675$lut for cells of type $lut. Using template $paramod$dfaa345ad5f211dc9fd72f0b2605b6ae6363f0e6$lut for cells of type $lut. Using template $paramod$78e1751931755f088c8bc676bcbc3bb642c26bfc$lut for cells of type $lut. Using template $paramod$21c681aae93c226cfbb227673a4e20ceb48574a6$lut for cells of type $lut. Using template $paramod$097478852c2d50c8bdddeae0d2cfdf1fcdee491a$lut for cells of type $lut. Using template $paramod$2a903325ab4a535dd324c8a1a0154ed8906f8c21$lut for cells of type $lut. Using template $paramod$efea44943d6bd18cf8f1ae223919bf47ae5a22e0$lut for cells of type $lut. Using template $paramod$fa091d7dfd82100c1ec6b68884d51ec98fefac87$lut for cells of type $lut. Using template $paramod$62b410fd8260aa9fa090f166419d1d998d27e324$lut for cells of type $lut. Using template $paramod$aeb8a41fcb3e3119bb22d135db6fc74e43999cf7$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$bc248d6f35d145d0c2ba3a067bc63ae701ad42d7$lut for cells of type $lut. Using template $paramod$c508ffccf3cb0d44491eb1a488b3e92b1375f011$lut for cells of type $lut. Using template $paramod$b9858789baa476c9fbda751032a8520395738e43$lut for cells of type $lut. Using template $paramod$863aebf593f746424d2e33aa721600b533debc4d$lut for cells of type $lut. Using template $paramod$8c5d6bfb2a72ac51d1f7bb7ce59d575e4f5cd1ff$lut for cells of type $lut. Using template $paramod$abf82a43bde4e76f9c7a4e32bb2d3c901ad3e84b$lut for cells of type $lut. Using template $paramod$a8cc16c01ba743221b9ad89f0545793fc4787d0e$lut for cells of type $lut. Using template $paramod$4f6b7a5a569a56b3391712a325114c3abdb0bde6$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut. Using template $paramod$c154f3b11e8510bc663d48d7c1c685820c6bea6b$lut for cells of type $lut. Using template $paramod$436623729943bb5457d0be7e9aeadccf40823ba4$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010100 for cells of type $lut. Using template $paramod$9f92ff5fa8e143b80669a436fc56c2bcb024e092$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod$6537a4bc680b023ff31948171bb3d2fbee382456$lut for cells of type $lut. Using template $paramod$3b3d55b4e6e1d8297f3381ed4ee2801671edbfca$lut for cells of type $lut. Using template $paramod$1acbab6ee33205a3e2fca1742d53d1668590a1c7$lut for cells of type $lut. Using template $paramod$74364d2eade13c17efba04f798990c85ed61ecaa$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$c5b694ec89d7629b942ccf6a9be1d39e24f8edec$lut for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$c86fc1d725c789ba460d688a9ff55c1a18b45873$lut for cells of type $lut. Using template $paramod$80fd3f90b6a7b38da9d25588666decbe3adaf5ec$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5$lut for cells of type $lut. Using template $paramod$72418fa64a43884c11c4484b8a542fb6fbd58e23$lut for cells of type $lut. Using template $paramod$12879138d1e376f344e47ea40be66b776233be75$lut for cells of type $lut. Using template $paramod$c0a4d9417755c1bd5ec9a311325000b8535d91ad$lut for cells of type $lut. Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542$lut for cells of type $lut. Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb$lut for cells of type $lut. Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912$lut for cells of type $lut. Using template $paramod$da0d148cdeade3c798212107d3d80b366097404a$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011110 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101011 for cells of type $lut. Using template $paramod$6bca8d345d26829068ad91403a25fbe3e0885c1a$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111000 for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304$lut for cells of type $lut. Using template $paramod$e996aaed594f07430cb4a5ef5c68a009ba6f25b7$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110100 for cells of type $lut. Using template $paramod$b8bc045c288b10518ec8e70dc9c6dd9c3b44b62a$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000111 for cells of type $lut. Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75$lut for cells of type $lut. Using template $paramod$765dca61dbfa835dacf2a260c8a4c5a36939a046$lut for cells of type $lut. Using template $paramod$358524b23a8f7ece2afb07df55f3c66052881045$lut for cells of type $lut. Using template $paramod$963699bef276f652ccd6c5a998c5849abad681c5$lut for cells of type $lut. Using template $paramod$47de740331f68fa638e1831726c24e0a05017f64$lut for cells of type $lut. Using template $paramod$5b13d2ee598c87cdbe912286a35c6fd102e2087c$lut for cells of type $lut. Using template $paramod$57310968ad93955c114e3ec7572156654371e7ee$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. Using template $paramod$d8491124e74ff4c2a6af58dc40d6b48eb4c0a220$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b$lut for cells of type $lut. Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2$lut for cells of type $lut. Using template $paramod$13dac64f483e9c96519accdd5d348aef438ce574$lut for cells of type $lut. Using template $paramod$859806e3fb108bcca4d3df5d77142ecbbce67590$lut for cells of type $lut. Using template $paramod$827db7bdd92583370d9900a0bd2338eeacc6e330$lut for cells of type $lut. Using template $paramod$0754ea1e71c5a0aa6e2f65f3f06c74c1389d40c1$lut for cells of type $lut. Using template $paramod$b69f45df0b7c98f394a67f4e14b193a9b7e0f5e0$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut. Using template $paramod$7c55afe16cea9a6e4b898995149da75b016c581e$lut for cells of type $lut. Using template $paramod$082f56d14be390905ebbaf7f650812e44dfe12a7$lut for cells of type $lut. Using template $paramod$e499a46398942fdca1555adb5528525eec5412eb$lut for cells of type $lut. Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut. Using template $paramod$9c83b62fa2dee416ec9861169579062ea7c73f48$lut for cells of type $lut. Using template $paramod$65f2b61594468b5360e0a08e19db732b4a2e1446$lut for cells of type $lut. Using template $paramod$10d95e026bd3e857cf0d2d18e139e7574ad3f526$lut for cells of type $lut. Using template $paramod$d6e3d076d144fb7d40f95a3cfb52f87a62998fbd$lut for cells of type $lut. Using template $paramod$d30888cd2654e7cd8a1c12ba7e692260a4d5655a$lut for cells of type $lut. Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6$lut for cells of type $lut. Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149$lut for cells of type $lut. Using template $paramod$ad5fa4c993dc43c3e00419e69284cb50b42316d6$lut for cells of type $lut. Using template $paramod$af2b970363478c934f632261f05f42c59b0d7a99$lut for cells of type $lut. Using template $paramod$badfdd962acbb4655d71f40546d632703caa4e5c$lut for cells of type $lut. Using template $paramod$38b86e709b1cff9173ff2f907bf9737d452c8bcc$lut for cells of type $lut. Using template $paramod$4ab20f2e18682e7cf646e1bf259efb96ed2a200a$lut for cells of type $lut. Using template $paramod$e92ece64eb7aef8bbb04ebae49e7b3eb2761009a$lut for cells of type $lut. Using template $paramod$400ad249037c926f38a8e89159258cdc9e3eba19$lut for cells of type $lut. Using template $paramod$04c17f685b5530ad4981ffe1c1f8c33f25a76e98$lut for cells of type $lut. Using template $paramod$e68d975d7055249eb24a0ce5822c04247a0085e2$lut for cells of type $lut. Using template $paramod$6be0bb48cd460f3880e770c454f60b48d551ebef$lut for cells of type $lut. Using template $paramod$33af9a654d0d8767ce4253c1bfd82206f064cd49$lut for cells of type $lut. Using template $paramod$7c17ee6f10bcb9402fd65718415290df3d3474e3$lut for cells of type $lut. Using template $paramod$dd2d293c5a457c808823760e2678dc850c355143$lut for cells of type $lut. Using template $paramod$163cc74c8177fa8469d283d0f363d525a268e8c9$lut for cells of type $lut. Using template $paramod$cbea786768e410deedfbb86d4c7777b2b45a7bf7$lut for cells of type $lut. Using template $paramod$1fc870dcd68c125b0e9e2e1ea5facbf931ca741e$lut for cells of type $lut. Using template $paramod$322a479824f4a1a3d9b5fc6fcd0f69171141b551$lut for cells of type $lut. Using template $paramod$0957553aac64542e05c36c7f127adc5dc59b6a0f$lut for cells of type $lut. Using template $paramod$cf0c359c46d5b4cbd9b9b41f042a1aa10765dcc0$lut for cells of type $lut. Using template $paramod$7921767ec42b10343b99f255bd2c4bd78b3f40a0$lut for cells of type $lut. Using template $paramod$2b20e0c3183eeb3c60d9a9d527f12331a3127600$lut for cells of type $lut. Using template $paramod$630bf79b569cb3b3fa1448f510d6b5f1c9e040b9$lut for cells of type $lut. Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0$lut for cells of type $lut. Using template $paramod$6d81b5af448b0f648e9aa77144a59f74f1085556$lut for cells of type $lut. Using template $paramod$b955e6eaa6997081746f97d6a54487bec320e7aa$lut for cells of type $lut. Using template $paramod$0c8fffd8502d9206a83f8254abdf43df1ddc81da$lut for cells of type $lut. Using template $paramod$7d9f1505189b63b651ea4cb1f3e070caa8e25ca5$lut for cells of type $lut. Using template $paramod$200337237619ba4c0bed9a492562f1d1b57fb569$lut for cells of type $lut. Using template $paramod$a52bc3b408311de7f49e7dc9e49a3bf6c56df63c$lut for cells of type $lut. Using template $paramod$edebdbe71006010f17ae4888c047435d9697a7f9$lut for cells of type $lut. Using template $paramod$fef8e00931a6f90054947808155e5fd904ae0c3d$lut for cells of type $lut. Using template $paramod$c37638110016211b8e6dcbb635e850290f90de8c$lut for cells of type $lut. Using template $paramod$8b49c5f9b928344c86b72a692f6ae5614e9886b2$lut for cells of type $lut. Using template $paramod$beec82aa85e66b3d965f1f496cd61d5de055ceea$lut for cells of type $lut. Using template $paramod$e80261ac050c799b89c3eb8f9dbdce052fa52408$lut for cells of type $lut. Using template $paramod$e35d583bee6d741f443a06de953f67334bd94348$lut for cells of type $lut. Using template $paramod$c27e9d225b230c8baba7893b699f32cb736bf27b$lut for cells of type $lut. Using template $paramod$19232694b104ec9f70ceb28797a5ac59e9b4cb1a$lut for cells of type $lut. Using template $paramod$48858a0cdda2de6934604a272e0a7e64a67fda48$lut for cells of type $lut. Using template $paramod$e93f4df3bb2a0997f949475853191e5b77041a63$lut for cells of type $lut. Using template $paramod$06dc8f5deb4108557fa887a04d2252f1a3c144ac$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011110 for cells of type $lut. Using template $paramod$f05d4b8888c79762c43743d193b4196209b4613e$lut for cells of type $lut. Using template $paramod$c23a35c92ce268c13bd338256e0e29072e4e256b$lut for cells of type $lut. Using template $paramod$ff172dfd2f5fbe9de760fe0ebe2b7c7412eb8835$lut for cells of type $lut. Using template $paramod$dd4e7da19f5a5dc729067b86883fba57a8a9685c$lut for cells of type $lut. Using template $paramod$63e56625bd8b4357319cae98121ea54ab3ced1c8$lut for cells of type $lut. Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14$lut for cells of type $lut. Using template $paramod$78b62a6e937ed8d20e95d0c21d3c6b72164987db$lut for cells of type $lut. Using template $paramod$8416b0e04f4a00cddd7b4f001da8b3538f88bc4a$lut for cells of type $lut. Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c$lut for cells of type $lut. Using template $paramod$7614968db5bb082ee538195c00594779836d04ec$lut for cells of type $lut. Using template $paramod$9932b99925d7f134cb9d84d0da052f854f6d96ed$lut for cells of type $lut. Using template $paramod$1b6226c8f59d99a6b6251fb4b2e76a7f4df33557$lut for cells of type $lut. Using template $paramod$cfecb0d666640a328030204dc9a3c069dcb55a3f$lut for cells of type $lut. Using template $paramod$4417ee9d522d528c95298dc7af04cb46cc36dff1$lut for cells of type $lut. Using template $paramod$e3ecee59b588264568c6cd99ce11a9e797607643$lut for cells of type $lut. Using template $paramod$a4cee2ea03a113fee43cd0560186e46f4fd6e97a$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101001 for cells of type $lut. Using template $paramod$1e3b9c388d992d6292f19f73604445c5432a0fd5$lut for cells of type $lut. Using template $paramod$7995a2c104c170dc46f114319297e91a40fbc922$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod$12618d2e4f24227d6f46ca347b63e1113d3c5831$lut for cells of type $lut. Using template $paramod$0e52967f8cb8db09e850a386eb25afa2c3424b54$lut for cells of type $lut. Using template $paramod$c2ecef3cf446a40c62c76833beda9834875c7ddb$lut for cells of type $lut. Using template $paramod$5d29e257b4653fa80f99db7cfa1ebec75bed3f76$lut for cells of type $lut. Using template $paramod$8a047b42185580b302ff851e1496cda5ca02925f$lut for cells of type $lut. Using template $paramod$0c67c2aca3b17469759da89c8e7a6b48929814ac$lut for cells of type $lut. Using template $paramod$79dccda09c8bc5c2a09f8a31837474a75e4e3562$lut for cells of type $lut. Using template $paramod$4cf3f705f102f73232294a18562351941c57e93e$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$343b2d4de53f67b7cc6b6094507cb4fb2c989ec1$lut for cells of type $lut. Using template $paramod$69f20e0703606f2ffd2ee27cd26f815bd5eeb6e9$lut for cells of type $lut. Using template $paramod$bff35d97b07dddb273c72678bf847e2b78003681$lut for cells of type $lut. Using template $paramod$f5c97e291c8b48d9f1b4239d871ab7639e5a24ac$lut for cells of type $lut. Using template $paramod$e45ac68972aa862408f371578ac45a3230e08aea$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001011 for cells of type $lut. Using template $paramod$56b03bb16189d0df5732f97659a58f26b0c9c41a$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. Using template $paramod$8159bff29d16755cfec2a140794dcb1334b008f5$lut for cells of type $lut. Using template $paramod$b3752e60ceb4e0c7539ea893d531051a3ae929d2$lut for cells of type $lut. Using template $paramod$5161a06bb2997376f642a3e15d574d873eff5b7c$lut for cells of type $lut. Using template $paramod$693bc3640a7517b313143c1e8f94a197396bd107$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111110 for cells of type $lut. Using template $paramod$795a66f7571cc04fcb50d0acdeed125edeb90178$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. Using template $paramod$2ae403fe30916063c9df1b961d28b5e497ee4d7b$lut for cells of type $lut. Using template $paramod$ca1d48527df516f209cb40a6149324209c84bc69$lut for cells of type $lut. Using template $paramod$fc2be7cf2aa1cfc8ebe963e124f1c70016e3f0fb$lut for cells of type $lut. Using template $paramod$db8db474b37e953931e1169179c91732f063f7cd$lut for cells of type $lut. Using template $paramod$527a49ee92a7492ecbd31cc616936e3d2d730451$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100011 for cells of type $lut. Using template $paramod$cc52c71d6b4b92e8d4039fa54e0e23337e73d354$lut for cells of type $lut. Using template $paramod$fe770a957c1c7e0fbad66c28d4586e67ab1a7b84$lut for cells of type $lut. Using template $paramod$af2f5d4c7f871436809f48511cd579a6a047c5fa$lut for cells of type $lut. Using template $paramod$b572a17bfa464a5e9eb4fa5b87f66c8c9ee2ad3d$lut for cells of type $lut. Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a$lut for cells of type $lut. Using template $paramod$08fd4020cd2baca07435bdd0ff1e32cea14b1d5e$lut for cells of type $lut. Using template $paramod$deb4f121bbf3d55ed9a98f692fd112e0918f51b5$lut for cells of type $lut. Using template $paramod$5d42bfd104cad6e58fa42e21e475b5263381cc4e$lut for cells of type $lut. Using template $paramod$9848c8049341a19a43eb88aef4f83593e1fcd91d$lut for cells of type $lut. Using template $paramod$32255ed2c6ec5e20561c9a955b29db1e8e93cf16$lut for cells of type $lut. Using template $paramod$de42ff02308cbe493c30367bfb1bbdca04aff45b$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$97bd0dd63f3e29ccbf5082d459a34ac44dd6d2f7$lut for cells of type $lut. Using template $paramod$2ba20dae1f5b67f6255349d80b9e53f8814c1740$lut for cells of type $lut. Using template $paramod$c6932d0419018208e5384761d78f0ead9bcc772f$lut for cells of type $lut. Using template $paramod$569f719f7029733dd7c821be0c201b5e8cd3f2ba$lut for cells of type $lut. Using template $paramod$3f1d058bc5620e18d97ee06a3fba19b893781242$lut for cells of type $lut. Using template $paramod$74072391a38204da28652968e8c23f7bfd602b77$lut for cells of type $lut. Using template $paramod$a2ea0d74a20d4a676623fa48a36ccb82962e1de6$lut for cells of type $lut. Using template $paramod$d7f4570f04f68175b1fa25c1bac92938027a2c96$lut for cells of type $lut. No more expansions possible. 2.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in top_flopoco_mul_we8_wf35_zynq7000_native_f500. Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125286.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125323.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125217.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125077.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125358.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125358.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125030.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125030.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125121.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125121.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125417.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125417.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125417.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125030.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125030.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125037.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125346.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125077.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125081.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125121.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125163.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125077.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125249.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125262.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125271.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125285.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125319.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125358.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125375.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125404.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125417.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125459.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125564.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125581.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125657.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$125017$auto$blifparse.cc:557:parse_blif$125660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Removed 0 unused cells and 1687 unused wires. 2.50. Executing AUTONAME pass. Renamed 5099 objects in module top_flopoco_mul_we8_wf35_zynq7000_native_f500 (705 iterations). 2.51. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `top_flopoco_mul_we8_wf35_zynq7000_native_f500'. Setting top module to top_flopoco_mul_we8_wf35_zynq7000_native_f500. 2.51.1. Analyzing design hierarchy.. Top module: \top_flopoco_mul_we8_wf35_zynq7000_native_f500 2.51.2. Analyzing design hierarchy.. Top module: \top_flopoco_mul_we8_wf35_zynq7000_native_f500 Removed 0 unused modules. 2.52. Printing statistics. === top_flopoco_mul_we8_wf35_zynq7000_native_f500 === +----------Local Count, excluding submodules. | 3457 wires 15127 wire bits 3457 public wires 15127 public wire bits 4 ports 139 port bits 183 cells 177 $scopeinfo 6 MULT18X18D 2940 submodules 107 CCU2C 137 L6MUX21 1200 LUT4 389 PFUMX 1107 TRELLIS_FF === design hierarchy === +----------Count including submodules. | 183 top_flopoco_mul_we8_wf35_zynq7000_native_f500 +----------Count including submodules. | 3457 wires 15127 wire bits 3457 public wires 15127 public wire bits 4 ports 139 port bits - memories - memory bits - processes 183 cells 177 $scopeinfo 6 MULT18X18D 2940 submodules 107 CCU2C 137 L6MUX21 1200 LUT4 389 PFUMX 1107 TRELLIS_FF 2.53. Executing CHECK pass (checking for obvious problems). Checking module top_flopoco_mul_we8_wf35_zynq7000_native_f500... Found and reported 0 problems. 2.54. Executing JSON backend. End of script. Logfile hash: 3e39573b06, time: 22.31s, user: 19.53s, system: 0.33s, MEM: 195.77 MB peak Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3) Time spent: 25% 3x abc (6 sec), 18% 39x opt_expr (4 sec), ... $ yosys -m ghdl -s /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/flopoco_mul_we8_wf35_zynq7000_native_f500/yosys.ys [exit code 0]