****** Vivado v2025.2.1 (64-bit) **** SW Build 6403652 on Thu Mar 19 13:47:00 MDT 2026 **** IP Build 6403511 on Thu Mar 19 12:41:45 MDT 2026 **** SharedData Build 6403650 on Thu Mar 19 14:02:13 MDT 2026 **** Start of session at: Sun May 24 14:44:14 2026 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved. source /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m17_large_p2/vivado.tcl -notrace read_xdc: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1583.121 ; gain = 8.027 ; free physical = 8296 ; free virtual = 20822 Command: synth_design -top top_tommath_div_e8_m17_large_p2 -part xc7s50csga324-1 -mode out_of_context -flatten_hierarchy rebuilt Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7s50' INFO: [Device 21-403] Loading part xc7s50csga324-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 1 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 354368 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.590 ; gain = 482.188 ; free physical = 7479 ; free virtual = 20006 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'top_tommath_div_e8_m17_large_p2' [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m17_large_p2/src/top_tommath_div_e8_m17_large_p2.v:3] INFO: [Synth 8-6157] synthesizing module 'FpxxDiv' [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m17_large_p2/src/tommath_div_e8_m17_large_p2.v:7] INFO: [Synth 8-3876] $readmem data file 'FpxxDiv.v_toplevel_div_table.bin' is read successfully [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m17_large_p2/src/tommath_div_e8_m17_large_p2.v:133] INFO: [Synth 8-6155] done synthesizing module 'FpxxDiv' (0#1) [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m17_large_p2/src/tommath_div_e8_m17_large_p2.v:7] INFO: [Synth 8-6155] done synthesizing module 'top_tommath_div_e8_m17_large_p2' (0#1) [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m17_large_p2/src/top_tommath_div_e8_m17_large_p2.v:3] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2281.559 ; gain = 570.156 ; free physical = 7386 ; free virtual = 19914 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2296.402 ; gain = 585.000 ; free physical = 7374 ; free virtual = 19902 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2296.402 ; gain = 585.000 ; free physical = 7374 ; free virtual = 19902 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2296.402 ; gain = 0.000 ; free physical = 7374 ; free virtual = 19902 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m17_large_p2/constraints.xdc] Finished Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m17_large_p2/constraints.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2374.121 ; gain = 0.000 ; free physical = 7299 ; free virtual = 19826 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2374.156 ; gain = 0.000 ; free physical = 7299 ; free virtual = 19826 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2374.156 ; gain = 662.754 ; free physical = 7297 ; free virtual = 19825 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7s50csga324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2382.125 ; gain = 670.723 ; free physical = 7297 ; free virtual = 19825 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2382.125 ; gain = 670.723 ; free physical = 7297 ; free virtual = 19825 --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element div_p5_reg was removed. [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m17_large_p2/src/tommath_div_e8_m17_large_p2.v:129] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 2382.125 ; gain = 670.723 ; free physical = 7297 ; free virtual = 19826 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 3 Input 18 Bit Adders := 1 3 Input 10 Bit Adders := 1 2 Input 10 Bit Adders := 1 3 Input 9 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 1 +---Registers : 48 Bit Registers := 1 36 Bit Registers := 1 26 Bit Registers := 3 21 Bit Registers := 1 20 Bit Registers := 1 18 Bit Registers := 3 17 Bit Registers := 2 10 Bit Registers := 4 9 Bit Registers := 1 5 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 27 +---ROMs : ROMs := 1 +---Muxes : 2 Input 35 Bit Muxes := 1 2 Input 17 Bit Muxes := 3 2 Input 8 Bit Muxes := 3 4 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 3 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 120 (col length:60) BRAMs: 150 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element div_p5_reg was removed. [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m17_large_p2/src/tommath_div_e8_m17_large_p2.v:129] WARNING: [Synth 8-3936] Found unconnected internal register 'div_p5_reg' and it is trimmed from '48' to '25' bits. [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m17_large_p2/src/tommath_div_e8_m17_large_p2.v:129] DSP Report: Generating DSP x_mul_yhyl_p3_reg, operation Mode is: (C+A*B)'. DSP Report: register x_mul_yhyl_p3_reg is absorbed into DSP x_mul_yhyl_p3_reg. DSP Report: operator x_mul_yhyl_full_p2 is absorbed into DSP x_mul_yhyl_p3_reg. DSP Report: operator x_mul_yhyl_full_p2 is absorbed into DSP x_mul_yhyl_p3_reg. DSP Report: Generating DSP div_full_p4, operation Mode is: A''*B2. DSP Report: register div_full_p4 is absorbed into DSP div_full_p4. DSP Report: register div_full_p4 is absorbed into DSP div_full_p4. DSP Report: register div_full_p4 is absorbed into DSP div_full_p4. DSP Report: operator div_full_p4 is absorbed into DSP div_full_p4. DSP Report: operator div_full_p4 is absorbed into DSP div_full_p4. DSP Report: Generating DSP div_p5_reg, operation Mode is: (PCIN>>17)+A''*B2. DSP Report: register div_p5_reg is absorbed into DSP div_p5_reg. DSP Report: register div_p5_reg is absorbed into DSP div_p5_reg. DSP Report: register div_p5_reg is absorbed into DSP div_p5_reg. DSP Report: register div_p5_reg is absorbed into DSP div_p5_reg. DSP Report: operator div_full_p4 is absorbed into DSP div_p5_reg. DSP Report: operator div_full_p4 is absorbed into DSP div_p5_reg. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2382.125 ; gain = 670.723 ; free physical = 7299 ; free virtual = 19828 --------------------------------------------------------------------------------- Sort Area is div_full_p4_2 : 0 0 : 3190 3985 : Used 1 time 0 Sort Area is div_full_p4_2 : 0 1 : 795 3985 : Used 1 time 0 Sort Area is x_mul_yhyl_p3_reg_0 : 0 0 : 2424 2424 : Used 1 time 0 --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- ROM: Preliminary Mapping Report +------------+-------------------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------+-------------------------+---------------+----------------+ |FpxxDiv | _zz_div_table_port0_reg | 512x20 | Block RAM | +------------+-------------------------+---------------+----------------+ DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set) +------------+-------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | +------------+-------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |FpxxDiv | (C+A*B)' | 18 | 17 | 35 | - | 36 | 0 | 0 | 0 | - | - | 0 | 1 | |FpxxDiv | A''*B2 | 22 | 18 | - | - | 48 | 2 | 1 | - | - | - | 0 | 0 | |FpxxDiv | (PCIN>>17)+A''*B2 | 22 | 5 | - | - | 25 | 2 | 1 | - | - | - | 0 | 1 | +------------+-------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2470.125 ; gain = 758.723 ; free physical = 7225 ; free virtual = 19754 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2471.125 ; gain = 759.723 ; free physical = 7225 ; free virtual = 19754 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2500.172 ; gain = 788.770 ; free physical = 7205 ; free virtual = 19734 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2671.984 ; gain = 960.582 ; free physical = 7030 ; free virtual = 19559 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2671.984 ; gain = 960.582 ; free physical = 7030 ; free virtual = 19559 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2671.984 ; gain = 960.582 ; free physical = 7030 ; free virtual = 19559 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2671.984 ; gain = 960.582 ; free physical = 7030 ; free virtual = 19559 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2674.953 ; gain = 963.551 ; free physical = 7026 ; free virtual = 19555 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2674.953 ; gain = 963.551 ; free physical = 7026 ; free virtual = 19555 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- DSP Final Report (the ' indicates corresponding REG is set) +------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | +------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |FpxxDiv | (C+A*B'')' | 18 | 17 | 35 | - | 36 | 0 | 2 | 0 | - | - | 0 | 1 | |FpxxDiv | A''*B' | 21 | 17 | - | - | 0 | 2 | 1 | - | - | - | 0 | 0 | |FpxxDiv | (PCIN>>17+A''*B')' | 21 | 4 | - | - | 25 | 2 | 1 | - | - | - | 0 | 1 | +------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |CARRY4 | 11| |2 |DSP48E1 | 3| |5 |LUT1 | 17| |6 |LUT2 | 36| |7 |LUT3 | 6| |8 |LUT4 | 25| |9 |LUT5 | 14| |10 |LUT6 | 39| |11 |RAMB18E1 | 1| |12 |FDCE | 5| |13 |FDRE | 187| +------+---------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2674.953 ; gain = 963.551 ; free physical = 7026 ; free virtual = 19555 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 3 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 2674.953 ; gain = 885.797 ; free physical = 7026 ; free virtual = 19555 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2674.961 ; gain = 963.551 ; free physical = 7026 ; free virtual = 19555 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2674.961 ; gain = 0.000 ; free physical = 7026 ; free virtual = 19555 INFO: [Netlist 29-17] Analyzing 15 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m17_large_p2/constraints.xdc] Finished Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m17_large_p2/constraints.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2674.961 ; gain = 0.000 ; free physical = 7197 ; free virtual = 19726 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Synth Design complete | Checksum: d5b6bd0d INFO: [Common 17-83] Releasing license: Synthesis 19 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:29 . Memory (MB): peak = 2674.988 ; gain = 1091.867 ; free physical = 7197 ; free virtual = 19725 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2170.837; main = 2170.837; forked = 359.631 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3463.164; main = 2674.957; forked = 1018.035 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7s50' Running DRC as a precondition to command opt_design Starting DRC Task WARNING: [DRC 23-814] Not all possible (connectivity based) DRCs may have been run because this design is seen as Out of Context. INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2674.988 ; gain = 0.000 ; free physical = 7206 ; free virtual = 19734 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 22f909b76 Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2674.988 ; gain = 0.000 ; free physical = 7185 ; free virtual = 19714 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 22f909b76 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2674.988 ; gain = 0.000 ; free physical = 7173 ; free virtual = 19701 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 22f909b76 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2674.988 ; gain = 0.000 ; free physical = 7173 ; free virtual = 19701 Phase 1 Initialization | Checksum: 22f909b76 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2674.988 ; gain = 0.000 ; free physical = 7173 ; free virtual = 19701 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Detect if minReqCache needed Phase 2.1 Detect if minReqCache needed | Checksum: 22f909b76 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2674.988 ; gain = 0.000 ; free physical = 7173 ; free virtual = 19701 Phase 2.2 Timer Update Phase 2.2 Timer Update | Checksum: 22f909b76 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2674.988 ; gain = 0.000 ; free physical = 7173 ; free virtual = 19701 Phase 2 Timer Update And Timing Data Collection | Checksum: 22f909b76 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2674.988 ; gain = 0.000 ; free physical = 7173 ; free virtual = 19701 Phase 3 Retarget INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 1bbd0fdbc Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2674.988 ; gain = 0.000 ; free physical = 7173 ; free virtual = 19701 Retarget | Checksum: 1bbd0fdbc INFO: [Opt 31-389] Phase Retarget created 1 cells and removed 1 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 1bbd0fdbc Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2674.988 ; gain = 0.000 ; free physical = 7173 ; free virtual = 19701 Constant propagation | Checksum: 1bbd0fdbc INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2674.988 ; gain = 0.000 ; free physical = 7173 ; free virtual = 19701 Phase 5 Sweep | Checksum: 10320437c Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2674.988 ; gain = 0.000 ; free physical = 7173 ; free virtual = 19701 Sweep | Checksum: 10320437c INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Sweep, 160 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 10320437c Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2706.969 ; gain = 31.980 ; free physical = 7173 ; free virtual = 19701 BUFG optimization | Checksum: 10320437c INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 10320437c Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2706.969 ; gain = 31.980 ; free physical = 7173 ; free virtual = 19701 Shift Register Optimization | Checksum: 10320437c INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 10320437c Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2706.969 ; gain = 31.980 ; free physical = 7173 ; free virtual = 19701 Post Processing Netlist | Checksum: 10320437c INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 240685230 Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2706.969 ; gain = 31.980 ; free physical = 7173 ; free virtual = 19701 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2706.969 ; gain = 0.000 ; free physical = 7173 ; free virtual = 19701 Phase 9.2 Verifying Netlist Connectivity | Checksum: 240685230 Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2706.969 ; gain = 31.980 ; free physical = 7173 ; free virtual = 19701 Phase 9 Finalization | Checksum: 240685230 Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2706.969 ; gain = 31.980 ; free physical = 7173 ; free virtual = 19701 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 1 | 1 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 0 | 160 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 240685230 Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2706.969 ; gain = 31.980 ; free physical = 7173 ; free virtual = 19701 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 1 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 2 Ending PowerOpt Patch Enables Task | Checksum: 240685230 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7172 ; free virtual = 19701 Ending Power Optimization Task | Checksum: 240685230 Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2777.996 ; gain = 71.027 ; free physical = 7172 ; free virtual = 19701 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 240685230 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7172 ; free virtual = 19701 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7172 ; free virtual = 19701 INFO: [Common 17-83] Releasing license: Implementation 46 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2777.996 ; gain = 103.008 ; free physical = 7172 ; free virtual = 19701 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-83] Releasing license: Implementation WARNING: [DRC 23-814] Not all possible (connectivity based) DRCs may have been run because this design is seen as Out of Context. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Timing 38-35] Done setting XDC timing constraints. Running DRC as a precondition to command place_design WARNING: [DRC 23-814] Not all possible (connectivity based) DRCs may have been run because this design is seen as Out of Context. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7170 ; free virtual = 19699 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1a50fb31e Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7170 ; free virtual = 19699 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7170 ; free virtual = 19699 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1528733b8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7170 ; free virtual = 19699 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 23f869015 Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7174 ; free virtual = 19703 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 23f869015 Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7174 ; free virtual = 19703 Phase 1 Placer Initialization | Checksum: 23f869015 Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7174 ; free virtual = 19703 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 18ce9036d Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7174 ; free virtual = 19703 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1dd4f8fb5 Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7174 ; free virtual = 19703 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 1dd4f8fb5 Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7174 ; free virtual = 19703 Phase 2.4 Global Place Phase1 Phase 2.4 Global Place Phase1 | Checksum: 164e4ed1e Time (s): cpu = 00:00:00.86 ; elapsed = 00:00:00.91 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7174 ; free virtual = 19702 Phase 2.5 Global Place Phase2 Phase 2.5.1 UpdateTiming Before Physical Synthesis Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 164e4ed1e Time (s): cpu = 00:00:00.89 ; elapsed = 00:00:00.94 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7174 ; free virtual = 19702 Phase 2.5.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 17 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 8 nets or LUTs. Breaked 0 LUT, combined 8 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 8 | 8 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 8 | 8 | 0 | 4 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.5.2 Physical Synthesis In Placer | Checksum: 117085310 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 2.5 Global Place Phase2 | Checksum: 16b6ae60d Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 2 Global Placement | Checksum: 16b6ae60d Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1cf1bfa97 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2734546a8 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 242a34e3b Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1dec3f878 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 237e5d1f7 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1f5e5f779 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 15967226c Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 3 Detail Placement | Checksum: 15967226c Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 20d165476 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.922 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 19d713fa8 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 295f7e636 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 4.1.1.1 BUFG Insertion | Checksum: 20d165476 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=0.922. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 2c1c7ec73 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 4.1 Post Commit Optimization | Checksum: 2c1c7ec73 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 2c1c7ec73 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 1x1| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 2c1c7ec73 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 4.3 Placer Reporting | Checksum: 2c1c7ec73 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1e6344ef2 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7191 ; free virtual = 19720 Ending Placer Task | Checksum: 11f0ba9a3 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7190 ; free virtual = 19719 72 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7s50' Starting Routing Task Phase 1 Build RT Design Checksum: PlaceDB: 606c80aa ConstDB: 0 ShapeSum: 140df5c3 RouteDB: aa913336 WARNING: [Route 35-197] Clock port "clk" does not have an associated HD.CLK_SRC. Without this constraint, timing analysis may not be accurate and upstream checks cannot be done to ensure correct clock placement. WARNING: [Route 35-198] Port "rst" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "rst". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[25]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[25]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[25]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[25]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[15]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[15]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[13]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[13]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[11]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[11]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "in_valid_i" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "in_valid_i". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[24]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[24]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[22]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[22]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[24]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[24]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[23]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[23]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[19]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[19]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[12]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[12]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[9]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[9]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[20]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[20]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[19]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[19]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[18]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[18]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[17]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[17]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[17]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[17]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[16]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[16]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[23]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[23]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[21]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[21]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[22]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[22]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[21]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[21]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[14]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[14]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[12]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[12]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[11]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[11]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[8]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[8]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[16]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[16]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[15]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[15]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[20]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[20]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[18]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[18]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[8]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[8]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[9]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[9]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[14]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[14]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[7]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[7]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[7]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[7]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[6]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[6]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[5]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[5]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[13]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[13]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[6]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[6]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[5]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[5]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "a_i[3]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "a_i[3]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[3]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[3]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "b_i[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "b_i[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Constraints 18-8777] Unable to split tiles. All required files are not available. Post Restoration Checksum: NetGraph: c220284 | NumContArr: 5ca18eb4 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 1ee158672 Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7198 ; free virtual = 19727 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1ee158672 Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7198 ; free virtual = 19727 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1ee158672 Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7198 ; free virtual = 19727 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 2df429970 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7198 ; free virtual = 19727 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.922 | TNS=0.000 | WHS=0.104 | THS=0.000 | Phase 2.4 Soft Constraint Pins - Fast Budgeting Phase 2.4 Soft Constraint Pins - Fast Budgeting | Checksum: 2e8eb1ea5 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7198 ; free virtual = 19727 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 371 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 371 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 2 Router Initialization | Checksum: 2e8eb1ea5 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7198 ; free virtual = 19727 Phase 3 Global Routing Phase 3 Global Routing | Checksum: 2e8eb1ea5 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7198 ; free virtual = 19727 Phase 4 Initial Routing Phase 4.1 Initial Net Routing Pass Phase 4.1 Initial Net Routing Pass | Checksum: 2af93913d Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7200 ; free virtual = 19729 Phase 4 Initial Routing | Checksum: 2af93913d Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7200 ; free virtual = 19729 Phase 5 Rip-up And Reroute Phase 5.1 Global Iteration 0 Number of Nodes with overlaps = 24 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.922 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 5.1 Global Iteration 0 | Checksum: 359ebeb29 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7200 ; free virtual = 19729 Phase 5 Rip-up And Reroute | Checksum: 359ebeb29 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7200 ; free virtual = 19729 Phase 6 Delay and Skew Optimization Phase 6.1 Delay CleanUp Phase 6.1 Delay CleanUp | Checksum: 359ebeb29 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7200 ; free virtual = 19729 Phase 6.2 Clock Skew Optimization Phase 6.2 Clock Skew Optimization | Checksum: 359ebeb29 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7200 ; free virtual = 19729 Phase 6 Delay and Skew Optimization | Checksum: 359ebeb29 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7200 ; free virtual = 19729 Phase 7 Post Hold Fix Phase 7.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.922 | TNS=0.000 | WHS=0.106 | THS=0.000 | Phase 7.1 Hold Fix Iter | Checksum: 2d5a48b1d Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7200 ; free virtual = 19729 Phase 7 Post Hold Fix | Checksum: 2d5a48b1d Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7200 ; free virtual = 19729 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0521406 % Global Horizontal Routing Utilization = 0.0715773 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 8 Route finalize | Checksum: 2d5a48b1d Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7200 ; free virtual = 19729 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 2d5a48b1d Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7200 ; free virtual = 19729 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 2bf64d847 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7200 ; free virtual = 19729 Phase 11 Post Process Routing Phase 11 Post Process Routing | Checksum: 2bf64d847 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7200 ; free virtual = 19729 Phase 12 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=0.922 | TNS=0.000 | WHS=0.106 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 12 Post Router Timing | Checksum: 2bf64d847 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7200 ; free virtual = 19729 Total Elapsed time in route_design: 16.37 secs Phase 13 Post-Route Event Processing Phase 13 Post-Route Event Processing | Checksum: 12955c2ed Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7200 ; free virtual = 19729 INFO: [Route 35-16] Router Completed Successfully Ending Routing Task | Checksum: 12955c2ed Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7200 ; free virtual = 19729 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 80 Infos, 62 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7200 ; free virtual = 19729 INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7195 ; free virtual = 19725 Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7195 ; free virtual = 19725 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7195 ; free virtual = 19725 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7195 ; free virtual = 19725 Wrote PlaceStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7195 ; free virtual = 19725 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7195 ; free virtual = 19725 Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7194 ; free virtual = 19724 Write Physdb Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2777.996 ; gain = 0.000 ; free physical = 7194 ; free virtual = 19724 INFO: [Common 17-1381] The checkpoint '/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m17_large_p2/post_route.dcp' has been generated. INFO: [Common 17-206] Exiting Vivado at Sun May 24 14:45:19 2026... $ /mnt/storage/xilinx/2025.2.1/Vivado/bin/vivado -mode batch -nojournal -nolog -notrace -source /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m17_large_p2/vivado.tcl [exit code 0]