****** Vivado v2025.2.1 (64-bit) **** SW Build 6403652 on Thu Mar 19 13:47:00 MDT 2026 **** IP Build 6403511 on Thu Mar 19 12:41:45 MDT 2026 **** SharedData Build 6403650 on Thu Mar 19 14:02:13 MDT 2026 **** Start of session at: Sat May 23 23:22:03 2026 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved. source /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/vivado.tcl -notrace read_xdc: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1552.941 ; gain = 51.840 ; free physical = 8612 ; free virtual = 12590 Command: synth_design -top top_flopoco_add_we8_wf17_zynq7000_native_single_f200 -part xc7s50csga324-1 -mode out_of_context -flatten_hierarchy rebuilt Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7s50' INFO: [Device 21-403] Loading part xc7s50csga324-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 1 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 188275 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2194.379 ; gain = 483.188 ; free physical = 9305 ; free virtual = 13283 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top_flopoco_add_we8_wf17_zynq7000_native_single_f200' [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/top_flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:13] INFO: [Synth 8-638] synthesizing module 'flopoco_add_we8_wf17_zynq7000_native_single_f200' [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:329] INFO: [Synth 8-3491] module 'RightShifterSticky18_by_max_20_Freq200_uid4' declared at '/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:24' bound to instance 'RightShifterComponent' of component 'RightShifterSticky18_by_max_20_Freq200_uid4' [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:512] INFO: [Synth 8-638] synthesizing module 'RightShifterSticky18_by_max_20_Freq200_uid4' [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:32] INFO: [Synth 8-256] done synthesizing module 'RightShifterSticky18_by_max_20_Freq200_uid4' (0#1) [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:32] INFO: [Synth 8-3491] module 'IntAdder_21_Freq200_uid6' declared at '/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:113' bound to instance 'fracAdder' of component 'IntAdder_21_Freq200_uid6' [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:523] INFO: [Synth 8-638] synthesizing module 'IntAdder_21_Freq200_uid6' [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:121] INFO: [Synth 8-256] done synthesizing module 'IntAdder_21_Freq200_uid6' (0#1) [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:121] INFO: [Synth 8-3491] module 'Normalizer_Z_22_22_22_Freq200_uid8' declared at '/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:173' bound to instance 'LZCAndShifter' of component 'Normalizer_Z_22_22_22_Freq200_uid8' [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:530] INFO: [Synth 8-638] synthesizing module 'Normalizer_Z_22_22_22_Freq200_uid8' [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:180] INFO: [Synth 8-256] done synthesizing module 'Normalizer_Z_22_22_22_Freq200_uid8' (0#1) [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:180] INFO: [Synth 8-3491] module 'IntAdder_28_Freq200_uid11' declared at '/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:259' bound to instance 'roundingAdder' of component 'IntAdder_28_Freq200_uid11' [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:544] INFO: [Synth 8-638] synthesizing module 'IntAdder_28_Freq200_uid11' [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:267] INFO: [Synth 8-256] done synthesizing module 'IntAdder_28_Freq200_uid11' (0#1) [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:267] INFO: [Synth 8-256] done synthesizing module 'flopoco_add_we8_wf17_zynq7000_native_single_f200' (0#1) [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:329] INFO: [Synth 8-256] done synthesizing module 'top_flopoco_add_we8_wf17_zynq7000_native_single_f200' (0#1) [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/top_flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:13] WARNING: [Synth 8-3936] Found unconnected internal register 'level3_d1_reg' and it is trimmed from '20' to '4' bits. [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:68] WARNING: [Synth 8-3936] Found unconnected internal register 'level4_d1_reg' and it is trimmed from '20' to '8' bits. [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:67] WARNING: [Synth 8-3936] Found unconnected internal register 'ps_d1_reg' and it is trimmed from '5' to '4' bits. [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:65] WARNING: [Synth 8-3936] Found unconnected internal register 'X_1_d2_reg' and it is trimmed from '22' to '21' bits. [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:138] WARNING: [Synth 8-3936] Found unconnected internal register 'X_1_d1_reg' and it is trimmed from '22' to '21' bits. [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:137] WARNING: [Synth 8-3936] Found unconnected internal register 'Y_1_d1_reg' and it is trimmed from '22' to '21' bits. [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:139] WARNING: [Synth 8-3936] Found unconnected internal register 'X_1_d1_reg' and it is trimmed from '29' to '28' bits. [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:283] WARNING: [Synth 8-3936] Found unconnected internal register 'Y_1_d4_reg' and it is trimmed from '29' to '28' bits. [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:287] WARNING: [Synth 8-3936] Found unconnected internal register 'Y_1_d3_reg' and it is trimmed from '29' to '28' bits. [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:286] WARNING: [Synth 8-3936] Found unconnected internal register 'Y_1_d2_reg' and it is trimmed from '29' to '28' bits. [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:285] WARNING: [Synth 8-3936] Found unconnected internal register 'Y_1_d1_reg' and it is trimmed from '29' to '28' bits. [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/src/flopoco_add_we8_wf17_zynq7000_native_single_f200.vhdl:284] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2283.348 ; gain = 572.156 ; free physical = 8962 ; free virtual = 12941 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2295.223 ; gain = 584.031 ; free physical = 8948 ; free virtual = 12928 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2295.223 ; gain = 584.031 ; free physical = 8948 ; free virtual = 12928 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2295.223 ; gain = 0.000 ; free physical = 8948 ; free virtual = 12928 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/constraints.xdc] Finished Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/constraints.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2369.941 ; gain = 0.000 ; free physical = 8864 ; free virtual = 12843 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2369.977 ; gain = 0.000 ; free physical = 8864 ; free virtual = 12843 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2369.977 ; gain = 658.785 ; free physical = 10320 ; free virtual = 14299 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7s50csga324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2377.945 ; gain = 666.754 ; free physical = 10312 ; free virtual = 14291 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2377.945 ; gain = 666.754 ; free physical = 10321 ; free virtual = 14300 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2377.945 ; gain = 666.754 ; free physical = 10296 ; free virtual = 14275 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 3 Input 28 Bit Adders := 1 3 Input 21 Bit Adders := 1 3 Input 10 Bit Adders := 1 2 Input 9 Bit Adders := 1 3 Input 8 Bit Adders := 1 +---XORs : 2 Input 21 Bit XORs := 1 2 Input 1 Bit XORs := 1 +---Registers : 28 Bit Registers := 8 22 Bit Registers := 1 21 Bit Registers := 4 20 Bit Registers := 1 9 Bit Registers := 3 8 Bit Registers := 1 4 Bit Registers := 2 2 Bit Registers := 4 1 Bit Registers := 16 +---Muxes : 2 Input 28 Bit Muxes := 2 2 Input 22 Bit Muxes := 5 2 Input 20 Bit Muxes := 6 2 Input 18 Bit Muxes := 1 2 Input 8 Bit Muxes := 2 2 Input 5 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 5 Input 2 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 120 (col length:60) BRAMs: 150 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2377.945 ; gain = 666.754 ; free physical = 11680 ; free virtual = 15663 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2425.945 ; gain = 714.754 ; free physical = 13345 ; free virtual = 17332 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2448.977 ; gain = 737.785 ; free physical = 13299 ; free virtual = 17286 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2464.992 ; gain = 753.801 ; free physical = 13236 ; free virtual = 17223 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2624.805 ; gain = 913.613 ; free physical = 12379 ; free virtual = 16370 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2624.805 ; gain = 913.613 ; free physical = 12379 ; free virtual = 16370 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2624.805 ; gain = 913.613 ; free physical = 12316 ; free virtual = 16306 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2624.805 ; gain = 913.613 ; free physical = 12316 ; free virtual = 16306 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2624.805 ; gain = 913.613 ; free physical = 12304 ; free virtual = 16294 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2624.805 ; gain = 913.613 ; free physical = 12300 ; free virtual = 16290 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +-----------------------------------------------------+--------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +-----------------------------------------------------+--------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top_flopoco_add_we8_wf17_zynq7000_native_single_f200 | u_dut/excRt_d4_reg[1] | 4 | 2 | NO | NO | YES | 2 | 0 | |top_flopoco_add_we8_wf17_zynq7000_native_single_f200 | u_dut/extendedExpInc_d3_reg[8] | 3 | 9 | NO | NO | YES | 9 | 0 | |top_flopoco_add_we8_wf17_zynq7000_native_single_f200 | u_dut/signR_d3_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +-----------------------------------------------------+--------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |CARRY4 | 22| |2 |LUT1 | 5| |3 |LUT2 | 45| |4 |LUT3 | 75| |5 |LUT4 | 42| |6 |LUT5 | 47| |7 |LUT6 | 91| |8 |SRL16E | 12| |9 |FDRE | 249| +------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2624.805 ; gain = 913.613 ; free physical = 12300 ; free virtual = 16290 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 2624.805 ; gain = 838.859 ; free physical = 12229 ; free virtual = 16220 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2624.812 ; gain = 913.613 ; free physical = 12229 ; free virtual = 16220 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2624.812 ; gain = 0.000 ; free physical = 12210 ; free virtual = 16200 INFO: [Netlist 29-17] Analyzing 22 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/constraints.xdc] Finished Parsing XDC File [/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/constraints.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2624.812 ; gain = 0.000 ; free physical = 12245 ; free virtual = 16236 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Synth Design complete | Checksum: e010d11d INFO: [Common 17-83] Releasing license: Synthesis 30 Infos, 11 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2624.840 ; gain = 1071.898 ; free physical = 12235 ; free virtual = 16226 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1692.898; main = 1621.052; forked = 237.221 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3425.004; main = 2624.809; forked = 1018.055 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7s50' Running DRC as a precondition to command opt_design Starting DRC Task WARNING: [DRC 23-814] Not all possible (connectivity based) DRCs may have been run because this design is seen as Out of Context. INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.53 . Memory (MB): peak = 2624.840 ; gain = 0.000 ; free physical = 12224 ; free virtual = 16214 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1f7b39c6b Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2624.840 ; gain = 0.000 ; free physical = 10834 ; free virtual = 14826 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 1f7b39c6b Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2662.805 ; gain = 0.000 ; free physical = 10121 ; free virtual = 14114 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1f7b39c6b Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2662.805 ; gain = 0.000 ; free physical = 10121 ; free virtual = 14114 Phase 1 Initialization | Checksum: 1f7b39c6b Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2662.805 ; gain = 0.000 ; free physical = 10121 ; free virtual = 14114 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Detect if minReqCache needed Phase 2.1 Detect if minReqCache needed | Checksum: 1f7b39c6b Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2662.805 ; gain = 0.000 ; free physical = 10121 ; free virtual = 14114 Phase 2.2 Timer Update Phase 2.2 Timer Update | Checksum: 1f7b39c6b Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2662.805 ; gain = 0.000 ; free physical = 10121 ; free virtual = 14114 Phase 2 Timer Update And Timing Data Collection | Checksum: 1f7b39c6b Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2662.805 ; gain = 0.000 ; free physical = 10121 ; free virtual = 14114 Phase 3 Retarget INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 INFO: [Opt 31-1566] Pulled 1 inverters resulting in an inversion of 9 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 25d2db62f Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2662.805 ; gain = 0.000 ; free physical = 10113 ; free virtual = 14106 Retarget | Checksum: 25d2db62f INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 25d2db62f Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2662.805 ; gain = 0.000 ; free physical = 10113 ; free virtual = 14106 Constant propagation | Checksum: 25d2db62f INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2662.805 ; gain = 0.000 ; free physical = 10113 ; free virtual = 14106 Phase 5 Sweep | Checksum: 27363c812 Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2662.805 ; gain = 0.000 ; free physical = 10113 ; free virtual = 14106 Sweep | Checksum: 27363c812 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Sweep, 168 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 27363c812 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2694.820 ; gain = 32.016 ; free physical = 10113 ; free virtual = 14106 BUFG optimization | Checksum: 27363c812 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 27363c812 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2694.820 ; gain = 32.016 ; free physical = 10113 ; free virtual = 14106 Shift Register Optimization | Checksum: 27363c812 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 27363c812 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2694.820 ; gain = 32.016 ; free physical = 10113 ; free virtual = 14106 Post Processing Netlist | Checksum: 27363c812 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 13e195d88 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2694.820 ; gain = 32.016 ; free physical = 10105 ; free virtual = 14098 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 10105 ; free virtual = 14098 Phase 9.2 Verifying Netlist Connectivity | Checksum: 13e195d88 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2694.820 ; gain = 32.016 ; free physical = 10105 ; free virtual = 14098 Phase 9 Finalization | Checksum: 13e195d88 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2694.820 ; gain = 32.016 ; free physical = 10105 ; free virtual = 14098 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 1 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 0 | 168 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 13e195d88 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2694.820 ; gain = 32.016 ; free physical = 10105 ; free virtual = 14098 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 13e195d88 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 10099 ; free virtual = 14092 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 13e195d88 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 10099 ; free virtual = 14092 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 10099 ; free virtual = 14092 INFO: [Common 17-83] Releasing license: Implementation 53 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2694.820 ; gain = 69.980 ; free physical = 10099 ; free virtual = 14092 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-83] Releasing license: Implementation WARNING: [DRC 23-814] Not all possible (connectivity based) DRCs may have been run because this design is seen as Out of Context. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Timing 38-35] Done setting XDC timing constraints. Running DRC as a precondition to command place_design WARNING: [DRC 23-814] Not all possible (connectivity based) DRCs may have been run because this design is seen as Out of Context. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9910 ; free virtual = 13905 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 122065d47 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9910 ; free virtual = 13905 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9910 ; free virtual = 13905 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1b75deeda Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9885 ; free virtual = 13879 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 284ae3a87 Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9837 ; free virtual = 13831 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 284ae3a87 Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9837 ; free virtual = 13831 Phase 1 Placer Initialization | Checksum: 284ae3a87 Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9829 ; free virtual = 13823 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 2b36924c5 Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.54 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9817 ; free virtual = 13811 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 227c379d9 Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9809 ; free virtual = 13803 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 227c379d9 Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9809 ; free virtual = 13803 Phase 2.4 Global Place Phase1 Phase 2.4 Global Place Phase1 | Checksum: 243b40121 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9597 ; free virtual = 13591 Phase 2.5 Global Place Phase2 Phase 2.5.1 UpdateTiming Before Physical Synthesis Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 1f4054981 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9561 ; free virtual = 13555 Phase 2.5.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 9 LUTNM shape to break, 3 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 6, two critical 3, total 9, new lutff created 5 INFO: [Physopt 32-1138] End 1 Pass. Optimized 10 nets or LUTs. Breaked 9 LUTs, combined 1 existing LUT and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization. INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9426 ; free virtual = 13421 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 9 | 1 | 10 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 9 | 1 | 10 | 0 | 9 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.5.2 Physical Synthesis In Placer | Checksum: 20914b6ca Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9408 ; free virtual = 13402 Phase 2.5 Global Place Phase2 | Checksum: 19af1c1fa Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9417 ; free virtual = 13412 Phase 2 Global Placement | Checksum: 19af1c1fa Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9417 ; free virtual = 13412 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 17ea6b39a Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9435 ; free virtual = 13430 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 31340a59b Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9365 ; free virtual = 13360 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 2ecb823c7 Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9365 ; free virtual = 13360 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 304533148 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9365 ; free virtual = 13360 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 2e207180c Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9158 ; free virtual = 13153 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 1a7d669bd Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9249 ; free virtual = 13244 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 2739d9205 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9233 ; free virtual = 13228 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 28af9807e Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9233 ; free virtual = 13228 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 21c3dded4 Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9085 ; free virtual = 13079 Phase 3 Detail Placement | Checksum: 21c3dded4 Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9085 ; free virtual = 13079 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 157a83430 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.317 | TNS=-2.069 | Phase 1 Physical Synthesis Initialization | Checksum: b9fdedd4 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9044 ; free virtual = 13039 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 12326c09a Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9030 ; free virtual = 13025 Phase 4.1.1.1 BUFG Insertion | Checksum: 157a83430 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 9026 ; free virtual = 13021 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=0.212. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 295bac4c6 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 8207 ; free virtual = 12212 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 8207 ; free virtual = 12212 Phase 4.1 Post Commit Optimization | Checksum: 295bac4c6 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 8207 ; free virtual = 12212 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 295bac4c6 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 8207 ; free virtual = 12212 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 1x1| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 295bac4c6 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 8207 ; free virtual = 12212 Phase 4.3 Placer Reporting | Checksum: 295bac4c6 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 8207 ; free virtual = 12212 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 8207 ; free virtual = 12212 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 8207 ; free virtual = 12212 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2c9458da8 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 8207 ; free virtual = 12212 Ending Placer Task | Checksum: 1f86a80a5 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 8207 ; free virtual = 12212 87 Infos, 14 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 8207 ; free virtual = 12212 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7s50' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7s50' Starting Routing Task Phase 1 Build RT Design Checksum: PlaceDB: ccf80ad1 ConstDB: 0 ShapeSum: 80e1429e RouteDB: aa913336 WARNING: [Route 35-197] Clock port "clk" does not have an associated HD.CLK_SRC. Without this constraint, timing analysis may not be accurate and upstream checks cannot be done to ensure correct clock placement. WARNING: [Route 35-198] Port "X_i[24]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[24]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[16]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[16]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[24]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[24]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[22]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[22]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[20]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[20]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[22]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[22]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[20]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[20]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[27]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[27]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[17]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[17]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[26]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[26]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[16]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[16]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[26]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[26]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[27]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[27]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[25]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[25]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[25]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[25]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[23]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[23]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[21]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[21]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[19]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[19]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[18]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[18]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[19]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[19]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[13]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[13]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[17]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[17]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[12]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[12]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[23]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[23]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[21]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[21]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[18]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[18]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[9]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[9]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[13]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[13]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[9]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[9]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[8]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[8]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[8]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[8]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[14]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[14]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[15]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[15]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[11]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[11]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[15]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[15]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[11]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[11]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[14]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[14]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[12]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[12]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[5]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[5]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[5]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[5]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[6]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[6]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[6]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[6]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[3]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[3]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[7]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[7]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[3]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[3]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "Y_i[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "Y_i[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[7]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[7]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "X_i[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "X_i[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Constraints 18-8777] Unable to split tiles. All required files are not available. Post Restoration Checksum: NetGraph: 5a5d618f | NumContArr: 404dbc36 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 21ffd12ff Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 7480 ; free virtual = 11507 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 21ffd12ff Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 7480 ; free virtual = 11507 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 21ffd12ff Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 7480 ; free virtual = 11507 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 26bf10813 Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2694.820 ; gain = 0.000 ; free physical = 7480 ; free virtual = 11507 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.427 | TNS=0.000 | WHS=0.158 | THS=0.000 | Phase 2.4 Soft Constraint Pins - Fast Budgeting Phase 2.4 Soft Constraint Pins - Fast Budgeting | Checksum: 2435d79d5 Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7473 ; free virtual = 11499 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 397 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 397 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 2 Router Initialization | Checksum: 2435d79d5 Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7473 ; free virtual = 11499 Phase 3 Global Routing Phase 3 Global Routing | Checksum: 2435d79d5 Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7473 ; free virtual = 11499 Phase 4 Initial Routing Phase 4.1 Initial Net Routing Pass Phase 4.1 Initial Net Routing Pass | Checksum: 365b5f1b0 Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7473 ; free virtual = 11499 Phase 4 Initial Routing | Checksum: 365b5f1b0 Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7473 ; free virtual = 11499 Phase 5 Rip-up And Reroute Phase 5.1 Global Iteration 0 Number of Nodes with overlaps = 148 Number of Nodes with overlaps = 64 Number of Nodes with overlaps = 31 Number of Nodes with overlaps = 19 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.096 | TNS=-0.252 | WHS=N/A | THS=N/A | Phase 5.1 Global Iteration 0 | Checksum: 270ed040b Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7457 ; free virtual = 11484 Phase 5.2 Global Iteration 1 Number of Nodes with overlaps = 32 Number of Nodes with overlaps = 23 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.041 | TNS=-0.041 | WHS=N/A | THS=N/A | Phase 5.2 Global Iteration 1 | Checksum: 282de0b15 Time (s): cpu = 00:00:32 ; elapsed = 00:00:32 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7413 ; free virtual = 11439 Phase 5.3 Global Iteration 2 Number of Nodes with overlaps = 25 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.073 | TNS=-0.073 | WHS=N/A | THS=N/A | Phase 5.3 Global Iteration 2 | Checksum: 1e75a1840 Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7396 ; free virtual = 11422 Phase 5 Rip-up And Reroute | Checksum: 1e75a1840 Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7396 ; free virtual = 11422 Phase 6 Delay and Skew Optimization Phase 6.1 Delay CleanUp Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1e75a1840 Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7388 ; free virtual = 11415 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.041 | TNS=-0.041 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 6.1 Delay CleanUp | Checksum: 1c5f73083 Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7388 ; free virtual = 11415 Phase 6.2 Clock Skew Optimization Phase 6.2 Clock Skew Optimization | Checksum: 1c5f73083 Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7388 ; free virtual = 11415 Phase 6 Delay and Skew Optimization | Checksum: 1c5f73083 Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7388 ; free virtual = 11415 Phase 7 Post Hold Fix Phase 7.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.018 | TNS=-0.018 | WHS=0.148 | THS=0.000 | Phase 7.1 Hold Fix Iter | Checksum: 2637c0ec8 Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7388 ; free virtual = 11415 Phase 7 Post Hold Fix | Checksum: 2637c0ec8 Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7388 ; free virtual = 11415 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0876186 % Global Horizontal Routing Utilization = 0.122853 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --GLOBAL Congestion: Utilization threshold used for congestion level computation: 0.85 Congestion Report North Dir 1x1 Area, Max Cong = 18.9189%, No Congested Regions. South Dir 1x1 Area, Max Cong = 40.5405%, No Congested Regions. East Dir 1x1 Area, Max Cong = 39.7059%, No Congested Regions. West Dir 1x1 Area, Max Cong = 25%, No Congested Regions. ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Phase 8 Route finalize | Checksum: 2637c0ec8 Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7388 ; free virtual = 11415 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 2637c0ec8 Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7388 ; free virtual = 11415 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 30cf4c3bb Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7383 ; free virtual = 11409 Phase 11 Post Process Routing Phase 11 Post Process Routing | Checksum: 30cf4c3bb Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7383 ; free virtual = 11409 Phase 12 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.018 | TNS=-0.018 | WHS=0.148 | THS=0.000 | WARNING: [Route 35-328] Router estimated timing not met. Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. Phase 12 Post Router Timing | Checksum: 30cf4c3bb Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7383 ; free virtual = 11409 Total Elapsed time in route_design: 33.24 secs Phase 13 Post-Route Event Processing Phase 13 Post-Route Event Processing | Checksum: 258528386 Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7383 ; free virtual = 11409 INFO: [Route 35-16] Router Completed Successfully Ending Routing Task | Checksum: 258528386 Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7383 ; free virtual = 11409 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 97 Infos, 73 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 2718.883 ; gain = 24.062 ; free physical = 7383 ; free virtual = 11409 INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {REF_NAME =~ DSP*}'. WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {REF_NAME =~ RAMB*}'. INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2718.883 ; gain = 0.000 ; free physical = 7366 ; free virtual = 11393 Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2718.883 ; gain = 0.000 ; free physical = 7366 ; free virtual = 11393 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2718.883 ; gain = 0.000 ; free physical = 7366 ; free virtual = 11393 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2718.883 ; gain = 0.000 ; free physical = 7366 ; free virtual = 11393 Wrote PlaceStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2718.883 ; gain = 0.000 ; free physical = 7366 ; free virtual = 11393 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2718.883 ; gain = 0.000 ; free physical = 7366 ; free virtual = 11393 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2718.883 ; gain = 0.000 ; free physical = 7366 ; free virtual = 11394 Write Physdb Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2718.883 ; gain = 0.000 ; free physical = 7366 ; free virtual = 11394 INFO: [Common 17-1381] The checkpoint '/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/post_route.dcp' has been generated. INFO: [Common 17-206] Exiting Vivado at Sat May 23 23:24:11 2026... $ /mnt/storage/xilinx/2025.2.1/Vivado/bin/vivado -mode batch -nojournal -nolog -notrace -source /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/flopoco_add_we8_wf17_zynq7000_native_single_f200/vivado.tcl [exit code 0]