Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2025.2.1 (lin64) Build 6403652 Thu Mar 19 13:47:00 MDT 2026
| Date         : Sun May 24 14:30:25 2026
| Host         : deep-thought running 64-bit Manjaro Linux
| Command      : report_timing_summary -file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_mul_e8_m17_round_even_p2/timing_summary.rpt -max_paths 10 -nworst 10
| Design       : top_tommath_mul_e8_m17_round_even_p2
| Device       : 7s50-csga324
| Speed File   : -1  PRODUCTION 1.23 2018-06-13
| Design State : Routed
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (54)
6. checking no_output_delay (27)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (54)
-------------------------------
 There are 54 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (27)
--------------------------------
 There are 27 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.360        0.000                      0                  150        0.110        0.000                      0                  150        2.833        0.000                       0                   169  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock  Waveform(ns)         Period(ns)      Frequency(MHz)
-----  ------------         ----------      --------------
clk    {0.000 3.333}        6.667           149.993         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
clk                 0.360        0.000                      0                  150        0.110        0.000                      0                  150        2.833        0.000                       0                   169  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  clk
  To Clock:  clk

Setup :            0  Failing Endpoints,  Worst Slack        0.360ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.110ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.833ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.360ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.254ns  (logic 2.739ns (43.796%)  route 3.515ns (56.204%))
  Logic Levels:           13  (CARRY4=5 LUT3=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.973     0.973    u_dut/clk
    SLICE_X10Y74         FDRE                                         r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y74         FDRE (Prop_fdre_C_Q)         0.518     1.491 r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/Q
                         net (fo=6, routed)           0.465     1.956    u_dut/n2_n1_mant_mul_reg_n_88
    SLICE_X11Y74         LUT3 (Prop_lut3_I0_O)        0.124     2.080 r  u_dut/io_result_payload_mant[3]_INST_0_i_7/O
                         net (fo=5, routed)           0.346     2.426    u_dut/p_0_in[0]
    SLICE_X9Y74          LUT5 (Prop_lut5_I3_O)        0.124     2.550 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/O
                         net (fo=1, routed)           0.403     2.953    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     3.077 r  u_dut/io_result_payload_mant[3]_INST_0_i_12/O
                         net (fo=1, routed)           0.313     3.390    u_dut/io_result_payload_mant[3]_INST_0_i_12_n_0
    SLICE_X10Y74         LUT6 (Prop_lut6_I4_O)        0.124     3.514 r  u_dut/io_result_payload_mant[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[3]_INST_0_i_6_n_0
    SLICE_X10Y74         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     4.027 r  u_dut/io_result_payload_mant[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     4.036    u_dut/io_result_payload_mant[3]_INST_0_i_1_n_0
    SLICE_X10Y75         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.153 r  u_dut/io_result_payload_mant[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.153    u_dut/io_result_payload_mant[7]_INST_0_i_1_n_0
    SLICE_X10Y76         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.270 r  u_dut/io_result_payload_mant[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.270    u_dut/io_result_payload_mant[11]_INST_0_i_1_n_0
    SLICE_X10Y77         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.387 r  u_dut/io_result_payload_mant[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.387    u_dut/io_result_payload_mant[15]_INST_0_i_1_n_0
    SLICE_X10Y78         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157     4.544 r  u_dut/io_result_payload_mant[16]_INST_0_i_1/CO[1]
                         net (fo=2, routed)           0.316     4.861    u_dut/_zz_n2_mant_mul_rounded_1[17]
    SLICE_X10Y79         LUT6 (Prop_lut6_I1_O)        0.332     5.193 r  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=9, routed)           0.623     5.815    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X10Y80         LUT6 (Prop_lut6_I1_O)        0.124     5.939 r  u_dut/io_result_payload_mant[16]_INST_0_i_10/O
                         net (fo=1, routed)           0.411     6.350    u_dut/io_result_payload_mant[16]_INST_0_i_10_n_0
    SLICE_X9Y81          LUT6 (Prop_lut6_I0_O)        0.124     6.474 r  u_dut/io_result_payload_mant[16]_INST_0_i_5/O
                         net (fo=17, routed)          0.629     7.103    u_dut/io_result_payload_mant[16]_INST_0_i_5_n_0
    SLICE_X11Y81         LUT6 (Prop_lut6_I5_O)        0.124     7.227 r  u_dut/io_result_payload_mant[15]_INST_0/O
                         net (fo=1, routed)           0.000     7.227    dut_y[15]
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=169, unset)          0.924     7.591    clk
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X11Y81         FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[15]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -7.227    
  -------------------------------------------------------------------
                         slack                                  0.360    

Slack (MET) :             0.360ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.254ns  (logic 2.739ns (43.796%)  route 3.515ns (56.204%))
  Logic Levels:           13  (CARRY4=5 LUT3=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.973     0.973    u_dut/clk
    SLICE_X10Y74         FDRE                                         r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y74         FDRE (Prop_fdre_C_Q)         0.518     1.491 r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/Q
                         net (fo=6, routed)           0.465     1.956    u_dut/n2_n1_mant_mul_reg_n_88
    SLICE_X11Y74         LUT3 (Prop_lut3_I0_O)        0.124     2.080 r  u_dut/io_result_payload_mant[3]_INST_0_i_7/O
                         net (fo=5, routed)           0.346     2.426    u_dut/p_0_in[0]
    SLICE_X9Y74          LUT5 (Prop_lut5_I3_O)        0.124     2.550 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/O
                         net (fo=1, routed)           0.403     2.953    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     3.077 r  u_dut/io_result_payload_mant[3]_INST_0_i_12/O
                         net (fo=1, routed)           0.313     3.390    u_dut/io_result_payload_mant[3]_INST_0_i_12_n_0
    SLICE_X10Y74         LUT6 (Prop_lut6_I4_O)        0.124     3.514 r  u_dut/io_result_payload_mant[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[3]_INST_0_i_6_n_0
    SLICE_X10Y74         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     4.027 r  u_dut/io_result_payload_mant[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     4.036    u_dut/io_result_payload_mant[3]_INST_0_i_1_n_0
    SLICE_X10Y75         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.153 f  u_dut/io_result_payload_mant[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.153    u_dut/io_result_payload_mant[7]_INST_0_i_1_n_0
    SLICE_X10Y76         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.270 r  u_dut/io_result_payload_mant[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.270    u_dut/io_result_payload_mant[11]_INST_0_i_1_n_0
    SLICE_X10Y77         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.387 r  u_dut/io_result_payload_mant[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.387    u_dut/io_result_payload_mant[15]_INST_0_i_1_n_0
    SLICE_X10Y78         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157     4.544 r  u_dut/io_result_payload_mant[16]_INST_0_i_1/CO[1]
                         net (fo=2, routed)           0.316     4.861    u_dut/_zz_n2_mant_mul_rounded_1[17]
    SLICE_X10Y79         LUT6 (Prop_lut6_I1_O)        0.332     5.193 r  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=9, routed)           0.623     5.815    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X10Y80         LUT6 (Prop_lut6_I1_O)        0.124     5.939 r  u_dut/io_result_payload_mant[16]_INST_0_i_10/O
                         net (fo=1, routed)           0.411     6.350    u_dut/io_result_payload_mant[16]_INST_0_i_10_n_0
    SLICE_X9Y81          LUT6 (Prop_lut6_I0_O)        0.124     6.474 r  u_dut/io_result_payload_mant[16]_INST_0_i_5/O
                         net (fo=17, routed)          0.629     7.103    u_dut/io_result_payload_mant[16]_INST_0_i_5_n_0
    SLICE_X11Y81         LUT6 (Prop_lut6_I5_O)        0.124     7.227 r  u_dut/io_result_payload_mant[15]_INST_0/O
                         net (fo=1, routed)           0.000     7.227    dut_y[15]
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=169, unset)          0.924     7.591    clk
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X11Y81         FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[15]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -7.227    
  -------------------------------------------------------------------
                         slack                                  0.360    

Slack (MET) :             0.360ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.254ns  (logic 2.739ns (43.796%)  route 3.515ns (56.204%))
  Logic Levels:           13  (CARRY4=5 LUT3=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.973     0.973    u_dut/clk
    SLICE_X10Y74         FDRE                                         r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y74         FDRE (Prop_fdre_C_Q)         0.518     1.491 r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/Q
                         net (fo=6, routed)           0.465     1.956    u_dut/n2_n1_mant_mul_reg_n_88
    SLICE_X11Y74         LUT3 (Prop_lut3_I0_O)        0.124     2.080 r  u_dut/io_result_payload_mant[3]_INST_0_i_7/O
                         net (fo=5, routed)           0.346     2.426    u_dut/p_0_in[0]
    SLICE_X9Y74          LUT5 (Prop_lut5_I3_O)        0.124     2.550 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/O
                         net (fo=1, routed)           0.403     2.953    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     3.077 r  u_dut/io_result_payload_mant[3]_INST_0_i_12/O
                         net (fo=1, routed)           0.313     3.390    u_dut/io_result_payload_mant[3]_INST_0_i_12_n_0
    SLICE_X10Y74         LUT6 (Prop_lut6_I4_O)        0.124     3.514 r  u_dut/io_result_payload_mant[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[3]_INST_0_i_6_n_0
    SLICE_X10Y74         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     4.027 r  u_dut/io_result_payload_mant[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     4.036    u_dut/io_result_payload_mant[3]_INST_0_i_1_n_0
    SLICE_X10Y75         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.153 r  u_dut/io_result_payload_mant[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.153    u_dut/io_result_payload_mant[7]_INST_0_i_1_n_0
    SLICE_X10Y76         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.270 f  u_dut/io_result_payload_mant[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.270    u_dut/io_result_payload_mant[11]_INST_0_i_1_n_0
    SLICE_X10Y77         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.387 r  u_dut/io_result_payload_mant[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.387    u_dut/io_result_payload_mant[15]_INST_0_i_1_n_0
    SLICE_X10Y78         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157     4.544 r  u_dut/io_result_payload_mant[16]_INST_0_i_1/CO[1]
                         net (fo=2, routed)           0.316     4.861    u_dut/_zz_n2_mant_mul_rounded_1[17]
    SLICE_X10Y79         LUT6 (Prop_lut6_I1_O)        0.332     5.193 r  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=9, routed)           0.623     5.815    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X10Y80         LUT6 (Prop_lut6_I1_O)        0.124     5.939 r  u_dut/io_result_payload_mant[16]_INST_0_i_10/O
                         net (fo=1, routed)           0.411     6.350    u_dut/io_result_payload_mant[16]_INST_0_i_10_n_0
    SLICE_X9Y81          LUT6 (Prop_lut6_I0_O)        0.124     6.474 r  u_dut/io_result_payload_mant[16]_INST_0_i_5/O
                         net (fo=17, routed)          0.629     7.103    u_dut/io_result_payload_mant[16]_INST_0_i_5_n_0
    SLICE_X11Y81         LUT6 (Prop_lut6_I5_O)        0.124     7.227 r  u_dut/io_result_payload_mant[15]_INST_0/O
                         net (fo=1, routed)           0.000     7.227    dut_y[15]
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=169, unset)          0.924     7.591    clk
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X11Y81         FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[15]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -7.227    
  -------------------------------------------------------------------
                         slack                                  0.360    

Slack (MET) :             0.360ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.254ns  (logic 2.739ns (43.796%)  route 3.515ns (56.204%))
  Logic Levels:           13  (CARRY4=5 LUT3=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.973     0.973    u_dut/clk
    SLICE_X10Y74         FDRE                                         r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y74         FDRE (Prop_fdre_C_Q)         0.518     1.491 r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/Q
                         net (fo=6, routed)           0.465     1.956    u_dut/n2_n1_mant_mul_reg_n_88
    SLICE_X11Y74         LUT3 (Prop_lut3_I0_O)        0.124     2.080 r  u_dut/io_result_payload_mant[3]_INST_0_i_7/O
                         net (fo=5, routed)           0.346     2.426    u_dut/p_0_in[0]
    SLICE_X9Y74          LUT5 (Prop_lut5_I3_O)        0.124     2.550 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/O
                         net (fo=1, routed)           0.403     2.953    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     3.077 r  u_dut/io_result_payload_mant[3]_INST_0_i_12/O
                         net (fo=1, routed)           0.313     3.390    u_dut/io_result_payload_mant[3]_INST_0_i_12_n_0
    SLICE_X10Y74         LUT6 (Prop_lut6_I4_O)        0.124     3.514 r  u_dut/io_result_payload_mant[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[3]_INST_0_i_6_n_0
    SLICE_X10Y74         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     4.027 r  u_dut/io_result_payload_mant[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     4.036    u_dut/io_result_payload_mant[3]_INST_0_i_1_n_0
    SLICE_X10Y75         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.153 f  u_dut/io_result_payload_mant[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.153    u_dut/io_result_payload_mant[7]_INST_0_i_1_n_0
    SLICE_X10Y76         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.270 f  u_dut/io_result_payload_mant[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.270    u_dut/io_result_payload_mant[11]_INST_0_i_1_n_0
    SLICE_X10Y77         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.387 r  u_dut/io_result_payload_mant[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.387    u_dut/io_result_payload_mant[15]_INST_0_i_1_n_0
    SLICE_X10Y78         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157     4.544 r  u_dut/io_result_payload_mant[16]_INST_0_i_1/CO[1]
                         net (fo=2, routed)           0.316     4.861    u_dut/_zz_n2_mant_mul_rounded_1[17]
    SLICE_X10Y79         LUT6 (Prop_lut6_I1_O)        0.332     5.193 r  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=9, routed)           0.623     5.815    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X10Y80         LUT6 (Prop_lut6_I1_O)        0.124     5.939 r  u_dut/io_result_payload_mant[16]_INST_0_i_10/O
                         net (fo=1, routed)           0.411     6.350    u_dut/io_result_payload_mant[16]_INST_0_i_10_n_0
    SLICE_X9Y81          LUT6 (Prop_lut6_I0_O)        0.124     6.474 r  u_dut/io_result_payload_mant[16]_INST_0_i_5/O
                         net (fo=17, routed)          0.629     7.103    u_dut/io_result_payload_mant[16]_INST_0_i_5_n_0
    SLICE_X11Y81         LUT6 (Prop_lut6_I5_O)        0.124     7.227 r  u_dut/io_result_payload_mant[15]_INST_0/O
                         net (fo=1, routed)           0.000     7.227    dut_y[15]
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=169, unset)          0.924     7.591    clk
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X11Y81         FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[15]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -7.227    
  -------------------------------------------------------------------
                         slack                                  0.360    

Slack (MET) :             0.360ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.254ns  (logic 2.739ns (43.796%)  route 3.515ns (56.204%))
  Logic Levels:           13  (CARRY4=5 LUT3=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.973     0.973    u_dut/clk
    SLICE_X10Y74         FDRE                                         r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y74         FDRE (Prop_fdre_C_Q)         0.518     1.491 r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/Q
                         net (fo=6, routed)           0.465     1.956    u_dut/n2_n1_mant_mul_reg_n_88
    SLICE_X11Y74         LUT3 (Prop_lut3_I0_O)        0.124     2.080 r  u_dut/io_result_payload_mant[3]_INST_0_i_7/O
                         net (fo=5, routed)           0.346     2.426    u_dut/p_0_in[0]
    SLICE_X9Y74          LUT5 (Prop_lut5_I3_O)        0.124     2.550 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/O
                         net (fo=1, routed)           0.403     2.953    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     3.077 r  u_dut/io_result_payload_mant[3]_INST_0_i_12/O
                         net (fo=1, routed)           0.313     3.390    u_dut/io_result_payload_mant[3]_INST_0_i_12_n_0
    SLICE_X10Y74         LUT6 (Prop_lut6_I4_O)        0.124     3.514 r  u_dut/io_result_payload_mant[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[3]_INST_0_i_6_n_0
    SLICE_X10Y74         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     4.027 r  u_dut/io_result_payload_mant[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     4.036    u_dut/io_result_payload_mant[3]_INST_0_i_1_n_0
    SLICE_X10Y75         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.153 r  u_dut/io_result_payload_mant[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.153    u_dut/io_result_payload_mant[7]_INST_0_i_1_n_0
    SLICE_X10Y76         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.270 r  u_dut/io_result_payload_mant[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.270    u_dut/io_result_payload_mant[11]_INST_0_i_1_n_0
    SLICE_X10Y77         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.387 f  u_dut/io_result_payload_mant[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.387    u_dut/io_result_payload_mant[15]_INST_0_i_1_n_0
    SLICE_X10Y78         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157     4.544 r  u_dut/io_result_payload_mant[16]_INST_0_i_1/CO[1]
                         net (fo=2, routed)           0.316     4.861    u_dut/_zz_n2_mant_mul_rounded_1[17]
    SLICE_X10Y79         LUT6 (Prop_lut6_I1_O)        0.332     5.193 r  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=9, routed)           0.623     5.815    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X10Y80         LUT6 (Prop_lut6_I1_O)        0.124     5.939 r  u_dut/io_result_payload_mant[16]_INST_0_i_10/O
                         net (fo=1, routed)           0.411     6.350    u_dut/io_result_payload_mant[16]_INST_0_i_10_n_0
    SLICE_X9Y81          LUT6 (Prop_lut6_I0_O)        0.124     6.474 r  u_dut/io_result_payload_mant[16]_INST_0_i_5/O
                         net (fo=17, routed)          0.629     7.103    u_dut/io_result_payload_mant[16]_INST_0_i_5_n_0
    SLICE_X11Y81         LUT6 (Prop_lut6_I5_O)        0.124     7.227 r  u_dut/io_result_payload_mant[15]_INST_0/O
                         net (fo=1, routed)           0.000     7.227    dut_y[15]
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=169, unset)          0.924     7.591    clk
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X11Y81         FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[15]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -7.227    
  -------------------------------------------------------------------
                         slack                                  0.360    

Slack (MET) :             0.360ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.254ns  (logic 2.739ns (43.796%)  route 3.515ns (56.204%))
  Logic Levels:           13  (CARRY4=5 LUT3=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.973     0.973    u_dut/clk
    SLICE_X10Y74         FDRE                                         r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y74         FDRE (Prop_fdre_C_Q)         0.518     1.491 r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/Q
                         net (fo=6, routed)           0.465     1.956    u_dut/n2_n1_mant_mul_reg_n_88
    SLICE_X11Y74         LUT3 (Prop_lut3_I0_O)        0.124     2.080 r  u_dut/io_result_payload_mant[3]_INST_0_i_7/O
                         net (fo=5, routed)           0.346     2.426    u_dut/p_0_in[0]
    SLICE_X9Y74          LUT5 (Prop_lut5_I3_O)        0.124     2.550 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/O
                         net (fo=1, routed)           0.403     2.953    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     3.077 r  u_dut/io_result_payload_mant[3]_INST_0_i_12/O
                         net (fo=1, routed)           0.313     3.390    u_dut/io_result_payload_mant[3]_INST_0_i_12_n_0
    SLICE_X10Y74         LUT6 (Prop_lut6_I4_O)        0.124     3.514 r  u_dut/io_result_payload_mant[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[3]_INST_0_i_6_n_0
    SLICE_X10Y74         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     4.027 r  u_dut/io_result_payload_mant[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     4.036    u_dut/io_result_payload_mant[3]_INST_0_i_1_n_0
    SLICE_X10Y75         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.153 f  u_dut/io_result_payload_mant[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.153    u_dut/io_result_payload_mant[7]_INST_0_i_1_n_0
    SLICE_X10Y76         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.270 r  u_dut/io_result_payload_mant[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.270    u_dut/io_result_payload_mant[11]_INST_0_i_1_n_0
    SLICE_X10Y77         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.387 f  u_dut/io_result_payload_mant[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.387    u_dut/io_result_payload_mant[15]_INST_0_i_1_n_0
    SLICE_X10Y78         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157     4.544 r  u_dut/io_result_payload_mant[16]_INST_0_i_1/CO[1]
                         net (fo=2, routed)           0.316     4.861    u_dut/_zz_n2_mant_mul_rounded_1[17]
    SLICE_X10Y79         LUT6 (Prop_lut6_I1_O)        0.332     5.193 r  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=9, routed)           0.623     5.815    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X10Y80         LUT6 (Prop_lut6_I1_O)        0.124     5.939 r  u_dut/io_result_payload_mant[16]_INST_0_i_10/O
                         net (fo=1, routed)           0.411     6.350    u_dut/io_result_payload_mant[16]_INST_0_i_10_n_0
    SLICE_X9Y81          LUT6 (Prop_lut6_I0_O)        0.124     6.474 r  u_dut/io_result_payload_mant[16]_INST_0_i_5/O
                         net (fo=17, routed)          0.629     7.103    u_dut/io_result_payload_mant[16]_INST_0_i_5_n_0
    SLICE_X11Y81         LUT6 (Prop_lut6_I5_O)        0.124     7.227 r  u_dut/io_result_payload_mant[15]_INST_0/O
                         net (fo=1, routed)           0.000     7.227    dut_y[15]
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=169, unset)          0.924     7.591    clk
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X11Y81         FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[15]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -7.227    
  -------------------------------------------------------------------
                         slack                                  0.360    

Slack (MET) :             0.360ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.254ns  (logic 2.739ns (43.796%)  route 3.515ns (56.204%))
  Logic Levels:           13  (CARRY4=5 LUT3=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.973     0.973    u_dut/clk
    SLICE_X10Y74         FDRE                                         r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y74         FDRE (Prop_fdre_C_Q)         0.518     1.491 r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/Q
                         net (fo=6, routed)           0.465     1.956    u_dut/n2_n1_mant_mul_reg_n_88
    SLICE_X11Y74         LUT3 (Prop_lut3_I0_O)        0.124     2.080 r  u_dut/io_result_payload_mant[3]_INST_0_i_7/O
                         net (fo=5, routed)           0.346     2.426    u_dut/p_0_in[0]
    SLICE_X9Y74          LUT5 (Prop_lut5_I3_O)        0.124     2.550 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/O
                         net (fo=1, routed)           0.403     2.953    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     3.077 r  u_dut/io_result_payload_mant[3]_INST_0_i_12/O
                         net (fo=1, routed)           0.313     3.390    u_dut/io_result_payload_mant[3]_INST_0_i_12_n_0
    SLICE_X10Y74         LUT6 (Prop_lut6_I4_O)        0.124     3.514 r  u_dut/io_result_payload_mant[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[3]_INST_0_i_6_n_0
    SLICE_X10Y74         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     4.027 r  u_dut/io_result_payload_mant[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     4.036    u_dut/io_result_payload_mant[3]_INST_0_i_1_n_0
    SLICE_X10Y75         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.153 r  u_dut/io_result_payload_mant[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.153    u_dut/io_result_payload_mant[7]_INST_0_i_1_n_0
    SLICE_X10Y76         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.270 f  u_dut/io_result_payload_mant[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.270    u_dut/io_result_payload_mant[11]_INST_0_i_1_n_0
    SLICE_X10Y77         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.387 f  u_dut/io_result_payload_mant[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.387    u_dut/io_result_payload_mant[15]_INST_0_i_1_n_0
    SLICE_X10Y78         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157     4.544 r  u_dut/io_result_payload_mant[16]_INST_0_i_1/CO[1]
                         net (fo=2, routed)           0.316     4.861    u_dut/_zz_n2_mant_mul_rounded_1[17]
    SLICE_X10Y79         LUT6 (Prop_lut6_I1_O)        0.332     5.193 r  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=9, routed)           0.623     5.815    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X10Y80         LUT6 (Prop_lut6_I1_O)        0.124     5.939 r  u_dut/io_result_payload_mant[16]_INST_0_i_10/O
                         net (fo=1, routed)           0.411     6.350    u_dut/io_result_payload_mant[16]_INST_0_i_10_n_0
    SLICE_X9Y81          LUT6 (Prop_lut6_I0_O)        0.124     6.474 r  u_dut/io_result_payload_mant[16]_INST_0_i_5/O
                         net (fo=17, routed)          0.629     7.103    u_dut/io_result_payload_mant[16]_INST_0_i_5_n_0
    SLICE_X11Y81         LUT6 (Prop_lut6_I5_O)        0.124     7.227 r  u_dut/io_result_payload_mant[15]_INST_0/O
                         net (fo=1, routed)           0.000     7.227    dut_y[15]
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=169, unset)          0.924     7.591    clk
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X11Y81         FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[15]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -7.227    
  -------------------------------------------------------------------
                         slack                                  0.360    

Slack (MET) :             0.360ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.254ns  (logic 2.739ns (43.796%)  route 3.515ns (56.204%))
  Logic Levels:           13  (CARRY4=5 LUT3=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.973     0.973    u_dut/clk
    SLICE_X10Y74         FDRE                                         r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y74         FDRE (Prop_fdre_C_Q)         0.518     1.491 r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/Q
                         net (fo=6, routed)           0.465     1.956    u_dut/n2_n1_mant_mul_reg_n_88
    SLICE_X11Y74         LUT3 (Prop_lut3_I0_O)        0.124     2.080 r  u_dut/io_result_payload_mant[3]_INST_0_i_7/O
                         net (fo=5, routed)           0.346     2.426    u_dut/p_0_in[0]
    SLICE_X9Y74          LUT5 (Prop_lut5_I3_O)        0.124     2.550 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/O
                         net (fo=1, routed)           0.403     2.953    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     3.077 r  u_dut/io_result_payload_mant[3]_INST_0_i_12/O
                         net (fo=1, routed)           0.313     3.390    u_dut/io_result_payload_mant[3]_INST_0_i_12_n_0
    SLICE_X10Y74         LUT6 (Prop_lut6_I4_O)        0.124     3.514 r  u_dut/io_result_payload_mant[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[3]_INST_0_i_6_n_0
    SLICE_X10Y74         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     4.027 r  u_dut/io_result_payload_mant[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     4.036    u_dut/io_result_payload_mant[3]_INST_0_i_1_n_0
    SLICE_X10Y75         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.153 f  u_dut/io_result_payload_mant[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.153    u_dut/io_result_payload_mant[7]_INST_0_i_1_n_0
    SLICE_X10Y76         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.270 f  u_dut/io_result_payload_mant[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.270    u_dut/io_result_payload_mant[11]_INST_0_i_1_n_0
    SLICE_X10Y77         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.387 f  u_dut/io_result_payload_mant[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.387    u_dut/io_result_payload_mant[15]_INST_0_i_1_n_0
    SLICE_X10Y78         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157     4.544 r  u_dut/io_result_payload_mant[16]_INST_0_i_1/CO[1]
                         net (fo=2, routed)           0.316     4.861    u_dut/_zz_n2_mant_mul_rounded_1[17]
    SLICE_X10Y79         LUT6 (Prop_lut6_I1_O)        0.332     5.193 r  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=9, routed)           0.623     5.815    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X10Y80         LUT6 (Prop_lut6_I1_O)        0.124     5.939 r  u_dut/io_result_payload_mant[16]_INST_0_i_10/O
                         net (fo=1, routed)           0.411     6.350    u_dut/io_result_payload_mant[16]_INST_0_i_10_n_0
    SLICE_X9Y81          LUT6 (Prop_lut6_I0_O)        0.124     6.474 r  u_dut/io_result_payload_mant[16]_INST_0_i_5/O
                         net (fo=17, routed)          0.629     7.103    u_dut/io_result_payload_mant[16]_INST_0_i_5_n_0
    SLICE_X11Y81         LUT6 (Prop_lut6_I5_O)        0.124     7.227 r  u_dut/io_result_payload_mant[15]_INST_0/O
                         net (fo=1, routed)           0.000     7.227    dut_y[15]
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=169, unset)          0.924     7.591    clk
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X11Y81         FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[15]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -7.227    
  -------------------------------------------------------------------
                         slack                                  0.360    

Slack (MET) :             0.360ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.254ns  (logic 2.739ns (43.796%)  route 3.515ns (56.204%))
  Logic Levels:           13  (CARRY4=5 LUT3=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.973     0.973    u_dut/clk
    SLICE_X10Y74         FDRE                                         r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y74         FDRE (Prop_fdre_C_Q)         0.518     1.491 r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/Q
                         net (fo=6, routed)           0.465     1.956    u_dut/n2_n1_mant_mul_reg_n_88
    SLICE_X11Y74         LUT3 (Prop_lut3_I0_O)        0.124     2.080 r  u_dut/io_result_payload_mant[3]_INST_0_i_7/O
                         net (fo=5, routed)           0.346     2.426    u_dut/p_0_in[0]
    SLICE_X9Y74          LUT5 (Prop_lut5_I3_O)        0.124     2.550 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/O
                         net (fo=1, routed)           0.403     2.953    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     3.077 r  u_dut/io_result_payload_mant[3]_INST_0_i_12/O
                         net (fo=1, routed)           0.313     3.390    u_dut/io_result_payload_mant[3]_INST_0_i_12_n_0
    SLICE_X10Y74         LUT6 (Prop_lut6_I4_O)        0.124     3.514 r  u_dut/io_result_payload_mant[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[3]_INST_0_i_6_n_0
    SLICE_X10Y74         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     4.027 r  u_dut/io_result_payload_mant[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     4.036    u_dut/io_result_payload_mant[3]_INST_0_i_1_n_0
    SLICE_X10Y75         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.153 r  u_dut/io_result_payload_mant[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.153    u_dut/io_result_payload_mant[7]_INST_0_i_1_n_0
    SLICE_X10Y76         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.270 r  u_dut/io_result_payload_mant[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.270    u_dut/io_result_payload_mant[11]_INST_0_i_1_n_0
    SLICE_X10Y77         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.387 r  u_dut/io_result_payload_mant[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.387    u_dut/io_result_payload_mant[15]_INST_0_i_1_n_0
    SLICE_X10Y78         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157     4.544 f  u_dut/io_result_payload_mant[16]_INST_0_i_1/CO[1]
                         net (fo=2, routed)           0.316     4.861    u_dut/_zz_n2_mant_mul_rounded_1[17]
    SLICE_X10Y79         LUT6 (Prop_lut6_I1_O)        0.332     5.193 f  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=9, routed)           0.623     5.815    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X10Y80         LUT6 (Prop_lut6_I1_O)        0.124     5.939 r  u_dut/io_result_payload_mant[16]_INST_0_i_10/O
                         net (fo=1, routed)           0.411     6.350    u_dut/io_result_payload_mant[16]_INST_0_i_10_n_0
    SLICE_X9Y81          LUT6 (Prop_lut6_I0_O)        0.124     6.474 r  u_dut/io_result_payload_mant[16]_INST_0_i_5/O
                         net (fo=17, routed)          0.629     7.103    u_dut/io_result_payload_mant[16]_INST_0_i_5_n_0
    SLICE_X11Y81         LUT6 (Prop_lut6_I5_O)        0.124     7.227 r  u_dut/io_result_payload_mant[15]_INST_0/O
                         net (fo=1, routed)           0.000     7.227    dut_y[15]
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=169, unset)          0.924     7.591    clk
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X11Y81         FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[15]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -7.227    
  -------------------------------------------------------------------
                         slack                                  0.360    

Slack (MET) :             0.360ns  (required time - arrival time)
  Source:                 u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.254ns  (logic 2.739ns (43.796%)  route 3.515ns (56.204%))
  Logic Levels:           13  (CARRY4=5 LUT3=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.973     0.973    u_dut/clk
    SLICE_X10Y74         FDRE                                         r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y74         FDRE (Prop_fdre_C_Q)         0.518     1.491 r  u_dut/io_result_payload_exp[0]_INST_0_i_1_psdsp_2/Q
                         net (fo=6, routed)           0.465     1.956    u_dut/n2_n1_mant_mul_reg_n_88
    SLICE_X11Y74         LUT3 (Prop_lut3_I0_O)        0.124     2.080 r  u_dut/io_result_payload_mant[3]_INST_0_i_7/O
                         net (fo=5, routed)           0.346     2.426    u_dut/p_0_in[0]
    SLICE_X9Y74          LUT5 (Prop_lut5_I3_O)        0.124     2.550 r  u_dut/io_result_payload_mant[3]_INST_0_i_14/O
                         net (fo=1, routed)           0.403     2.953    u_dut/io_result_payload_mant[3]_INST_0_i_14_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     3.077 r  u_dut/io_result_payload_mant[3]_INST_0_i_12/O
                         net (fo=1, routed)           0.313     3.390    u_dut/io_result_payload_mant[3]_INST_0_i_12_n_0
    SLICE_X10Y74         LUT6 (Prop_lut6_I4_O)        0.124     3.514 r  u_dut/io_result_payload_mant[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     3.514    u_dut/io_result_payload_mant[3]_INST_0_i_6_n_0
    SLICE_X10Y74         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.513     4.027 r  u_dut/io_result_payload_mant[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     4.036    u_dut/io_result_payload_mant[3]_INST_0_i_1_n_0
    SLICE_X10Y75         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.153 f  u_dut/io_result_payload_mant[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.153    u_dut/io_result_payload_mant[7]_INST_0_i_1_n_0
    SLICE_X10Y76         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.270 r  u_dut/io_result_payload_mant[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.270    u_dut/io_result_payload_mant[11]_INST_0_i_1_n_0
    SLICE_X10Y77         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.387 r  u_dut/io_result_payload_mant[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.387    u_dut/io_result_payload_mant[15]_INST_0_i_1_n_0
    SLICE_X10Y78         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157     4.544 f  u_dut/io_result_payload_mant[16]_INST_0_i_1/CO[1]
                         net (fo=2, routed)           0.316     4.861    u_dut/_zz_n2_mant_mul_rounded_1[17]
    SLICE_X10Y79         LUT6 (Prop_lut6_I1_O)        0.332     5.193 f  u_dut/io_result_payload_exp[1]_INST_0_i_1/O
                         net (fo=9, routed)           0.623     5.815    u_dut/io_result_payload_exp[1]_INST_0_i_1_n_0
    SLICE_X10Y80         LUT6 (Prop_lut6_I1_O)        0.124     5.939 r  u_dut/io_result_payload_mant[16]_INST_0_i_10/O
                         net (fo=1, routed)           0.411     6.350    u_dut/io_result_payload_mant[16]_INST_0_i_10_n_0
    SLICE_X9Y81          LUT6 (Prop_lut6_I0_O)        0.124     6.474 r  u_dut/io_result_payload_mant[16]_INST_0_i_5/O
                         net (fo=17, routed)          0.629     7.103    u_dut/io_result_payload_mant[16]_INST_0_i_5_n_0
    SLICE_X11Y81         LUT6 (Prop_lut6_I5_O)        0.124     7.227 r  u_dut/io_result_payload_mant[15]_INST_0/O
                         net (fo=1, routed)           0.000     7.227    dut_y[15]
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=169, unset)          0.924     7.591    clk
    SLICE_X11Y81         FDRE                                         r  y_r_reg[15]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X11Y81         FDRE (Setup_fdre_C_D)        0.031     7.587    y_r_reg[15]
  -------------------------------------------------------------------
                         required time                          7.587    
                         arrival time                          -7.227    
  -------------------------------------------------------------------
                         slack                                  0.360    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.110ns  (arrival time - required time)
  Source:                 a_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_mant_a_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.209ns  (logic 0.141ns (67.433%)  route 0.068ns (32.567%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.410     0.410    clk
    SLICE_X13Y72         FDRE                                         r  a_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y72         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  a_r_reg[2]/Q
                         net (fo=3, routed)           0.068     0.619    u_dut/io_input_payload_a_mant[2]
    SLICE_X13Y72         FDRE                                         r  u_dut/n1_n0_mant_a_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.432     0.432    u_dut/clk
    SLICE_X13Y72         FDRE                                         r  u_dut/n1_n0_mant_a_reg[2]/C
                         clock pessimism              0.000     0.432    
    SLICE_X13Y72         FDRE (Hold_fdre_C_D)         0.078     0.510    u_dut/n1_n0_mant_a_reg[2]
  -------------------------------------------------------------------
                         required time                         -0.510    
                         arrival time                           0.619    
  -------------------------------------------------------------------
                         slack                                  0.110    

Slack (MET) :             0.110ns  (arrival time - required time)
  Source:                 a_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_mant_a_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.209ns  (logic 0.141ns (67.433%)  route 0.068ns (32.567%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.410     0.410    clk
    SLICE_X13Y72         FDRE                                         r  a_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y72         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  a_r_reg[2]/Q
                         net (fo=3, routed)           0.068     0.619    u_dut/io_input_payload_a_mant[2]
    SLICE_X13Y72         FDRE                                         f  u_dut/n1_n0_mant_a_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.432     0.432    u_dut/clk
    SLICE_X13Y72         FDRE                                         r  u_dut/n1_n0_mant_a_reg[2]/C
                         clock pessimism              0.000     0.432    
    SLICE_X13Y72         FDRE (Hold_fdre_C_D)         0.078     0.510    u_dut/n1_n0_mant_a_reg[2]
  -------------------------------------------------------------------
                         required time                         -0.510    
                         arrival time                           0.619    
  -------------------------------------------------------------------
                         slack                                  0.110    

Slack (MET) :             0.123ns  (arrival time - required time)
  Source:                 a_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_mant_a_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.220ns  (logic 0.141ns (64.033%)  route 0.079ns (35.967%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.410     0.410    clk
    SLICE_X13Y72         FDRE                                         r  a_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y72         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  a_r_reg[1]/Q
                         net (fo=3, routed)           0.079     0.630    u_dut/io_input_payload_a_mant[1]
    SLICE_X13Y72         FDRE                                         r  u_dut/n1_n0_mant_a_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.432     0.432    u_dut/clk
    SLICE_X13Y72         FDRE                                         r  u_dut/n1_n0_mant_a_reg[1]/C
                         clock pessimism              0.000     0.432    
    SLICE_X13Y72         FDRE (Hold_fdre_C_D)         0.076     0.508    u_dut/n1_n0_mant_a_reg[1]
  -------------------------------------------------------------------
                         required time                         -0.508    
                         arrival time                           0.630    
  -------------------------------------------------------------------
                         slack                                  0.123    

Slack (MET) :             0.123ns  (arrival time - required time)
  Source:                 a_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_mant_a_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.220ns  (logic 0.141ns (64.033%)  route 0.079ns (35.967%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.410     0.410    clk
    SLICE_X13Y72         FDRE                                         r  a_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y72         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  a_r_reg[1]/Q
                         net (fo=3, routed)           0.079     0.630    u_dut/io_input_payload_a_mant[1]
    SLICE_X13Y72         FDRE                                         f  u_dut/n1_n0_mant_a_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.432     0.432    u_dut/clk
    SLICE_X13Y72         FDRE                                         r  u_dut/n1_n0_mant_a_reg[1]/C
                         clock pessimism              0.000     0.432    
    SLICE_X13Y72         FDRE (Hold_fdre_C_D)         0.076     0.508    u_dut/n1_n0_mant_a_reg[1]
  -------------------------------------------------------------------
                         required time                         -0.508    
                         arrival time                           0.630    
  -------------------------------------------------------------------
                         slack                                  0.123    

Slack (MET) :             0.132ns  (arrival time - required time)
  Source:                 a_r_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_sign_mul_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.273ns  (logic 0.186ns (68.106%)  route 0.087ns (31.894%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.410     0.410    clk
    SLICE_X35Y75         FDRE                                         r  a_r_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y75         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  a_r_reg[25]/Q
                         net (fo=1, routed)           0.087     0.638    u_dut/io_input_payload_a_sign
    SLICE_X34Y75         LUT2 (Prop_lut2_I1_O)        0.045     0.683 r  u_dut/n1_n0_sign_mul_i_1/O
                         net (fo=1, routed)           0.000     0.683    u_dut/n0_sign_mul
    SLICE_X34Y75         FDRE                                         r  u_dut/n1_n0_sign_mul_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.432     0.432    u_dut/clk
    SLICE_X34Y75         FDRE                                         r  u_dut/n1_n0_sign_mul_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X34Y75         FDRE (Hold_fdre_C_D)         0.120     0.552    u_dut/n1_n0_sign_mul_reg
  -------------------------------------------------------------------
                         required time                         -0.552    
                         arrival time                           0.683    
  -------------------------------------------------------------------
                         slack                                  0.132    

Slack (MET) :             0.132ns  (arrival time - required time)
  Source:                 a_r_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_sign_mul_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.273ns  (logic 0.186ns (68.106%)  route 0.087ns (31.894%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.410     0.410    clk
    SLICE_X35Y75         FDRE                                         r  a_r_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y75         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  a_r_reg[25]/Q
                         net (fo=1, routed)           0.087     0.638    u_dut/io_input_payload_a_sign
    SLICE_X34Y75         LUT2 (Prop_lut2_I1_O)        0.045     0.683 r  u_dut/n1_n0_sign_mul_i_1/O
                         net (fo=1, routed)           0.000     0.683    u_dut/n0_sign_mul
    SLICE_X34Y75         FDRE                                         r  u_dut/n1_n0_sign_mul_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.432     0.432    u_dut/clk
    SLICE_X34Y75         FDRE                                         r  u_dut/n1_n0_sign_mul_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X34Y75         FDRE (Hold_fdre_C_D)         0.120     0.552    u_dut/n1_n0_sign_mul_reg
  -------------------------------------------------------------------
                         required time                         -0.552    
                         arrival time                           0.683    
  -------------------------------------------------------------------
                         slack                                  0.132    

Slack (MET) :             0.132ns  (arrival time - required time)
  Source:                 a_r_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_sign_mul_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.273ns  (logic 0.186ns (68.106%)  route 0.087ns (31.894%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.410     0.410    clk
    SLICE_X35Y75         FDRE                                         r  a_r_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y75         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  a_r_reg[25]/Q
                         net (fo=1, routed)           0.087     0.638    u_dut/io_input_payload_a_sign
    SLICE_X34Y75         LUT2 (Prop_lut2_I1_O)        0.045     0.683 f  u_dut/n1_n0_sign_mul_i_1/O
                         net (fo=1, routed)           0.000     0.683    u_dut/n0_sign_mul
    SLICE_X34Y75         FDRE                                         f  u_dut/n1_n0_sign_mul_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.432     0.432    u_dut/clk
    SLICE_X34Y75         FDRE                                         r  u_dut/n1_n0_sign_mul_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X34Y75         FDRE (Hold_fdre_C_D)         0.120     0.552    u_dut/n1_n0_sign_mul_reg
  -------------------------------------------------------------------
                         required time                         -0.552    
                         arrival time                           0.683    
  -------------------------------------------------------------------
                         slack                                  0.132    

Slack (MET) :             0.132ns  (arrival time - required time)
  Source:                 a_r_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_sign_mul_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.273ns  (logic 0.186ns (68.106%)  route 0.087ns (31.894%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.410     0.410    clk
    SLICE_X35Y75         FDRE                                         r  a_r_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y75         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  a_r_reg[25]/Q
                         net (fo=1, routed)           0.087     0.638    u_dut/io_input_payload_a_sign
    SLICE_X34Y75         LUT2 (Prop_lut2_I1_O)        0.045     0.683 f  u_dut/n1_n0_sign_mul_i_1/O
                         net (fo=1, routed)           0.000     0.683    u_dut/n0_sign_mul
    SLICE_X34Y75         FDRE                                         f  u_dut/n1_n0_sign_mul_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.432     0.432    u_dut/clk
    SLICE_X34Y75         FDRE                                         r  u_dut/n1_n0_sign_mul_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X34Y75         FDRE (Hold_fdre_C_D)         0.120     0.552    u_dut/n1_n0_sign_mul_reg
  -------------------------------------------------------------------
                         required time                         -0.552    
                         arrival time                           0.683    
  -------------------------------------------------------------------
                         slack                                  0.132    

Slack (MET) :             0.144ns  (arrival time - required time)
  Source:                 a_r_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_is_zero_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.285ns  (logic 0.186ns (65.209%)  route 0.099ns (34.791%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.410     0.410    clk
    SLICE_X15Y77         FDRE                                         r  a_r_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y77         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  a_r_reg[17]/Q
                         net (fo=4, routed)           0.099     0.650    u_dut/io_input_payload_a_exp[0]
    SLICE_X14Y77         LUT6 (Prop_lut6_I1_O)        0.045     0.695 r  u_dut/n1_n0_is_zero_i_1/O
                         net (fo=1, routed)           0.000     0.695    u_dut/n0_is_zero
    SLICE_X14Y77         FDRE                                         r  u_dut/n1_n0_is_zero_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.432     0.432    u_dut/clk
    SLICE_X14Y77         FDRE                                         r  u_dut/n1_n0_is_zero_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X14Y77         FDRE (Hold_fdre_C_D)         0.120     0.552    u_dut/n1_n0_is_zero_reg
  -------------------------------------------------------------------
                         required time                         -0.552    
                         arrival time                           0.695    
  -------------------------------------------------------------------
                         slack                                  0.144    

Slack (MET) :             0.144ns  (arrival time - required time)
  Source:                 a_r_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/n1_n0_is_zero_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.285ns  (logic 0.186ns (65.209%)  route 0.099ns (34.791%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.410     0.410    clk
    SLICE_X15Y77         FDRE                                         r  a_r_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y77         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  a_r_reg[17]/Q
                         net (fo=4, routed)           0.099     0.650    u_dut/io_input_payload_a_exp[0]
    SLICE_X14Y77         LUT6 (Prop_lut6_I1_O)        0.045     0.695 f  u_dut/n1_n0_is_zero_i_1/O
                         net (fo=1, routed)           0.000     0.695    u_dut/n0_is_zero
    SLICE_X14Y77         FDRE                                         f  u_dut/n1_n0_is_zero_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=169, unset)          0.432     0.432    u_dut/clk
    SLICE_X14Y77         FDRE                                         r  u_dut/n1_n0_is_zero_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X14Y77         FDRE (Hold_fdre_C_D)         0.120     0.552    u_dut/n1_n0_is_zero_reg
  -------------------------------------------------------------------
                         required time                         -0.552    
                         arrival time                           0.695    
  -------------------------------------------------------------------
                         slack                                  0.144    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.667
Sources:            { clk }

Check Type        Corner  Lib Pin  Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X13Y72  a_r_reg[0]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X12Y72  a_r_reg[10]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X13Y72  a_r_reg[11]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X13Y73  a_r_reg[12]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X12Y73  a_r_reg[13]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X12Y73  a_r_reg[14]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X12Y73  a_r_reg[15]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X13Y73  a_r_reg[16]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X15Y77  a_r_reg[17]/C
Min Period        n/a     FDRE/C   n/a            1.000         6.667       5.667      SLICE_X15Y77  a_r_reg[18]/C
Low Pulse Width   Slow    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X13Y72  a_r_reg[0]/C
Low Pulse Width   Fast    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X13Y72  a_r_reg[0]/C
Low Pulse Width   Slow    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X12Y72  a_r_reg[10]/C
Low Pulse Width   Fast    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X12Y72  a_r_reg[10]/C
Low Pulse Width   Slow    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X13Y72  a_r_reg[11]/C
Low Pulse Width   Fast    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X13Y72  a_r_reg[11]/C
Low Pulse Width   Slow    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X13Y73  a_r_reg[12]/C
Low Pulse Width   Fast    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X13Y73  a_r_reg[12]/C
Low Pulse Width   Slow    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X12Y73  a_r_reg[13]/C
Low Pulse Width   Fast    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X12Y73  a_r_reg[13]/C
High Pulse Width  Slow    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X13Y72  a_r_reg[0]/C
High Pulse Width  Fast    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X13Y72  a_r_reg[0]/C
High Pulse Width  Slow    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X12Y72  a_r_reg[10]/C
High Pulse Width  Fast    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X12Y72  a_r_reg[10]/C
High Pulse Width  Slow    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X13Y72  a_r_reg[11]/C
High Pulse Width  Fast    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X13Y72  a_r_reg[11]/C
High Pulse Width  Slow    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X13Y73  a_r_reg[12]/C
High Pulse Width  Fast    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X13Y73  a_r_reg[12]/C
High Pulse Width  Slow    FDRE/C   n/a            0.500         3.334       2.834      SLICE_X12Y73  a_r_reg[13]/C
High Pulse Width  Fast    FDRE/C   n/a            0.500         3.333       2.833      SLICE_X12Y73  a_r_reg[13]/C



