/----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3) -- Executing script file `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/flopoco_add_we8_wf17_dummyfpga_plain_single_f300/yosys.ys' -- 1. Executing GHDL. Importing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Importing module flopoco_add_we8_wf17_dummyfpga_plain_single_f300_Barch. Importing module rightshiftersticky18_by_max_20_freq300_uid4_Barch. Importing module intadder_21_freq300_uid6_Barch. Importing module normalizer_z_22_22_22_freq300_uid8_Barch. Importing module intadder_28_freq300_uid11_Barch. 2. Executing SYNTH_LATTICE pass. 2.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\VLO'. Generating RTLIL representation for module `\VHI'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\DP16KD'. Replacing existing blackbox module `\FD1P3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:2.1-2.261. Generating RTLIL representation for module `\FD1P3AX'. Replacing existing blackbox module `\FD1P3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:3.1-3.261. Generating RTLIL representation for module `\FD1P3AY'. Replacing existing blackbox module `\FD1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:4.1-4.261. Generating RTLIL representation for module `\FD1P3BX'. Replacing existing blackbox module `\FD1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:5.1-5.261. Generating RTLIL representation for module `\FD1P3DX'. Replacing existing blackbox module `\FD1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:6.1-6.261. Generating RTLIL representation for module `\FD1P3IX'. Replacing existing blackbox module `\FD1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:7.1-7.261. Generating RTLIL representation for module `\FD1P3JX'. Replacing existing blackbox module `\FD1S3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:8.1-8.261. Generating RTLIL representation for module `\FD1S3AX'. Replacing existing blackbox module `\FD1S3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:9.1-9.261. Generating RTLIL representation for module `\FD1S3AY'. Replacing existing blackbox module `\FD1S3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:10.1-10.261. Generating RTLIL representation for module `\FD1S3BX'. Replacing existing blackbox module `\FD1S3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:11.1-11.261. Generating RTLIL representation for module `\FD1S3DX'. Replacing existing blackbox module `\FD1S3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:12.1-12.261. Generating RTLIL representation for module `\FD1S3IX'. Replacing existing blackbox module `\FD1S3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:13.1-13.261. Generating RTLIL representation for module `\FD1S3JX'. Replacing existing blackbox module `\IFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:26.1-26.301. Generating RTLIL representation for module `\IFS1P3BX'. Replacing existing blackbox module `\IFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:27.1-27.301. Generating RTLIL representation for module `\IFS1P3DX'. Replacing existing blackbox module `\IFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:28.1-28.301. Generating RTLIL representation for module `\IFS1P3IX'. Replacing existing blackbox module `\IFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:29.1-29.301. Generating RTLIL representation for module `\IFS1P3JX'. Replacing existing blackbox module `\OFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:31.1-31.302. Generating RTLIL representation for module `\OFS1P3BX'. Replacing existing blackbox module `\OFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:32.1-32.302. Generating RTLIL representation for module `\OFS1P3DX'. Replacing existing blackbox module `\OFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:33.1-33.302. Generating RTLIL representation for module `\OFS1P3IX'. Replacing existing blackbox module `\OFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:34.1-34.302. Generating RTLIL representation for module `\OFS1P3JX'. Replacing existing blackbox module `\IB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:2.1-2.157. Generating RTLIL representation for module `\IB'. Replacing existing blackbox module `\IBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:3.1-3.157. Generating RTLIL representation for module `\IBPU'. Replacing existing blackbox module `\IBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:4.1-4.157. Generating RTLIL representation for module `\IBPD'. Replacing existing blackbox module `\OB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:5.1-5.157. Generating RTLIL representation for module `\OB'. Replacing existing blackbox module `\OBZ' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:6.1-6.164. Generating RTLIL representation for module `\OBZ'. Replacing existing blackbox module `\OBZPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:7.1-7.164. Generating RTLIL representation for module `\OBZPU'. Replacing existing blackbox module `\OBZPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:8.1-8.164. Generating RTLIL representation for module `\OBZPD'. Replacing existing blackbox module `\OBCO' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:9.1-9.90. Generating RTLIL representation for module `\OBCO'. Replacing existing blackbox module `\BB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:10.1-10.179. Generating RTLIL representation for module `\BB'. Replacing existing blackbox module `\BBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:11.1-11.179. Generating RTLIL representation for module `\BBPU'. Replacing existing blackbox module `\BBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:12.1-12.179. Generating RTLIL representation for module `\BBPD'. Replacing existing blackbox module `\ILVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:13.1-13.139. Generating RTLIL representation for module `\ILVDS'. Replacing existing blackbox module `\OLVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:14.1-14.146. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 2.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DCUA'. Successfully finished Verilog frontend. 2.3. Executing HIERARCHY pass (managing design hierarchy). 2.3.1. Analyzing design hierarchy.. Top module: \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300 Used module: \flopoco_add_we8_wf17_dummyfpga_plain_single_f300_Barch Used module: \intadder_28_freq300_uid11_Barch Used module: \normalizer_z_22_22_22_freq300_uid8_Barch Used module: \intadder_21_freq300_uid6_Barch Used module: \rightshiftersticky18_by_max_20_freq300_uid4_Barch 2.3.2. Analyzing design hierarchy.. Top module: \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300 Used module: \flopoco_add_we8_wf17_dummyfpga_plain_single_f300_Barch Used module: \intadder_28_freq300_uid11_Barch Used module: \normalizer_z_22_22_22_freq300_uid8_Barch Used module: \intadder_21_freq300_uid6_Barch Used module: \rightshiftersticky18_by_max_20_freq300_uid4_Barch Removed 0 unused modules. 2.4. Executing PROC pass (convert processes to netlists). 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4.4. Executing PROC_INIT pass (extract init attributes). 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module intadder_28_freq300_uid11_Barch. Optimizing module normalizer_z_22_22_22_freq300_uid8_Barch. Optimizing module intadder_21_freq300_uid6_Barch. Optimizing module rightshiftersticky18_by_max_20_freq300_uid4_Barch. Optimizing module flopoco_add_we8_wf17_dummyfpga_plain_single_f300_Barch. Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.5. Executing CHECK pass (checking for obvious problems). Checking module intadder_28_freq300_uid11_Barch... Checking module normalizer_z_22_22_22_freq300_uid8_Barch... Checking module intadder_21_freq300_uid6_Barch... Checking module rightshiftersticky18_by_max_20_freq300_uid4_Barch... Checking module flopoco_add_we8_wf17_dummyfpga_plain_single_f300_Barch... Checking module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300... Found and reported 0 problems. 2.6. Executing FLATTEN pass (flatten design). Deleting now unused module intadder_28_freq300_uid11_Barch. Deleting now unused module normalizer_z_22_22_22_freq300_uid8_Barch. Deleting now unused module intadder_21_freq300_uid6_Barch. Deleting now unused module rightshiftersticky18_by_max_20_freq300_uid4_Barch. Deleting now unused module flopoco_add_we8_wf17_dummyfpga_plain_single_f300_Barch. 2.7. Executing TRIBUF pass. 2.8. Executing DEMINOUT pass (demote inout ports to input or output). 2.9. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.10. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Removed 14 unused cells and 112 unused wires. 2.11. Executing CHECK pass (checking for obvious problems). Checking module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300... Found and reported 0 problems. 2.12. Executing OPT pass (performing simple optimizations). 2.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 218 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 216 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 2 cells. 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell u_dut.lzcandshifter.:513: \u_dut.lzcandshifter.level1_d1 -> { 1'1 \u_dut.lzcandshifter.level1_d1 [20:0] } Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Performed a total of 0 changes. 2.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 216 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 0 cells. 2.12.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.rightshiftercomponent.:433 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 1 on u_dut.rightshiftercomponent.:433 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 0 on u_dut.fracadder.:446 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 1 on u_dut.fracadder.:446 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 1-bit at position 19 on u_dut.fracadder.:446 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 20 on u_dut.fracadder.:446 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 0 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 1 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 2 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 3 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 4 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 5 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 6 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 7 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 8 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 9 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 10 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 11 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 12 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 13 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 14 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 15 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 16 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 17 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 18 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 19 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 20 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 21 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 22 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 23 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 24 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 25 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 26 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 27 on u_dut.roundingadder.:540 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Removed 0 unused cells and 2 unused wires. 2.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.12.9. Rerunning OPT passes. (Maybe there is more to do..) 2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Performed a total of 0 changes. 2.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 215 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 0 cells. 2.12.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.fracadder.:447 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 1 on u_dut.fracadder.:447 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 1-bit at position 19 on u_dut.fracadder.:447 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 20 on u_dut.fracadder.:447 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 0 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 1 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 2 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 3 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 4 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 5 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 6 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 7 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 8 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 9 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 10 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 11 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 12 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 13 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 14 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 15 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 16 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 17 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 18 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 19 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 20 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 21 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 22 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 23 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 24 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 25 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 26 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 27 on u_dut.roundingadder.:541 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. 2.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.12.16. Rerunning OPT passes. (Maybe there is more to do..) 2.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Performed a total of 0 changes. 2.12.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 214 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 0 cells. 2.12.20. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 1 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 2 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 3 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 4 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 5 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 6 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 7 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 8 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 9 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 10 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 11 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 12 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 13 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 14 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 15 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 16 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 17 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 18 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 19 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 20 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 21 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 22 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 23 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 24 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 25 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 26 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 27 on u_dut.roundingadder.:542 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. 2.12.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.12.23. Rerunning OPT passes. (Maybe there is more to do..) 2.12.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Performed a total of 0 changes. 2.12.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 213 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 0 cells. 2.12.27. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 1 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 2 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 3 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 4 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 5 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 6 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 7 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 8 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 9 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 10 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 11 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 12 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 13 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 14 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 15 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 16 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 17 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 18 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 19 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 20 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 21 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 22 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 23 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 24 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 25 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 26 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Setting constant 0-bit at position 27 on u_dut.roundingadder.:543 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.12.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. 2.12.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.12.30. Rerunning OPT passes. (Maybe there is more to do..) 2.12.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Performed a total of 0 changes. 2.12.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 212 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 0 cells. 2.12.34. Executing OPT_DFF pass (perform DFF optimizations). 2.12.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Removed 0 unused cells and 1 unused wires. 2.12.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.12.37. Rerunning OPT passes. (Maybe there is more to do..) 2.12.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Performed a total of 0 changes. 2.12.40. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 211 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 0 cells. 2.12.41. Executing OPT_DFF pass (perform DFF optimizations). 2.12.42. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. 2.12.43. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.12.44. Finished fast OPT passes. (There is nothing left to do.) 2.13. Executing FSM pass (extract and optimize FSM). 2.13.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.excrt_d1 as FSM state register: Users of register don't seem to benefit from recoding. 2.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. 2.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2.14. Executing OPT pass (performing simple optimizations). 2.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 211 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 0 cells. 2.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Performed a total of 0 changes. 2.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 211 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 0 cells. 2.14.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on :11 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300 (D = \u_dut.excrt2, Q = \R_o [27:26], rval = 2'00). Adding SRST signal on u_dut.lzcandshifter.:527 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300 (D = \u_dut.lzcandshifter.level2 [1:0], Q = \u_dut.lzcandshifter.level1_d1 [1:0], rval = 2'00). Adding SRST signal on u_dut.lzcandshifter.:523 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300 (D = { \u_dut.fracadder.r [14:0] \u_dut.sticky_d1 }, Q = \u_dut.lzcandshifter.level4_d1 [15:0], rval = 16'0000000000000000). Adding SRST signal on u_dut.rightshiftercomponent.:434 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300 (D = \u_dut.fracy [15:14], Q = \u_dut.rightshiftercomponent.level4_d1 [1:0], rval = 2'00). Adding SRST signal on u_dut.rightshiftercomponent.:434 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300 (D = \u_dut.fracy [17:2], Q = \u_dut.rightshiftercomponent.level4_d1 [19:4], rval = 16'0000000000000000). Adding SRST signal on u_dut.rightshiftercomponent.:432 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300 (D = \u_dut.expdiff [3:0], Q = \u_dut.rightshiftercomponent.ps_d1 [3:0], rval = 4'0100). Adding SRST signal on u_dut.:346 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300 (D = \u_dut.signr_d4, Q = \u_dut.signr2_d1, rval = 1'0). Adding SRST signal on u_dut.:332 ($dff) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300 (D = \u_dut.newx [25], Q = \u_dut.signr_d1, rval = 1'0). 2.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Removed 3 unused cells and 2 unused wires. 2.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.14.9. Rerunning OPT passes. (Maybe there is more to do..) 2.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Performed a total of 0 changes. 2.14.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 214 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 0 cells. 2.14.13. Executing OPT_DFF pass (perform DFF optimizations). 2.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. 2.14.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.14.16. Finished fast OPT passes. (There is nothing left to do.) 2.15. Executing WREDUCE pass (reducing word size of cells). Removed top 4 bits (of 18) from FF cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.$auto$ff.cc:337:slice$467 ($dff). Removed top 27 bits (of 28) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.roundingadder.:539 ($add). Removed top 1 bits (of 22) from mux cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.lzcandshifter.:513 ($mux). Removed top 20 bits (of 21) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.fracadder.:445 ($add). Removed top 16 bits (of 20) from mux cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.rightshiftercomponent.:368 ($mux). Removed top 20 bits (of 21) from FF cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:337 ($dff). Removed top 1 bits (of 4) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:304 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:295 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:293 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:290 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:274 ($eq). Removed top 1 bits (of 10) from port A of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:239 ($sub). Removed top 5 bits (of 10) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:239 ($sub). Removed top 1 bits (of 9) from port A of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:234 ($add). Removed top 8 bits (of 9) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:234 ($add). Removed top 1 bits (of 21) from port A of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.fracadder.:443 ($add). Removed top 1 bits (of 21) from port A of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:212 ($xor). Removed top 24 bits (of 32) from port A of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:196 ($gt). Removed top 27 bits (of 32) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:196 ($gt). Removed top 1 bits (of 6) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:175 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:172 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:163 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:160 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:151 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:148 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:139 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:136 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:133 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:121 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:118 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:109 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:106 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:97 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:95 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.u_dut.:85 ($eq). Removed top 2 bits (of 28) from wire top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.r_dut. 2.16. Executing PEEPOPT pass (run peephole optimizers). 2.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Removed 0 unused cells and 1 unused wires. 2.18. Executing SHARE pass (SAT-based resource sharing). 2.19. Executing TECHMAP pass (map to technology primitives). 2.19.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 2.19.2. Continuing TECHMAP pass. No more expansions possible. 2.20. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. 2.22. Executing TECHMAP pass (map to technology primitives). 2.22.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 2.22.2. Continuing TECHMAP pass. No more expansions possible. 2.23. Executing TECHMAP pass (map to technology primitives). 2.23.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. Generating RTLIL representation for module `$__MUL18X18'. Successfully finished Verilog frontend. 2.23.2. Continuing TECHMAP pass. No more expansions possible. 2.24. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300: creating $macc model for u_dut.fracadder.:443 ($add). creating $macc model for u_dut.:234 ($add). creating $macc model for u_dut.:239 ($sub). creating $macc model for u_dut.fracadder.:445 ($add). creating $macc model for u_dut.:57 ($sub). creating $macc model for u_dut.:54 ($sub). creating $macc model for u_dut.roundingadder.:539 ($add). merging $macc model for u_dut.fracadder.:443 into u_dut.fracadder.:445. creating $alu model for $macc u_dut.:54. creating $alu model for $macc u_dut.:57. creating $alu model for $macc u_dut.fracadder.:445. creating $alu model for $macc u_dut.:239. creating $alu model for $macc u_dut.:234. creating $alu model for $macc u_dut.roundingadder.:539. creating $alu model for u_dut.:196 ($gt): new $alu creating $alu model for u_dut.:49 ($lt): new $alu creating $alu cell for u_dut.:49: $auto$alumacc.cc:512:replace_alu$487 creating $alu cell for u_dut.:196: $auto$alumacc.cc:512:replace_alu$492 creating $alu cell for u_dut.roundingadder.:539: $auto$alumacc.cc:512:replace_alu$503 creating $alu cell for u_dut.:234: $auto$alumacc.cc:512:replace_alu$506 creating $alu cell for u_dut.:239: $auto$alumacc.cc:512:replace_alu$509 creating $alu cell for u_dut.fracadder.:445: $auto$alumacc.cc:512:replace_alu$512 creating $alu cell for u_dut.:57: $auto$alumacc.cc:512:replace_alu$515 creating $alu cell for u_dut.:54: $auto$alumacc.cc:512:replace_alu$518 created 8 $alu and 0 $macc cells. 2.25. Executing OPT pass (performing simple optimizations). 2.25.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.25.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 219 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 218 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 1 cells. 2.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux \u_dut.:197. dead port 2/2 on $mux \u_dut.:197. dead port 1/2 on $mux \u_dut.:50. dead port 2/2 on $mux \u_dut.:50. Removed 4 multiplexer ports. 2.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Performed a total of 0 changes. 2.25.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 216 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 0 cells. 2.25.6. Executing OPT_DFF pass (perform DFF optimizations). 2.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Removed 3 unused cells and 7 unused wires. 2.25.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.25.9. Rerunning OPT passes. (Maybe there is more to do..) 2.25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Performed a total of 0 changes. 2.25.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 213 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 0 cells. 2.25.13. Executing OPT_DFF pass (perform DFF optimizations). 2.25.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. 2.25.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.25.16. Finished fast OPT passes. (There is nothing left to do.) 2.26. Executing MEMORY pass. 2.26.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 2.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 2.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 2.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 2.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 2.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. 2.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 2.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. 2.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2.27. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. 2.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). 2.29. Executing TECHMAP pass (map to technology primitives). 2.29.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 2.29.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v' to AST representation. Generating RTLIL representation for module `$__DP16KD_'. Generating RTLIL representation for module `$__PDPW16KD_'. Successfully finished Verilog frontend. 2.29.3. Continuing TECHMAP pass. No more expansions possible. 2.30. Executing OPT pass (performing simple optimizations). 2.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 202 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 0 cells. 2.30.3. Executing OPT_DFF pass (perform DFF optimizations). 2.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Removed 0 unused cells and 13 unused wires. 2.30.5. Finished fast OPT passes. 2.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 2.32. Executing OPT pass (performing simple optimizations). 2.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 202 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 0 cells. 2.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Performed a total of 0 changes. 2.32.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 202 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 0 cells. 2.32.6. Executing OPT_DFF pass (perform DFF optimizations). 2.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. 2.32.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.32.9. Finished fast OPT passes. (There is nothing left to do.) 2.33. Executing TECHMAP pass (map to technology primitives). 2.33.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 2.33.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. Generating RTLIL representation for module `\_80_ccu2c_alu'. Successfully finished Verilog frontend. 2.33.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $xor. Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\_80_ccu2c_alu for cells of type $alu. Using template $paramod$cfcbb97e28b3a957f0a463a64fec87a7e9f92652\_80_ccu2c_alu for cells of type $alu. Using template $paramod$1937355a57c5bb91d22a1e030ed3f0d5c44d9991\_80_ccu2c_alu for cells of type $alu. Using template $paramod$a2af9b43308e3114c3b5dd3f4dc3329b2387395d\_80_ccu2c_alu for cells of type $alu. Using template $paramod$200b9977acfd333433396bc8e744688584077592\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $not. Using template $paramod$5d2e07eca6b9fbd538aff231e6f05d9604b7a77e\_80_ccu2c_alu for cells of type $alu. Using template $paramod$f02bbbf710bba6238f4bdfa41b3051acfe2064a8\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $pmux. Using extmapper simplemap for cells of type $logic_or. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $pos. No more expansions possible. 2.34. Executing OPT pass (performing simple optimizations). 2.34.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.34.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 1517 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 1376 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 1289 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 1267 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 250 cells. 2.34.3. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:337:slice$1577 ($_DFF_P_) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300 (D = $auto$simplemap.cc:189:logic_reduce$1896, Q = \u_dut.excrt_d1 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$1576 ($_DFF_P_) from module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300 (D = $auto$simplemap.cc:189:logic_reduce$1885, Q = \u_dut.excrt_d1 [0], rval = 1'1). 2.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Removed 343 unused cells and 683 unused wires. 2.34.5. Rerunning OPT passes. (Removed registers in this run.) 2.34.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.34.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 924 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 0 cells. 2.34.8. Executing OPT_DFF pass (perform DFF optimizations). 2.34.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. 2.34.10. Finished fast OPT passes. 2.35. Executing ABC pass (technology mapping using ABC). 2.35.1. Summary of detected clock domains: 5 cells in clk={ }, en={ }, arst={ }, srst={ } 2 cells in clk=\clk, en={ }, arst={ }, srst=$flatten\u_dut.$auto$ghdl.cc:862:import_module$140 13 cells in clk=\clk, en={ }, arst={ }, srst=$flatten\u_dut.$auto$ghdl.cc:862:import_module$86 117 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$1875 118 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$rtlil.cc:3303:Or$500 36 cells in clk=\clk, en={ }, arst={ }, srst=\u_dut.rightshiftercomponent.ps [4] 4 cells in clk=\clk, en={ }, arst={ }, srst=!\u_dut.rightshiftercomponent.ps [4] 44 cells in clk=\clk, en={ }, arst={ }, srst=\u_dut.lzcandshifter.count4 10 cells in clk=\clk, en={ }, arst={ }, srst=\u_dut.lzcandshifter.count1 42 cells in clk=\clk, en={ }, arst={ }, srst=$flatten\u_dut.$auto$ghdl.cc:862:import_module$138 533 cells in clk=\clk, en={ }, arst={ }, srst={ } 2.35.2. Extracting gate netlist of module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 2.35.3. Extracting gate netlist of module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by $flatten\u_dut.$auto$ghdl.cc:862:import_module$140 2.35.4. Extracting gate netlist of module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by $flatten\u_dut.$auto$ghdl.cc:862:import_module$86 2.35.5. Extracting gate netlist of module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$1875 2.35.5.1. Executed ABC. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 2.35.6. Extracting gate netlist of module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$rtlil.cc:3303:Or$500 2.35.7. Extracting gate netlist of module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by \u_dut.rightshiftercomponent.ps [4] 2.35.8. Extracting gate netlist of module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !\u_dut.rightshiftercomponent.ps [4] 2.35.9. Extracting gate netlist of module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by \u_dut.lzcandshifter.count4 2.35.10. Extracting gate netlist of module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by \u_dut.lzcandshifter.count1 2.35.11. Extracting gate netlist of module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by $flatten\u_dut.$auto$ghdl.cc:862:import_module$138 2.35.12. Extracting gate netlist of module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk 2.35.12.1. Executed ABC. Extracted 2 gates and 5 wires to a netlist network with 3 inputs and 2 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.12.2. Re-integrating ABC results. ABC RESULTS: AND cells: 1 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 1 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 3 ABC RESULTS: output signals: 2 Removing temp directory. 2.35.12.1. Executed ABC. Extracted 13 gates and 20 wires to a netlist network with 7 inputs and 11 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.12.2. Re-integrating ABC results. ABC RESULTS: AND cells: 1 ABC RESULTS: ANDNOT cells: 2 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 1 ABC RESULTS: MUX cells: 2 ABC RESULTS: NAND cells: 1 ABC RESULTS: NOR cells: 1 ABC RESULTS: NOT cells: 4 ABC RESULTS: OR cells: 2 ABC RESULTS: internal signals: 2 ABC RESULTS: input signals: 7 ABC RESULTS: output signals: 11 Removing temp directory. 2.35.12.1. Executed ABC. Extracted 117 gates and 132 wires to a netlist network with 15 inputs and 3 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.12.2. Re-integrating ABC results. ABC RESULTS: AND cells: 7 ABC RESULTS: ANDNOT cells: 2 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 11 ABC RESULTS: NOR cells: 1 ABC RESULTS: NOT cells: 2 ABC RESULTS: OR cells: 4 ABC RESULTS: ORNOT cells: 2 ABC RESULTS: internal signals: 114 ABC RESULTS: input signals: 15 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.12.1. Executed ABC. Extracted 114 gates and 157 wires to a netlist network with 42 inputs and 33 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.12.2. Re-integrating ABC results. ABC RESULTS: AND cells: 11 ABC RESULTS: ANDNOT cells: 11 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 4 ABC RESULTS: MUX cells: 74 ABC RESULTS: NAND cells: 3 ABC RESULTS: NOR cells: 7 ABC RESULTS: NOT cells: 1 ABC RESULTS: OR cells: 1 ABC RESULTS: internal signals: 82 ABC RESULTS: input signals: 42 ABC RESULTS: output signals: 33 Removing temp directory. 2.35.12.1. Executed ABC. Extracted 36 gates and 60 wires to a netlist network with 22 inputs and 35 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.12.2. Re-integrating ABC results. ABC RESULTS: AND cells: 26 ABC RESULTS: ANDNOT cells: 1 ABC RESULTS: BUF cells: 17 ABC RESULTS: DFF cells: 16 ABC RESULTS: MUX cells: 2 ABC RESULTS: NOT cells: 1 ABC RESULTS: OR cells: 5 ABC RESULTS: internal signals: 3 ABC RESULTS: input signals: 22 ABC RESULTS: output signals: 35 Removing temp directory. 2.35.12.1. Executed ABC. Extracted 4 gates and 8 wires to a netlist network with 3 inputs and 4 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.12.2. Re-integrating ABC results. ABC RESULTS: AND cells: 2 ABC RESULTS: BUF cells: 3 ABC RESULTS: DFF cells: 2 ABC RESULTS: OR cells: 1 ABC RESULTS: internal signals: 1 ABC RESULTS: input signals: 3 ABC RESULTS: output signals: 4 Removing temp directory. 2.35.12.1. Executed ABC. Extracted 36 gates and 56 wires to a netlist network with 19 inputs and 23 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.12.2. Re-integrating ABC results. ABC RESULTS: AND cells: 8 ABC RESULTS: ANDNOT cells: 3 ABC RESULTS: BUF cells: 22 ABC RESULTS: DFF cells: 16 ABC RESULTS: MUX cells: 6 ABC RESULTS: NAND cells: 1 ABC RESULTS: NOR cells: 2 ABC RESULTS: OR cells: 2 ABC RESULTS: internal signals: 14 ABC RESULTS: input signals: 19 ABC RESULTS: output signals: 23 Removing temp directory. 2.35.12.1. Executed ABC. Extracted 10 gates and 20 wires to a netlist network with 9 inputs and 7 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 10> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.12.2. Re-integrating ABC results. ABC RESULTS: AND cells: 4 ABC RESULTS: BUF cells: 1 ABC RESULTS: DFF cells: 2 ABC RESULTS: MUX cells: 2 ABC RESULTS: NAND cells: 1 ABC RESULTS: NOR cells: 2 ABC RESULTS: NOT cells: 1 ABC RESULTS: internal signals: 4 ABC RESULTS: input signals: 9 ABC RESULTS: output signals: 7 Removing temp directory. 2.35.12.1. Executed ABC. Extracted 42 gates and 54 wires to a netlist network with 11 inputs and 3 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 10> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.12.2. Re-integrating ABC results. ABC RESULTS: AND cells: 4 ABC RESULTS: DFF cells: 4 ABC RESULTS: NAND cells: 3 ABC RESULTS: NOR cells: 2 ABC RESULTS: NOT cells: 1 ABC RESULTS: OR cells: 5 ABC RESULTS: internal signals: 40 ABC RESULTS: input signals: 11 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.12.1. Executed ABC. Extracted 485 gates and 673 wires to a netlist network with 187 inputs and 212 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 10> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 265 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.12.2. Re-integrating ABC results. ABC RESULTS: AND cells: 31 ABC RESULTS: ANDNOT cells: 8 ABC RESULTS: BUF cells: 320 ABC RESULTS: DFF cells: 256 ABC RESULTS: MUX cells: 105 ABC RESULTS: NAND cells: 10 ABC RESULTS: NOR cells: 17 ABC RESULTS: NOT cells: 9 ABC RESULTS: OR cells: 18 ABC RESULTS: ORNOT cells: 4 ABC RESULTS: XOR cells: 21 ABC RESULTS: internal signals: 274 ABC RESULTS: input signals: 187 ABC RESULTS: output signals: 212 Removing temp directory. Removing global temp directory. 2.36. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Removed 0 unused cells and 1232 unused wires. 2.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2.38. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 836 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Computing hashes of 807 cells of `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Removed a total of 29 cells. 2.39. Executing TECHMAP pass (map to technology primitives). 2.39.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 2.39.2. Continuing TECHMAP pass. Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. No more expansions possible. 2.40. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2.42. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.43. Executing ATTRMVCP pass (move or copy attributes). 2.44. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300.. Removed 1 unused cells and 1295 unused wires. 2.45. Executing ABC pass (technology mapping using ABC). 2.45.1. Extracting gate netlist of module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300' to `/input.blif'.. 2.45.1.1. Executed ABC. Extracted 436 gates and 625 wires to a netlist network with 189 inputs and 150 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.45.1.2. Re-integrating ABC results. ABC RESULTS: AND cells: 66 ABC RESULTS: ANDNOT cells: 40 ABC RESULTS: MUX cells: 176 ABC RESULTS: NAND cells: 31 ABC RESULTS: NOR cells: 25 ABC RESULTS: NOT cells: 8 ABC RESULTS: OR cells: 29 ABC RESULTS: ORNOT cells: 7 ABC RESULTS: XNOR cells: 8 ABC RESULTS: XOR cells: 13 ABC RESULTS: internal signals: 286 ABC RESULTS: input signals: 189 ABC RESULTS: output signals: 150 Removing temp directory. Removing global temp directory. 2.46. Executing TECHMAP pass (map to technology primitives). 2.46.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v' to AST representation. Generating RTLIL representation for module `$_DLATCH_N_'. Generating RTLIL representation for module `$_DLATCH_P_'. Successfully finished Verilog frontend. 2.46.2. Continuing TECHMAP pass. No more expansions possible. 2.47. Executing ABC pass (technology mapping using ABC). 2.47.1. Summary of detected clock domains: 772 cells in clk={ }, en={ }, arst={ }, srst={ } 2.47.2. Extracting gate netlist of module `\top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 2.47.2.1. Executed ABC. Extracted 403 gates and 592 wires to a netlist network with 189 inputs and 150 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_lut /lutdefs.txt ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + dress /input.blif ABC: Total number of equiv classes = 245. ABC: Participating nodes from both networks = 496. ABC: Participating nodes from the first network = 246. ( 95.35 % of nodes) ABC: Participating nodes from the second network = 250. ( 96.90 % of nodes) ABC: Node pairs (any polarity) = 246. ( 95.35 % of names can be moved) ABC: Node pairs (same polarity) = 169. ( 65.50 % of names can be moved) ABC: Total runtime = 0.06 sec ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.47.2.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 257 ABC RESULTS: internal signals: 253 ABC RESULTS: input signals: 189 ABC RESULTS: output signals: 150 Removing temp directory. Removing global temp directory. Removed 0 unused cells and 1154 unused wires. 2.48. Executing TECHMAP pass (map to technology primitives). 2.48.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `$lut'. Successfully finished Verilog frontend. 2.48.2. Continuing TECHMAP pass. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110100 for cells of type $lut. Using template $paramod$80bc945f6d438f16387422ec284dc12b4bb4e68f$lut for cells of type $lut. Using template $paramod$60b758fd5679f6508bff32bea2afedb4f329e5f9$lut for cells of type $lut. Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba$lut for cells of type $lut. Using template $paramod$68ddec0fa51e887f01749f7dbab50dc0a13f0f42$lut for cells of type $lut. Using template $paramod$b4d59a169df3392cc49f75ff3f36786eb368b5e7$lut for cells of type $lut. Using template $paramod$8df4133c0925b18833ba1cf72fbaf6e43e80623e$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod$02124d42e8a5a4220d8c8e1235a8790f30076968$lut for cells of type $lut. Using template $paramod$df0b68f8e63b2deb6710e23abd8b8ff0796d4897$lut for cells of type $lut. Using template $paramod$12fb017f90e7463fe74789d2ec23494cce2be24a$lut for cells of type $lut. Using template $paramod$f63fe32f78d5f3c5de711945c592c8c5ec2303ae$lut for cells of type $lut. Using template $paramod$92d606332f1ee29cf1de0bfa0bc5c21b77f4493e$lut for cells of type $lut. Using template $paramod$bf0916c6d7935eef0257c8c924841f67bcefce14$lut for cells of type $lut. Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75$lut for cells of type $lut. Using template $paramod$e6a4aac14b366f7770f6afc50867b3b8176ebb96$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. Using template $paramod$f640e14f03c62b2b3b14623beef8e529772b0fd9$lut for cells of type $lut. Using template $paramod$162eacaa56f6f80a5a27551a5f2071c174364807$lut for cells of type $lut. Using template $paramod$1e85638df3738ceee271197a7526b228b39e55cd$lut for cells of type $lut. Using template $paramod$9433e4c46f315e866b05a89dd23fdca67281f9ef$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod$b6a2beb109dfa346ffae0582e15604ea80c4bc5f$lut for cells of type $lut. Using template $paramod$cd9589379b8100a20489a1bdd4f12f6f9b891b48$lut for cells of type $lut. Using template $paramod$cbfd30b70b4f0ac8dd1d3ed758215fbf49783a3b$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$ae21dc086791755288181dd4a1759489ee6a72c9$lut for cells of type $lut. Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a$lut for cells of type $lut. Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut. Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304$lut for cells of type $lut. Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9$lut for cells of type $lut. Using template $paramod$80fd3f90b6a7b38da9d25588666decbe3adaf5ec$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$179024403958176266098594f896ef320b086a21$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod$2902eb8ec3ca272968b5d8a7010e48f85069ed0f$lut for cells of type $lut. No more expansions possible. 2.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5401.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5403.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5452.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5609.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5611.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$5397$auto$blifparse.cc:557:parse_blif$5398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Removed 0 unused cells and 557 unused wires. 2.50. Executing AUTONAME pass. Renamed 1209 objects in module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300 (179 iterations). 2.51. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300'. Setting top module to top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300. 2.51.1. Analyzing design hierarchy.. Top module: \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300 2.51.2. Analyzing design hierarchy.. Top module: \top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300 Removed 0 unused modules. 2.52. Printing statistics. === top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300 === +----------Local Count, excluding submodules. | 558 wires 2663 wire bits 558 public wires 2663 public wire bits 4 ports 85 port bits 5 cells 5 $scopeinfo 761 submodules 60 CCU2C 20 L6MUX21 327 LUT4 50 PFUMX 304 TRELLIS_FF === design hierarchy === +----------Count including submodules. | 5 top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300 +----------Count including submodules. | 558 wires 2663 wire bits 558 public wires 2663 public wire bits 4 ports 85 port bits - memories - memory bits - processes 5 cells 5 $scopeinfo 761 submodules 60 CCU2C 20 L6MUX21 327 LUT4 50 PFUMX 304 TRELLIS_FF 2.53. Executing CHECK pass (checking for obvious problems). Checking module top_flopoco_add_we8_wf17_dummyfpga_plain_single_f300... Found and reported 0 problems. 2.54. Executing JSON backend. End of script. Logfile hash: 2ab58f4d52, time: 2.76s, user: 1.42s, system: 0.09s, MEM: 81.20 MB peak Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3) Time spent: 43% 3x abc (1 sec), 19% 13x read_verilog (0 sec), ... $ yosys -m ghdl -s /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/flopoco_add_we8_wf17_dummyfpga_plain_single_f300/yosys.ys [exit code 0]