/----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3) -- Executing script file `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/yosys.ys' -- 1. Executing Verilog-2005 frontend: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v Parsing SystemVerilog input from `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v' to AST representation. Generating RTLIL representation for module `\FpxxDiv'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/top_tommath_div_e8_m35_balanced_p3.v Parsing SystemVerilog input from `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/top_tommath_div_e8_m35_balanced_p3.v' to AST representation. Generating RTLIL representation for module `\top_tommath_div_e8_m35_balanced_p3'. Successfully finished Verilog frontend. 3. Executing SYNTH_LATTICE pass. 3.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\VLO'. Generating RTLIL representation for module `\VHI'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\DP16KD'. Replacing existing blackbox module `\FD1P3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:2.1-2.261. Generating RTLIL representation for module `\FD1P3AX'. Replacing existing blackbox module `\FD1P3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:3.1-3.261. Generating RTLIL representation for module `\FD1P3AY'. Replacing existing blackbox module `\FD1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:4.1-4.261. Generating RTLIL representation for module `\FD1P3BX'. Replacing existing blackbox module `\FD1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:5.1-5.261. Generating RTLIL representation for module `\FD1P3DX'. Replacing existing blackbox module `\FD1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:6.1-6.261. Generating RTLIL representation for module `\FD1P3IX'. Replacing existing blackbox module `\FD1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:7.1-7.261. Generating RTLIL representation for module `\FD1P3JX'. Replacing existing blackbox module `\FD1S3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:8.1-8.261. Generating RTLIL representation for module `\FD1S3AX'. Replacing existing blackbox module `\FD1S3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:9.1-9.261. Generating RTLIL representation for module `\FD1S3AY'. Replacing existing blackbox module `\FD1S3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:10.1-10.261. Generating RTLIL representation for module `\FD1S3BX'. Replacing existing blackbox module `\FD1S3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:11.1-11.261. Generating RTLIL representation for module `\FD1S3DX'. Replacing existing blackbox module `\FD1S3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:12.1-12.261. Generating RTLIL representation for module `\FD1S3IX'. Replacing existing blackbox module `\FD1S3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:13.1-13.261. Generating RTLIL representation for module `\FD1S3JX'. Replacing existing blackbox module `\IFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:26.1-26.301. Generating RTLIL representation for module `\IFS1P3BX'. Replacing existing blackbox module `\IFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:27.1-27.301. Generating RTLIL representation for module `\IFS1P3DX'. Replacing existing blackbox module `\IFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:28.1-28.301. Generating RTLIL representation for module `\IFS1P3IX'. Replacing existing blackbox module `\IFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:29.1-29.301. Generating RTLIL representation for module `\IFS1P3JX'. Replacing existing blackbox module `\OFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:31.1-31.302. Generating RTLIL representation for module `\OFS1P3BX'. Replacing existing blackbox module `\OFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:32.1-32.302. Generating RTLIL representation for module `\OFS1P3DX'. Replacing existing blackbox module `\OFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:33.1-33.302. Generating RTLIL representation for module `\OFS1P3IX'. Replacing existing blackbox module `\OFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:34.1-34.302. Generating RTLIL representation for module `\OFS1P3JX'. Replacing existing blackbox module `\IB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:2.1-2.157. Generating RTLIL representation for module `\IB'. Replacing existing blackbox module `\IBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:3.1-3.157. Generating RTLIL representation for module `\IBPU'. Replacing existing blackbox module `\IBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:4.1-4.157. Generating RTLIL representation for module `\IBPD'. Replacing existing blackbox module `\OB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:5.1-5.157. Generating RTLIL representation for module `\OB'. Replacing existing blackbox module `\OBZ' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:6.1-6.164. Generating RTLIL representation for module `\OBZ'. Replacing existing blackbox module `\OBZPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:7.1-7.164. Generating RTLIL representation for module `\OBZPU'. Replacing existing blackbox module `\OBZPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:8.1-8.164. Generating RTLIL representation for module `\OBZPD'. Replacing existing blackbox module `\OBCO' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:9.1-9.90. Generating RTLIL representation for module `\OBCO'. Replacing existing blackbox module `\BB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:10.1-10.179. Generating RTLIL representation for module `\BB'. Replacing existing blackbox module `\BBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:11.1-11.179. Generating RTLIL representation for module `\BBPU'. Replacing existing blackbox module `\BBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:12.1-12.179. Generating RTLIL representation for module `\BBPD'. Replacing existing blackbox module `\ILVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:13.1-13.139. Generating RTLIL representation for module `\ILVDS'. Replacing existing blackbox module `\OLVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:14.1-14.146. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 3.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DCUA'. Successfully finished Verilog frontend. 3.3. Executing HIERARCHY pass (managing design hierarchy). 3.3.1. Analyzing design hierarchy.. Top module: \top_tommath_div_e8_m35_balanced_p3 Used module: \FpxxDiv 3.3.2. Analyzing design hierarchy.. Top module: \top_tommath_div_e8_m35_balanced_p3 Used module: \FpxxDiv Removed 0 unused modules. 3.4. Executing PROC pass (convert processes to netlists). 3.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:140$61'. Cleaned up 0 empty switches. 3.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/top_tommath_div_e8_m35_balanced_p3.v:43$62 in module top_tommath_div_e8_m35_balanced_p3. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:269$58 in module FpxxDiv. Marked 3 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:246$54 in module FpxxDiv. Marked 3 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:230$53 in module FpxxDiv. Marked 3 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:214$52 in module FpxxDiv. Marked 3 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:192$46 in module FpxxDiv. Marked 3 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:176$45 in module FpxxDiv. Removed a total of 0 dead cases. 3.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 2 redundant assignments. Promoted 8 assignments to connections. 3.4.4. Executing PROC_INIT pass (extract init attributes). 3.4.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \reset in `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:269$58'. 3.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\top_tommath_div_e8_m35_balanced_p3.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/top_tommath_div_e8_m35_balanced_p3.v:43$62'. 1/2: $0\out_valid_r[0:0] 2/2: $0\in_valid_r[0:0] Creating decoders for process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. 1/42: $0\op_nan_p6[0:0] 2/42: $0\op_b_zero_p6[0:0] 3/42: $0\op_a_zero_p6[0:0] 4/42: $0\exp_adj_p6[9:0] 5/42: $0\div_adj_p6[34:0] 6/42: $0\sign_p6[0:0] 7/42: $0\op_nan_p5[0:0] 8/42: $0\op_b_zero_p5[0:0] 9/42: $0\op_a_zero_p5[0:0] 10/42: $0\exp_full_p5[9:0] 11/42: $0\div_p5[38:0] 12/42: $0\sign_p5[0:0] 13/42: $0\op_nan_p4[0:0] 14/42: $0\op_b_zero_p4[0:0] 15/42: $0\op_a_zero_p4[0:0] 16/42: $0\exp_full_p4[9:0] 17/42: $0\recip_yh2_p4[16:0] 18/42: $0\x_mul_yhyl_p4[38:0] 19/42: $0\sign_p4[0:0] 20/42: $0\op_nan_p3[0:0] 21/42: $0\op_b_zero_p3[0:0] 22/42: $0\op_a_zero_p3[0:0] 23/42: $0\exp_full_p3[9:0] 24/42: $0\recip_yh2_p3[16:0] 25/42: $0\x_mul_yhyl_p3[38:0] 26/42: $0\sign_p3[0:0] 27/42: $0\op_nan_p2[0:0] 28/42: $0\op_b_zero_p2[0:0] 29/42: $0\op_a_zero_p2[0:0] 30/42: $0\exp_full_p2[9:0] 31/42: $0\recip_yh2_p2[16:0] 32/42: $0\sign_p2[0:0] 33/42: $0\mant_a_p2[34:0] 34/42: $0\yh_m_yl_p2[35:0] 35/42: $0\recip_exp_p1[1:0] 36/42: $0\op_nan_p1[0:0] 37/42: $0\op_b_zero_p1[0:0] 38/42: $0\op_a_zero_p1[0:0] 39/42: $0\sign_p1[0:0] 40/42: $0\exp_p1[8:0] 41/42: $0\mant_a_p1[34:0] 42/42: $0\yh_m_yl_p1[35:0] Creating decoders for process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:269$58'. 1/6: $0\p6_vld[0:0] 2/6: $0\p5_vld[0:0] 3/6: $0\p4_vld[0:0] 4/6: $0\p3_vld[0:0] 5/6: $0\p2_vld[0:0] 6/6: $0\p1_vld[0:0] Creating decoders for process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:246$54'. 1/4: $3\div_final_p6[34:0] 2/4: $2\div_final_p6[34:0] 3/4: $1\div_final_p6[34:0] [34] 4/4: $1\div_final_p6[34:0] [33:0] Creating decoders for process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:230$53'. 1/3: $3\exp_final_p6[7:0] 2/3: $2\exp_final_p6[7:0] 3/3: $1\exp_final_p6[7:0] Creating decoders for process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:214$52'. 1/3: $3\sign_final_p6[0:0] 2/3: $2\sign_final_p6[0:0] 3/3: $1\sign_final_p6[0:0] Creating decoders for process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:192$46'. 1/3: $3\exp_delta_p5[2:0] 2/3: $2\exp_delta_p5[2:0] 3/3: $1\exp_delta_p5[2:0] Creating decoders for process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:176$45'. 1/3: $3\shift_adj_p5[1:0] 2/3: $2\shift_adj_p5[1:0] 3/3: $1\shift_adj_p5[1:0] Creating decoders for process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:143$3'. 1/1: $0\_zz_div_table_port0[15:0] 3.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `\FpxxDiv.\div_final_p6' from process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:246$54'. No latch inferred for signal `\FpxxDiv.\exp_final_p6' from process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:230$53'. No latch inferred for signal `\FpxxDiv.\sign_final_p6' from process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:214$52'. No latch inferred for signal `\FpxxDiv.\exp_delta_p5' from process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:192$46'. No latch inferred for signal `\FpxxDiv.\shift_adj_p5' from process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:176$45'. 3.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\top_tommath_div_e8_m35_balanced_p3.\a_r' using process `\top_tommath_div_e8_m35_balanced_p3.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/top_tommath_div_e8_m35_balanced_p3.v:43$62'. created $dff cell `$procdff$484' with positive edge clock. Creating register for signal `\top_tommath_div_e8_m35_balanced_p3.\b_r' using process `\top_tommath_div_e8_m35_balanced_p3.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/top_tommath_div_e8_m35_balanced_p3.v:43$62'. created $dff cell `$procdff$485' with positive edge clock. Creating register for signal `\top_tommath_div_e8_m35_balanced_p3.\in_valid_r' using process `\top_tommath_div_e8_m35_balanced_p3.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/top_tommath_div_e8_m35_balanced_p3.v:43$62'. created $dff cell `$procdff$486' with positive edge clock. Creating register for signal `\top_tommath_div_e8_m35_balanced_p3.\y_r' using process `\top_tommath_div_e8_m35_balanced_p3.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/top_tommath_div_e8_m35_balanced_p3.v:43$62'. created $dff cell `$procdff$487' with positive edge clock. Creating register for signal `\top_tommath_div_e8_m35_balanced_p3.\out_valid_r' using process `\top_tommath_div_e8_m35_balanced_p3.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/top_tommath_div_e8_m35_balanced_p3.v:43$62'. created $dff cell `$procdff$488' with positive edge clock. Creating register for signal `\FpxxDiv.\yh_m_yl_p1' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$489' with positive edge clock. Creating register for signal `\FpxxDiv.\mant_a_p1' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$490' with positive edge clock. Creating register for signal `\FpxxDiv.\exp_p1' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$491' with positive edge clock. Creating register for signal `\FpxxDiv.\sign_p1' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$492' with positive edge clock. Creating register for signal `\FpxxDiv.\op_a_zero_p1' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$493' with positive edge clock. Creating register for signal `\FpxxDiv.\op_b_zero_p1' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$494' with positive edge clock. Creating register for signal `\FpxxDiv.\op_nan_p1' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$495' with positive edge clock. Creating register for signal `\FpxxDiv.\recip_exp_p1' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$496' with positive edge clock. Creating register for signal `\FpxxDiv.\yh_m_yl_p2' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$497' with positive edge clock. Creating register for signal `\FpxxDiv.\mant_a_p2' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$498' with positive edge clock. Creating register for signal `\FpxxDiv.\sign_p2' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$499' with positive edge clock. Creating register for signal `\FpxxDiv.\recip_yh2_p2' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$500' with positive edge clock. Creating register for signal `\FpxxDiv.\exp_full_p2' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$501' with positive edge clock. Creating register for signal `\FpxxDiv.\op_a_zero_p2' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$502' with positive edge clock. Creating register for signal `\FpxxDiv.\op_b_zero_p2' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$503' with positive edge clock. Creating register for signal `\FpxxDiv.\op_nan_p2' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$504' with positive edge clock. Creating register for signal `\FpxxDiv.\sign_p3' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$505' with positive edge clock. Creating register for signal `\FpxxDiv.\x_mul_yhyl_p3' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$506' with positive edge clock. Creating register for signal `\FpxxDiv.\recip_yh2_p3' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$507' with positive edge clock. Creating register for signal `\FpxxDiv.\exp_full_p3' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$508' with positive edge clock. Creating register for signal `\FpxxDiv.\op_a_zero_p3' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$509' with positive edge clock. Creating register for signal `\FpxxDiv.\op_b_zero_p3' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$510' with positive edge clock. Creating register for signal `\FpxxDiv.\op_nan_p3' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$511' with positive edge clock. Creating register for signal `\FpxxDiv.\sign_p4' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$512' with positive edge clock. Creating register for signal `\FpxxDiv.\x_mul_yhyl_p4' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$513' with positive edge clock. Creating register for signal `\FpxxDiv.\recip_yh2_p4' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$514' with positive edge clock. Creating register for signal `\FpxxDiv.\exp_full_p4' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$515' with positive edge clock. Creating register for signal `\FpxxDiv.\op_a_zero_p4' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$516' with positive edge clock. Creating register for signal `\FpxxDiv.\op_b_zero_p4' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$517' with positive edge clock. Creating register for signal `\FpxxDiv.\op_nan_p4' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$518' with positive edge clock. Creating register for signal `\FpxxDiv.\sign_p5' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$519' with positive edge clock. Creating register for signal `\FpxxDiv.\div_p5' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$520' with positive edge clock. Creating register for signal `\FpxxDiv.\exp_full_p5' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$521' with positive edge clock. Creating register for signal `\FpxxDiv.\op_a_zero_p5' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$522' with positive edge clock. Creating register for signal `\FpxxDiv.\op_b_zero_p5' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$523' with positive edge clock. Creating register for signal `\FpxxDiv.\op_nan_p5' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$524' with positive edge clock. Creating register for signal `\FpxxDiv.\sign_p6' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$525' with positive edge clock. Creating register for signal `\FpxxDiv.\div_adj_p6' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$526' with positive edge clock. Creating register for signal `\FpxxDiv.\exp_adj_p6' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$527' with positive edge clock. Creating register for signal `\FpxxDiv.\op_a_zero_p6' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$528' with positive edge clock. Creating register for signal `\FpxxDiv.\op_b_zero_p6' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$529' with positive edge clock. Creating register for signal `\FpxxDiv.\op_nan_p6' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. created $dff cell `$procdff$530' with positive edge clock. Creating register for signal `\FpxxDiv.\p1_vld' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:269$58'. created $adff cell `$procdff$533' with positive edge clock and positive level reset. Creating register for signal `\FpxxDiv.\p2_vld' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:269$58'. created $adff cell `$procdff$536' with positive edge clock and positive level reset. Creating register for signal `\FpxxDiv.\p3_vld' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:269$58'. created $adff cell `$procdff$539' with positive edge clock and positive level reset. Creating register for signal `\FpxxDiv.\p4_vld' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:269$58'. created $adff cell `$procdff$542' with positive edge clock and positive level reset. Creating register for signal `\FpxxDiv.\p5_vld' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:269$58'. created $adff cell `$procdff$545' with positive edge clock and positive level reset. Creating register for signal `\FpxxDiv.\p6_vld' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:269$58'. created $adff cell `$procdff$548' with positive edge clock and positive level reset. Creating register for signal `\FpxxDiv.\_zz_div_table_port0' using process `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:143$3'. created $dff cell `$procdff$549' with positive edge clock. 3.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\top_tommath_div_e8_m35_balanced_p3.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/top_tommath_div_e8_m35_balanced_p3.v:43$62'. Removing empty process `top_tommath_div_e8_m35_balanced_p3.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/top_tommath_div_e8_m35_balanced_p3.v:43$62'. Found and cleaned up 42 empty switches in `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. Removing empty process `FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:299$59'. Found and cleaned up 6 empty switches in `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:269$58'. Removing empty process `FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:269$58'. Found and cleaned up 3 empty switches in `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:246$54'. Removing empty process `FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:246$54'. Found and cleaned up 3 empty switches in `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:230$53'. Removing empty process `FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:230$53'. Found and cleaned up 3 empty switches in `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:214$52'. Removing empty process `FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:214$52'. Found and cleaned up 3 empty switches in `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:192$46'. Removing empty process `FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:192$46'. Found and cleaned up 3 empty switches in `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:176$45'. Removing empty process `FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:176$45'. Found and cleaned up 1 empty switch in `\FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:143$3'. Removing empty process `FpxxDiv.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:143$3'. Cleaned up 65 empty switches. 3.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.5. Executing CHECK pass (checking for obvious problems). Checking module top_tommath_div_e8_m35_balanced_p3... Checking module FpxxDiv... Found and reported 0 problems. 3.6. Executing FLATTEN pass (flatten design). Keeping top_tommath_div_e8_m35_balanced_p3.u_dut (found keep_hierarchy attribute). 3.7. Executing TRIBUF pass. 3.8. Executing DEMINOUT pass (demote inout ports to input or output). 3.9. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.10. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. Removed 0 unused cells and 196 unused wires. 3.11. Executing CHECK pass (checking for obvious problems). Checking module top_tommath_div_e8_m35_balanced_p3... Checking module FpxxDiv... Found and reported 0 problems. 3.12. Executing OPT pass (performing simple optimizations). 3.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 8 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 171 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Computing hashes of 165 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 6 cells. 3.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_div_e8_m35_balanced_p3.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \FpxxDiv.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux $procmux$477. dead port 1/2 on $mux $procmux$471. dead port 1/2 on $mux $procmux$468. dead port 1/2 on $mux $procmux$459. dead port 1/2 on $mux $procmux$453. dead port 1/2 on $mux $procmux$450. dead port 1/2 on $mux $procmux$441. dead port 1/2 on $mux $procmux$435. dead port 1/2 on $mux $procmux$432. dead port 1/2 on $mux $procmux$424. dead port 1/2 on $mux $procmux$418. dead port 1/2 on $mux $procmux$415. dead port 1/2 on $mux $procmux$403. dead port 1/2 on $mux $procmux$397. dead port 1/2 on $mux $procmux$394. Removed 15 multiplexer ports. 3.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_div_e8_m35_balanced_p3. Optimizing cells in module \FpxxDiv. Performed a total of 0 changes. 3.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 8 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 150 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 0 cells. 3.12.6. Executing OPT_DFF pass (perform DFF optimizations). 3.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. Removed 0 unused cells and 21 unused wires. 3.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.12.9. Rerunning OPT passes. (Maybe there is more to do..) 3.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_div_e8_m35_balanced_p3.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \FpxxDiv.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_div_e8_m35_balanced_p3. Optimizing cells in module \FpxxDiv. Performed a total of 0 changes. 3.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 8 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 148 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 0 cells. 3.12.13. Executing OPT_DFF pass (perform DFF optimizations). 3.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. Removed 0 unused cells and 1 unused wires. 3.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.12.16. Rerunning OPT passes. (Maybe there is more to do..) 3.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_div_e8_m35_balanced_p3.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \FpxxDiv.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_div_e8_m35_balanced_p3. Optimizing cells in module \FpxxDiv. Performed a total of 0 changes. 3.12.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 8 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 148 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 0 cells. 3.12.20. Executing OPT_DFF pass (perform DFF optimizations). 3.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. 3.12.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.12.23. Finished fast OPT passes. (There is nothing left to do.) 3.13. Executing FSM pass (extract and optimize FSM). 3.13.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking FpxxDiv.recip_exp_p1 as FSM state register: Users of register don't seem to benefit from recoding. 3.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). 3.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). 3.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. 3.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). 3.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 3.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 3.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 3.14. Executing OPT pass (performing simple optimizations). 3.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 8 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 148 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 0 cells. 3.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_div_e8_m35_balanced_p3.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \FpxxDiv.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_div_e8_m35_balanced_p3. Optimizing cells in module \FpxxDiv. Performed a total of 0 changes. 3.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 8 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 148 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 0 cells. 3.14.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $procdff$486 ($dff) from module top_tommath_div_e8_m35_balanced_p3 (D = \in_valid_i, Q = \in_valid_r, rval = 1'0). Adding SRST signal on $procdff$488 ($dff) from module top_tommath_div_e8_m35_balanced_p3 (D = \dut_valid, Q = \out_valid_r, rval = 1'0). Adding EN signal on $procdff$523 ($dff) from module FpxxDiv (D = \op_b_zero_p4, Q = \op_b_zero_p5). Adding EN signal on $procdff$524 ($dff) from module FpxxDiv (D = \op_nan_p4, Q = \op_nan_p5). Adding EN signal on $procdff$525 ($dff) from module FpxxDiv (D = \sign_p5, Q = \sign_p6). Adding EN signal on $procdff$526 ($dff) from module FpxxDiv (D = \_zz_div_adj_p5 [34:0], Q = \div_adj_p6). Adding EN signal on $procdff$527 ($dff) from module FpxxDiv (D = \exp_adj_p5, Q = \exp_adj_p6). Adding EN signal on $procdff$528 ($dff) from module FpxxDiv (D = \op_a_zero_p5, Q = \op_a_zero_p6). Adding EN signal on $procdff$549 ($dff) from module FpxxDiv (D = $memrd$\div_table$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:145$4_DATA, Q = \_zz_div_table_port0). Adding EN signal on $procdff$530 ($dff) from module FpxxDiv (D = \op_nan_p5, Q = \op_nan_p6). Adding EN signal on $procdff$529 ($dff) from module FpxxDiv (D = \op_b_zero_p5, Q = \op_b_zero_p6). Adding EN signal on $procdff$508 ($dff) from module FpxxDiv (D = \exp_full_p2, Q = \exp_full_p3). Adding EN signal on $procdff$509 ($dff) from module FpxxDiv (D = \op_a_zero_p2, Q = \op_a_zero_p3). Adding EN signal on $procdff$510 ($dff) from module FpxxDiv (D = \op_b_zero_p2, Q = \op_b_zero_p3). Adding EN signal on $procdff$511 ($dff) from module FpxxDiv (D = \op_nan_p2, Q = \op_nan_p3). Adding EN signal on $procdff$512 ($dff) from module FpxxDiv (D = \sign_p3, Q = \sign_p4). Adding EN signal on $procdff$513 ($dff) from module FpxxDiv (D = \x_mul_yhyl_p3, Q = \x_mul_yhyl_p4). Adding EN signal on $procdff$514 ($dff) from module FpxxDiv (D = \recip_yh2_p3, Q = \recip_yh2_p4). Adding EN signal on $procdff$515 ($dff) from module FpxxDiv (D = \exp_full_p3, Q = \exp_full_p4). Adding EN signal on $procdff$507 ($dff) from module FpxxDiv (D = \recip_yh2_p2, Q = \recip_yh2_p3). Adding EN signal on $procdff$516 ($dff) from module FpxxDiv (D = \op_a_zero_p3, Q = \op_a_zero_p4). Adding EN signal on $procdff$506 ($dff) from module FpxxDiv (D = \x_mul_yhyl_full_p2 [71:33], Q = \x_mul_yhyl_p3). Adding EN signal on $procdff$517 ($dff) from module FpxxDiv (D = \op_b_zero_p3, Q = \op_b_zero_p4). Adding EN signal on $procdff$518 ($dff) from module FpxxDiv (D = \op_nan_p3, Q = \op_nan_p4). Adding EN signal on $procdff$519 ($dff) from module FpxxDiv (D = \sign_p4, Q = \sign_p5). Adding EN signal on $procdff$520 ($dff) from module FpxxDiv (D = \div_full_p4 [55:17], Q = \div_p5). Adding EN signal on $procdff$521 ($dff) from module FpxxDiv (D = \exp_full_p4, Q = \exp_full_p5). Adding EN signal on $procdff$522 ($dff) from module FpxxDiv (D = \op_a_zero_p4, Q = \op_a_zero_p5). Adding EN signal on $procdff$489 ($dff) from module FpxxDiv (D = \yh_m_yl_p0, Q = \yh_m_yl_p1). Adding EN signal on $procdff$490 ($dff) from module FpxxDiv (D = \io_op_a_mant, Q = \mant_a_p1). Adding EN signal on $procdff$491 ($dff) from module FpxxDiv (D = \exp_p0, Q = \exp_p1). Adding EN signal on $procdff$492 ($dff) from module FpxxDiv (D = \sign_p0, Q = \sign_p1). Adding EN signal on $procdff$493 ($dff) from module FpxxDiv (D = \op_a_zero_p0, Q = \op_a_zero_p1). Adding EN signal on $procdff$494 ($dff) from module FpxxDiv (D = \op_b_zero_p0, Q = \op_b_zero_p1). Adding EN signal on $procdff$495 ($dff) from module FpxxDiv (D = \op_nan_p0, Q = \op_nan_p1). Adding EN signal on $procdff$496 ($dff) from module FpxxDiv (D = \recip_exp_p0, Q = \recip_exp_p1). Adding SRST signal on $auto$ff.cc:337:slice$585 ($dffe) from module FpxxDiv (D = $ternary$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:161$39_Y, Q = \recip_exp_p1, rval = 2'00). Adding EN signal on $procdff$497 ($dff) from module FpxxDiv (D = \yh_m_yl_p1, Q = \yh_m_yl_p2). Adding EN signal on $procdff$498 ($dff) from module FpxxDiv (D = \mant_a_p1, Q = \mant_a_p2). Adding EN signal on $procdff$499 ($dff) from module FpxxDiv (D = \sign_p1, Q = \sign_p2). Adding EN signal on $procdff$500 ($dff) from module FpxxDiv (D = { 1'1 \_zz_div_table_port0 }, Q = \recip_yh2_p2). Adding EN signal on $procdff$501 ($dff) from module FpxxDiv (D = \exp_full_p1, Q = \exp_full_p2). Adding EN signal on $procdff$502 ($dff) from module FpxxDiv (D = \op_a_zero_p1, Q = \op_a_zero_p2). Adding EN signal on $procdff$503 ($dff) from module FpxxDiv (D = \op_b_zero_p1, Q = \op_b_zero_p2). Adding EN signal on $procdff$504 ($dff) from module FpxxDiv (D = \op_nan_p1, Q = \op_nan_p2). Adding EN signal on $procdff$505 ($dff) from module FpxxDiv (D = \sign_p2, Q = \sign_p3). Setting constant 1-bit at position 16 on $auto$ff.cc:337:slice$590 ($dffe) from module FpxxDiv. 3.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. Removed 46 unused cells and 46 unused wires. 3.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.14.9. Rerunning OPT passes. (Maybe there is more to do..) 3.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_div_e8_m35_balanced_p3.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \FpxxDiv.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_div_e8_m35_balanced_p3. Optimizing cells in module \FpxxDiv. Performed a total of 0 changes. 3.14.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 6 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 104 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 0 cells. 3.14.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 16 on $auto$ff.cc:337:slice$569 ($dffe) from module FpxxDiv. 3.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. 3.14.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.14.16. Rerunning OPT passes. (Maybe there is more to do..) 3.14.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_div_e8_m35_balanced_p3.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \FpxxDiv.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.14.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_div_e8_m35_balanced_p3. Optimizing cells in module \FpxxDiv. Performed a total of 0 changes. 3.14.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 6 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 104 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 0 cells. 3.14.20. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 16 on $auto$ff.cc:337:slice$567 ($dffe) from module FpxxDiv. 3.14.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. 3.14.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.14.23. Rerunning OPT passes. (Maybe there is more to do..) 3.14.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_div_e8_m35_balanced_p3.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \FpxxDiv.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.14.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_div_e8_m35_balanced_p3. Optimizing cells in module \FpxxDiv. Performed a total of 0 changes. 3.14.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 6 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 104 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 0 cells. 3.14.27. Executing OPT_DFF pass (perform DFF optimizations). 3.14.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. 3.14.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.14.30. Finished fast OPT passes. (There is nothing left to do.) 3.15. Executing WREDUCE pass (reducing word size of cells). Removed top 24 address bits (of 32) from memory init port FpxxDiv.$meminit$\div_table$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:141$60 (div_table). Converting cell FpxxDiv.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:133$1 ($sub) from unsigned to signed. Removed top 1 bits (of 10) from port A of cell FpxxDiv.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:133$1 ($sub). Removed top 7 bits (of 10) from port B of cell FpxxDiv.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:133$1 ($sub). Removed top 4 bits (of 39) from port Y of cell FpxxDiv.$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:137$2 ($sshr). Removed top 19 bits (of 36) from port B of cell FpxxDiv.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:151$6 ($sub). Converting cell FpxxDiv.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:153$8 ($sub) from signed to unsigned. Removed top 1 bits (of 9) from port A of cell FpxxDiv.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:153$8 ($sub). Removed top 1 bits (of 9) from port B of cell FpxxDiv.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:153$8 ($sub). Removed top 1 bits (of 8) from port B of cell FpxxDiv.$lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:161$38 ($lt). Removed top 1 bits (of 10) from port B of cell FpxxDiv.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:165$41 ($add). Removed top 1 bits (of 2) from port B of cell FpxxDiv.$eq$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:208$47 ($eq). Removed top 2 bits (of 3) from port B of cell FpxxDiv.$eq$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:209$48 ($eq). Removed top 7 bits (of 10) from port B of cell FpxxDiv.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:211$49 ($add). Removed top 1 bits (of 10) from port A of cell FpxxDiv.$le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:263$55 ($le). Removed top 9 bits (of 10) from port B of cell FpxxDiv.$le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:264$57 ($le). Removed top 2 bits (of 3) from mux cell FpxxDiv.$procmux$447 ($mux). Removed top 1 bits (of 2) from mux cell FpxxDiv.$procmux$465 ($mux). Removed top 2 bits (of 3) from wire FpxxDiv.$3\exp_delta_p5[2:0]. Removed top 1 bits (of 2) from wire FpxxDiv.$3\shift_adj_p5[1:0]. Removed top 1 bits (of 17) from wire FpxxDiv.recip_yh2_p4. Removed top 1 bits (of 17) from wire FpxxDiv.recip_yh2_p3. Removed top 1 bits (of 17) from wire FpxxDiv.recip_yh2_p2. Removed top 1 bits (of 36) from wire FpxxDiv.yh_p0. 3.16. Executing PEEPOPT pass (run peephole optimizers). 3.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. Removed 0 unused cells and 6 unused wires. 3.18. Executing SHARE pass (SAT-based resource sharing). 3.19. Executing TECHMAP pass (map to technology primitives). 3.19.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 3.19.2. Continuing TECHMAP pass. No more expansions possible. 3.20. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. 3.22. Executing TECHMAP pass (map to technology primitives). 3.22.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 3.22.2. Continuing TECHMAP pass. Using template $paramod$d03d51e46aa6720f7257e5a663156a9a28d64d1d\_80_mul for cells of type $mul. Using template $paramod$59bfdbefb2a69ea86adc35f7e843430ddff48cfa\_80_mul for cells of type $mul. Using template $paramod$60d8ed60b2dcdbf3459044a0a02f78dfe9e72818\_80_mul for cells of type $__mul. Using template $paramod$19ef985a4ee9e062e79c85730411595c5981ac12\_80_mul for cells of type $__mul. Using template $paramod$7ad493862d67ec9b3d22282c42f544cd2ef4f196\_80_mul for cells of type $__mul. Using template $paramod$4d9c00726d012270364e62e1b6281140b94a78e5\_80_mul for cells of type $__mul. No more expansions possible. 3.23. Executing TECHMAP pass (map to technology primitives). 3.23.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. Generating RTLIL representation for module `$__MUL18X18'. Successfully finished Verilog frontend. 3.23.2. Continuing TECHMAP pass. Using template $paramod$e2221a8e1c62487f5036e26a39a075aafac8168d$__MUL18X18 for cells of type $__MUL18X18. Using template $paramod$fe40a425568926b0164c524e57bf5a0b343ac3df$__MUL18X18 for cells of type $__MUL18X18. Using template $paramod$6d12bf30e693aad43884066ff41c02c3d61c4f33$__MUL18X18 for cells of type $__MUL18X18. No more expansions possible. 3.24. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top_tommath_div_e8_m35_balanced_p3: created 0 $alu and 0 $macc cells. Extracting $alu and $macc cells in module FpxxDiv: creating $macc model for $techmap$mul$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:168$42.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$620 ($add). creating $macc model for $techmap$mul$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:168$42.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$620 ($add). creating $macc model for $techmap$mul$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:172$43.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$616 ($add). creating $macc model for $techmap$mul$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:172$43.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:159$613 ($add). creating $macc model for $techmap$mul$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:168$42.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$609 ($add). creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:211$49 ($add). creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:165$41 ($add). creating $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:153$8 ($sub). creating $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:151$6 ($sub). creating $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:133$1 ($sub). merging $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:133$1 into $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:165$41. merging $macc model for $techmap$mul$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:172$43.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:159$613 into $techmap$mul$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:172$43.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$616. creating $alu model for $macc $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:153$8. creating $alu model for $macc $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:211$49. creating $alu model for $macc $techmap$mul$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:168$42.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$609. creating $alu model for $macc $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:151$6. creating $alu model for $macc $techmap$mul$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:168$42.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$620. creating $alu model for $macc $techmap$mul$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:168$42.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$620. creating $macc cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:165$41: $auto$alumacc.cc:382:replace_macc$635 creating $macc cell for $techmap$mul$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:172$43.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$616: $auto$alumacc.cc:382:replace_macc$636 creating $alu model for $le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:264$57 ($le): new $alu creating $alu model for $le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:263$55 ($le): new $alu creating $alu model for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:161$38 ($lt): new $alu creating $alu cell for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:161$38: $auto$alumacc.cc:512:replace_alu$640 creating $alu cell for $le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:263$55: $auto$alumacc.cc:512:replace_alu$645 creating $alu cell for $le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:264$57: $auto$alumacc.cc:512:replace_alu$656 creating $alu cell for $techmap$mul$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:168$42.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$620: $auto$alumacc.cc:512:replace_alu$667 creating $alu cell for $techmap$mul$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:168$42.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$620: $auto$alumacc.cc:512:replace_alu$670 creating $alu cell for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:151$6: $auto$alumacc.cc:512:replace_alu$673 creating $alu cell for $techmap$mul$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:168$42.$add$/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$609: $auto$alumacc.cc:512:replace_alu$676 creating $alu cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:211$49: $auto$alumacc.cc:512:replace_alu$679 creating $alu cell for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:153$8: $auto$alumacc.cc:512:replace_alu$682 created 9 $alu and 2 $macc cells. 3.25. Executing OPT pass (performing simple optimizations). 3.25.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.25.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 6 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 122 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 0 cells. 3.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_div_e8_m35_balanced_p3.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \FpxxDiv.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_div_e8_m35_balanced_p3. Optimizing cells in module \FpxxDiv. Performed a total of 0 changes. 3.25.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 6 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 122 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Computing hashes of 121 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 1 cells. 3.25.6. Executing OPT_DFF pass (perform DFF optimizations). 3.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. Removed 3 unused cells and 96 unused wires. 3.25.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.25.9. Rerunning OPT passes. (Maybe there is more to do..) 3.25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_div_e8_m35_balanced_p3.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \FpxxDiv.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_div_e8_m35_balanced_p3. Optimizing cells in module \FpxxDiv. Performed a total of 0 changes. 3.25.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 6 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 117 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 0 cells. 3.25.13. Executing OPT_DFF pass (perform DFF optimizations). 3.25.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. 3.25.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.25.16. Finished fast OPT passes. (There is nothing left to do.) 3.26. Executing MEMORY pass. 3.26.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 3.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 3.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 3.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 3.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\div_table'[0] in module `\FpxxDiv': merging output FF to cell. 3.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. Removed 1 unused cells and 17 unused wires. 3.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 3.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 3.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. 3.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). 3.27. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. 3.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). mapping memory FpxxDiv.div_table via $__DP16KD_ 3.29. Executing TECHMAP pass (map to technology primitives). 3.29.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 3.29.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v' to AST representation. Generating RTLIL representation for module `$__DP16KD_'. Generating RTLIL representation for module `$__PDPW16KD_'. Successfully finished Verilog frontend. 3.29.3. Continuing TECHMAP pass. Using template $paramod$e2d84f878d2523e5416ecd2f7c4da0a259fb5c15$__DP16KD_ for cells of type $__DP16KD_. No more expansions possible. 3.30. Executing OPT pass (performing simple optimizations). 3.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 6 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 122 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 0 cells. 3.30.3. Executing OPT_DFF pass (perform DFF optimizations). 3.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. Removed 8 unused cells and 31 unused wires. 3.30.5. Finished fast OPT passes. 3.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 3.32. Executing OPT pass (performing simple optimizations). 3.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 6 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 114 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 0 cells. 3.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_div_e8_m35_balanced_p3.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \FpxxDiv.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_div_e8_m35_balanced_p3. Optimizing cells in module \FpxxDiv. Consolidated identical input bits for $mux cell $procmux$456: Old ports: A={ 2'11 \when_FpxxDiv_l171 }, B=3'000, Y=$2\exp_delta_p5[2:0] New ports: A={ 1'1 \when_FpxxDiv_l171 }, B=2'00, Y=$2\exp_delta_p5[2:0] [1:0] New connections: $2\exp_delta_p5[2:0] [2] = $2\exp_delta_p5[2:0] [1] Optimizing cells in module \FpxxDiv. Consolidated identical input bits for $mux cell $procmux$462: Old ports: A=$2\exp_delta_p5[2:0], B=3'001, Y=\exp_delta_p5 New ports: A=$2\exp_delta_p5[2:0] [1:0], B=2'01, Y=\exp_delta_p5 [1:0] New connections: \exp_delta_p5 [2] = \exp_delta_p5 [1] Optimizing cells in module \FpxxDiv. Performed a total of 2 changes. 3.32.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 6 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 114 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 0 cells. 3.32.6. Executing OPT_DFF pass (perform DFF optimizations). 3.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. 3.32.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.32.9. Rerunning OPT passes. (Maybe there is more to do..) 3.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_div_e8_m35_balanced_p3.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \FpxxDiv.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_div_e8_m35_balanced_p3. Optimizing cells in module \FpxxDiv. Performed a total of 0 changes. 3.32.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 6 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 114 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 0 cells. 3.32.13. Executing OPT_DFF pass (perform DFF optimizations). 3.32.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. 3.32.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.32.16. Finished fast OPT passes. (There is nothing left to do.) 3.33. Executing TECHMAP pass (map to technology primitives). 3.33.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 3.33.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. Generating RTLIL representation for module `\_80_ccu2c_alu'. Successfully finished Verilog frontend. 3.33.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $not. Using template $paramod$4ccbe221165818e15f326ddee3d1183c7924e12f\_80_ccu2c_alu for cells of type $alu. Using template $paramod$7c9861d7ae06b82b18e703735c441bd6c5963cb5\_80_ccu2c_alu for cells of type $alu. Using template $paramod$9fb24bf0faa43f804d3c379242188667e42c235c\_80_ccu2c_alu for cells of type $alu. Using template $paramod$95803b2f2a0a67ebc594f50cf9cd7d672cce8582\_80_ccu2c_alu for cells of type $alu. Using template $paramod$749b5ba8f307e8fd3d027813f010bff762b1370f\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $xor. Using template $paramod$0cf90cc92a8a726f7480da3c1dd521ff92701be4\_90_alu for cells of type $alu. Using template $paramod$befd47b1c77b68561d11d0cb61a0fae29b79f34c\_80_ccu2c_alu for cells of type $alu. Using extmapper maccmap for cells of type $macc_v2. add { $mul$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:172$43.genblk1.genblk1.genblk1.genblk1.genblk1.blk.last_partial 36'000000000000000000000000000000000000 } (56 bits, unsigned) add { $mul$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:172$43.genblk1.genblk1.genblk1.genblk1.genblk1.blk.partial[1] 18'000000000000000000 } (53 bits, unsigned) add $mul$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:172$43.genblk1.genblk1.genblk1.genblk1.genblk1.blk.partial[0] (35 bits, unsigned) add \exp_p1 (9 bits, signed) sub { 1'0 \recip_exp_p1 } (3 bits, signed) add 10'0010000000 (10 bits, unsigned) Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $sdffce. Using template $paramod$constmap:113aec186e85299253e31dfd5283996a0cbb7dd1$paramod$308a992180060b4dcb3f2a49d25eb2a1924bb87b\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $logic_or. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $adff. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000001010 for cells of type $fa. Using template $paramod$484d51534650924b7ed4c69e46eed3a56904771f\_80_ccu2c_alu for cells of type $alu. Using template $paramod$7bd4281b5f3a80256512f7bfc730d1882f38423f\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $dff. No more expansions possible. 3.34. Executing OPT pass (performing simple optimizations). 3.34.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.34.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 135 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 1642 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Computing hashes of 1593 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Computing hashes of 1573 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Computing hashes of 1565 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Computing hashes of 1561 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Computing hashes of 1559 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Computing hashes of 1557 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Computing hashes of 1555 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 87 cells. 3.34.3. Executing OPT_DFF pass (perform DFF optimizations). 3.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. Removed 605 unused cells and 802 unused wires. 3.34.5. Finished fast OPT passes. 3.35. Executing ABC pass (technology mapping using ABC). 3.35.1. Summary of detected clock domains: 3 cells in clk=\clk, en={ }, arst={ }, srst=\rst 132 cells in clk=\clk, en={ }, arst={ }, srst={ } 3.35.2. Extracting gate netlist of module `\top_tommath_div_e8_m35_balanced_p3' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by \rst 3.35.3. Extracting gate netlist of module `\top_tommath_div_e8_m35_balanced_p3' to `/input.blif'.. Found matching posedge clock domain: \clk 3.35.3.1. Executed ABC. Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 2 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.3.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 4 ABC RESULTS: DFF cells: 2 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 2 ABC RESULTS: output signals: 2 Removing temp directory. 3.35.3.1. Executed ABC. Extracted 132 gates and 264 wires to a netlist network with 132 inputs and 132 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 132 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.3.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 264 ABC RESULTS: DFF cells: 132 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 132 ABC RESULTS: output signals: 132 Removing temp directory. 3.35.4. Summary of detected clock domains: 6 cells in clk=\clk, en={ }, arst=\reset, srst={ } 253 cells in clk=\clk, en=\p5_vld, arst={ }, srst={ } 112 cells in clk=\clk, en=\p1_vld, arst={ }, srst={ } 19 cells in clk=\clk, en=\io_op_vld, arst={ }, srst=$eq$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:161$37_Y 227 cells in clk=\clk, en=\io_op_vld, arst={ }, srst={ } 129 cells in clk=\clk, en=\p4_vld, arst={ }, srst={ } 132 cells in clk=\clk, en=\p2_vld, arst={ }, srst={ } 72 cells in clk=\clk, en=\p3_vld, arst={ }, srst={ } 3.35.5. Extracting gate netlist of module `\FpxxDiv' to `/input.blif'.. Found matching posedge clock domain: \clk, asynchronously reset by \reset 3.35.6. Extracting gate netlist of module `\FpxxDiv' to `/input.blif'.. Found matching posedge clock domain: \clk, enabled by \p5_vld 3.35.7. Extracting gate netlist of module `\FpxxDiv' to `/input.blif'.. Found matching posedge clock domain: \clk, enabled by \p1_vld 3.35.8. Extracting gate netlist of module `\FpxxDiv' to `/input.blif'.. Found matching posedge clock domain: \clk, enabled by \io_op_vld, synchronously reset by $eq$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/src/tommath_div_e8_m35_balanced_p3.v:161$37_Y 3.35.9. Extracting gate netlist of module `\FpxxDiv' to `/input.blif'.. Found matching posedge clock domain: \clk, enabled by \io_op_vld 3.35.10. Extracting gate netlist of module `\FpxxDiv' to `/input.blif'.. Found matching posedge clock domain: \clk, enabled by \p4_vld 3.35.11. Extracting gate netlist of module `\FpxxDiv' to `/input.blif'.. Found matching posedge clock domain: \clk, enabled by \p2_vld 3.35.12. Extracting gate netlist of module `\FpxxDiv' to `/input.blif'.. Found matching posedge clock domain: \clk, enabled by \p3_vld 3.35.12.1. Executed ABC. Extracted 6 gates and 7 wires to a netlist network with 1 inputs and 6 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.12.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 12 ABC RESULTS: DFF cells: 6 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 1 ABC RESULTS: output signals: 6 Removing temp directory. 3.35.12.1. Executed ABC. Extracted 248 gates and 302 wires to a netlist network with 52 inputs and 44 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 49 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.12.2. Re-integrating ABC results. ABC RESULTS: AND cells: 48 ABC RESULTS: ANDNOT cells: 3 ABC RESULTS: BUF cells: 11 ABC RESULTS: DFF cells: 49 ABC RESULTS: MUX cells: 35 ABC RESULTS: NAND cells: 14 ABC RESULTS: NOR cells: 8 ABC RESULTS: OR cells: 2 ABC RESULTS: ORNOT cells: 1 ABC RESULTS: internal signals: 206 ABC RESULTS: input signals: 52 ABC RESULTS: output signals: 44 Removing temp directory. 3.35.12.1. Executed ABC. Extracted 102 gates and 205 wires to a netlist network with 103 inputs and 102 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 101 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.12.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 202 ABC RESULTS: DFF cells: 101 ABC RESULTS: OR cells: 1 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 103 ABC RESULTS: output signals: 102 Removing temp directory. 3.35.12.1. Executed ABC. Extracted 15 gates and 25 wires to a netlist network with 10 inputs and 5 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: Abc_NtkRetimeInitialValues(): The problem is unsatisfiable. DC latch values are used. ABC: + strash ABC: + &get -n ABC: Warning: 1 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.12.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: ANDNOT cells: 1 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 1 ABC RESULTS: NOR cells: 4 ABC RESULTS: NOT cells: 1 ABC RESULTS: XNOR cells: 1 ABC RESULTS: internal signals: 10 ABC RESULTS: input signals: 10 ABC RESULTS: output signals: 5 Removing temp directory. 3.35.12.1. Executed ABC. Extracted 204 gates and 338 wires to a netlist network with 134 inputs and 91 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 84 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.12.2. Re-integrating ABC results. ABC RESULTS: AND cells: 51 ABC RESULTS: ANDNOT cells: 3 ABC RESULTS: BUF cells: 163 ABC RESULTS: DFF cells: 90 ABC RESULTS: NAND cells: 5 ABC RESULTS: NOR cells: 42 ABC RESULTS: NOT cells: 6 ABC RESULTS: XOR cells: 2 ABC RESULTS: internal signals: 113 ABC RESULTS: input signals: 134 ABC RESULTS: output signals: 91 Removing temp directory. 3.35.12.1. Executed ABC. Extracted 101 gates and 156 wires to a netlist network with 53 inputs and 54 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 53 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.12.2. Re-integrating ABC results. ABC RESULTS: AND cells: 1 ABC RESULTS: ANDNOT cells: 1 ABC RESULTS: BUF cells: 67 ABC RESULTS: DFF cells: 55 ABC RESULTS: MUX cells: 35 ABC RESULTS: NAND cells: 1 ABC RESULTS: NOR cells: 1 ABC RESULTS: NOT cells: 2 ABC RESULTS: OR cells: 1 ABC RESULTS: ORNOT cells: 3 ABC RESULTS: internal signals: 49 ABC RESULTS: input signals: 53 ABC RESULTS: output signals: 54 Removing temp directory. 3.35.12.1. Executed ABC. Extracted 69 gates and 138 wires to a netlist network with 69 inputs and 69 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 69 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.12.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 138 ABC RESULTS: DFF cells: 69 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 69 ABC RESULTS: output signals: 69 Removing temp directory. 3.35.12.1. Executed ABC. Extracted 69 gates and 138 wires to a netlist network with 69 inputs and 69 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 10> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 69 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.12.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 138 ABC RESULTS: DFF cells: 69 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 69 ABC RESULTS: output signals: 69 Removing temp directory. Removing global temp directory. 3.36. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. Removed 0 unused cells and 2246 unused wires. 3.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 3.38. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_div_e8_m35_balanced_p3'. Computing hashes of 135 cells of `\top_tommath_div_e8_m35_balanced_p3'. Finding duplicate cells in `\top_tommath_div_e8_m35_balanced_p3'. Finding identical cells in module `\FpxxDiv'. Computing hashes of 852 cells of `\FpxxDiv'. Finding duplicate cells in `\FpxxDiv'. Removed a total of 0 cells. 3.39. Executing TECHMAP pass (map to technology primitives). 3.39.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 3.39.2. Continuing TECHMAP pass. Using template $_DFF_PP0_ for cells of type $_DFF_PP0_. Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. No more expansions possible. 3.40. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_div_e8_m35_balanced_p3. Optimizing module FpxxDiv. 3.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). 3.42. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in top_tommath_div_e8_m35_balanced_p3. Handling GSR in FpxxDiv. 3.43. Executing ATTRMVCP pass (move or copy attributes). 3.44. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_div_e8_m35_balanced_p3.. Finding unused cells or wires in module \FpxxDiv.. Removed 1 unused cells and 2739 unused wires. 3.45. Executing ABC pass (technology mapping using ABC). 3.45.1. Extracting gate netlist of module `\top_tommath_div_e8_m35_balanced_p3' to `/input.blif'.. 3.45.1.1. Executed ABC. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 3.45.2. Extracting gate netlist of module `\FpxxDiv' to `/input.blif'.. 3.45.2.1. Executed ABC. Extracted 275 gates and 484 wires to a netlist network with 209 inputs and 107 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.45.2.2. Re-integrating ABC results. ABC RESULTS: AND cells: 101 ABC RESULTS: ANDNOT cells: 9 ABC RESULTS: MUX cells: 69 ABC RESULTS: NAND cells: 23 ABC RESULTS: NOR cells: 54 ABC RESULTS: NOT cells: 6 ABC RESULTS: OR cells: 4 ABC RESULTS: ORNOT cells: 3 ABC RESULTS: XNOR cells: 2 ABC RESULTS: XOR cells: 1 ABC RESULTS: internal signals: 168 ABC RESULTS: input signals: 209 ABC RESULTS: output signals: 107 Removing temp directory. Removing global temp directory. 3.46. Executing TECHMAP pass (map to technology primitives). 3.46.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v' to AST representation. Generating RTLIL representation for module `$_DLATCH_N_'. Generating RTLIL representation for module `$_DLATCH_P_'. Successfully finished Verilog frontend. 3.46.2. Continuing TECHMAP pass. No more expansions possible. 3.47. Executing ABC pass (technology mapping using ABC). 3.47.1. Summary of detected clock domains: 135 cells in clk={ }, en={ }, arst={ }, srst={ } 3.47.2. Extracting gate netlist of module `\top_tommath_div_e8_m35_balanced_p3' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 3.47.2.1. Executed ABC. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 3.47.3. Summary of detected clock domains: 848 cells in clk={ }, en={ }, arst={ }, srst={ } 3.47.4. Extracting gate netlist of module `\FpxxDiv' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 3.47.4.1. Executed ABC. Extracted 272 gates and 481 wires to a netlist network with 209 inputs and 107 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_lut /lutdefs.txt ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + dress /input.blif ABC: Total number of equiv classes = 160. ABC: Participating nodes from both networks = 318. ABC: Participating nodes from the first network = 159. ( 92.44 % of nodes) ABC: Participating nodes from the second network = 159. ( 92.44 % of nodes) ABC: Node pairs (any polarity) = 159. ( 92.44 % of names can be moved) ABC: Node pairs (same polarity) = 124. ( 72.09 % of names can be moved) ABC: Total runtime = 0.06 sec ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.47.4.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 171 ABC RESULTS: internal signals: 165 ABC RESULTS: input signals: 209 ABC RESULTS: output signals: 107 Removing temp directory. Removing global temp directory. Removed 0 unused cells and 965 unused wires. 3.48. Executing TECHMAP pass (map to technology primitives). 3.48.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `$lut'. Successfully finished Verilog frontend. 3.48.2. Continuing TECHMAP pass. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775$lut for cells of type $lut. Using template $paramod$ef26adabe6060e01077b576cfe34e95e55a26aef$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$812d6fc36e110e5dddfe0998e45231ba0e361a1c$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut. Using template $paramod$45d617c2ce0041e27b541f62b0fc3c3ce441a616$lut for cells of type $lut. Using template $paramod$e5f53fb2cb3e702c9422ebddd3ba952e5a8f3401$lut for cells of type $lut. Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut. Using template $paramod$c9c145a3c6d085b43407e8d146c4cb593e0f20bb$lut for cells of type $lut. Using template $paramod$c24ed72ebb67e9ead6029e42e909ef7fc0abbb11$lut for cells of type $lut. No more expansions possible. 3.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in top_tommath_div_e8_m35_balanced_p3. Optimizing LUTs in FpxxDiv. Optimizing lut $abc$6910$auto$blifparse.cc:557:parse_blif$6959.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$6910$auto$blifparse.cc:557:parse_blif$6960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$6910$auto$blifparse.cc:557:parse_blif$6959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$6910$auto$blifparse.cc:557:parse_blif$6960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$6910$auto$blifparse.cc:557:parse_blif$6984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$6910$auto$blifparse.cc:557:parse_blif$7032.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$6910$auto$blifparse.cc:557:parse_blif$7037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$6910$auto$blifparse.cc:557:parse_blif$7045.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$6910$auto$blifparse.cc:557:parse_blif$7056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$6910$auto$blifparse.cc:557:parse_blif$7065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$6910$auto$blifparse.cc:557:parse_blif$7067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Removed 0 unused cells and 392 unused wires. 3.50. Executing AUTONAME pass. Renamed 134 objects in module top_tommath_div_e8_m35_balanced_p3 (4 iterations). Renamed 981 objects in module FpxxDiv (118 iterations). 3.51. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `top_tommath_div_e8_m35_balanced_p3'. Setting top module to top_tommath_div_e8_m35_balanced_p3. 3.51.1. Analyzing design hierarchy.. Top module: \top_tommath_div_e8_m35_balanced_p3 Used module: \FpxxDiv 3.51.2. Analyzing design hierarchy.. Top module: \top_tommath_div_e8_m35_balanced_p3 Used module: \FpxxDiv Removed 0 unused modules. 3.52. Printing statistics. === top_tommath_div_e8_m35_balanced_p3 === +----------Local Count, excluding submodules. | 17 wires 359 wire bits 17 public wires 359 public wire bits 7 ports 136 port bits 135 submodules 1 FpxxDiv 134 TRELLIS_FF === FpxxDiv === +----------Local Count, excluding submodules. | 311 wires 2665 wire bits 311 public wires 2665 public wire bits 13 ports 136 port bits 8 cells 1 DP16KD 7 MULT18X18D 757 submodules 128 CCU2C 180 LUT4 9 PFUMX 440 TRELLIS_FF === design hierarchy === +----------Count including submodules. | 8 top_tommath_div_e8_m35_balanced_p3 8 FpxxDiv +----------Count including submodules. | 328 wires 3024 wire bits 328 public wires 3024 public wire bits 20 ports 272 port bits - memories - memory bits - processes 8 cells 1 DP16KD 7 MULT18X18D 135 submodules 1 FpxxDiv 134 TRELLIS_FF 3.53. Executing CHECK pass (checking for obvious problems). Checking module top_tommath_div_e8_m35_balanced_p3... Checking module FpxxDiv... Found and reported 0 problems. 3.54. Executing JSON backend. End of script. Logfile hash: 4da6c45a91, time: 1.36s, user: 0.91s, system: 0.06s, MEM: 54.07 MB peak Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3) Time spent: 46% 3x abc (0 sec), 16% 17x read_verilog (0 sec), ... $ yosys -s /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_div_e8_m35_balanced_p3/yosys.ys [exit code 0]