/----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3) -- Executing script file `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/flopoco_add_we8_wf35_zynq7000_native_single_f300/yosys.ys' -- 1. Executing GHDL. Importing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Importing module flopoco_add_we8_wf35_zynq7000_native_single_f300_Barch. Importing module rightshiftersticky36_by_max_38_freq300_uid4_Barch. Importing module intadder_39_freq300_uid6_Barch. Importing module normalizer_z_40_40_40_freq300_uid8_Barch. Importing module intadder_46_freq300_uid11_Barch. 2. Executing SYNTH_LATTICE pass. 2.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\VLO'. Generating RTLIL representation for module `\VHI'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\DP16KD'. Replacing existing blackbox module `\FD1P3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:2.1-2.261. Generating RTLIL representation for module `\FD1P3AX'. Replacing existing blackbox module `\FD1P3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:3.1-3.261. Generating RTLIL representation for module `\FD1P3AY'. Replacing existing blackbox module `\FD1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:4.1-4.261. Generating RTLIL representation for module `\FD1P3BX'. Replacing existing blackbox module `\FD1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:5.1-5.261. Generating RTLIL representation for module `\FD1P3DX'. Replacing existing blackbox module `\FD1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:6.1-6.261. Generating RTLIL representation for module `\FD1P3IX'. Replacing existing blackbox module `\FD1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:7.1-7.261. Generating RTLIL representation for module `\FD1P3JX'. Replacing existing blackbox module `\FD1S3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:8.1-8.261. Generating RTLIL representation for module `\FD1S3AX'. Replacing existing blackbox module `\FD1S3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:9.1-9.261. Generating RTLIL representation for module `\FD1S3AY'. Replacing existing blackbox module `\FD1S3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:10.1-10.261. Generating RTLIL representation for module `\FD1S3BX'. Replacing existing blackbox module `\FD1S3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:11.1-11.261. Generating RTLIL representation for module `\FD1S3DX'. Replacing existing blackbox module `\FD1S3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:12.1-12.261. Generating RTLIL representation for module `\FD1S3IX'. Replacing existing blackbox module `\FD1S3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:13.1-13.261. Generating RTLIL representation for module `\FD1S3JX'. Replacing existing blackbox module `\IFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:26.1-26.301. Generating RTLIL representation for module `\IFS1P3BX'. Replacing existing blackbox module `\IFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:27.1-27.301. Generating RTLIL representation for module `\IFS1P3DX'. Replacing existing blackbox module `\IFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:28.1-28.301. Generating RTLIL representation for module `\IFS1P3IX'. Replacing existing blackbox module `\IFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:29.1-29.301. Generating RTLIL representation for module `\IFS1P3JX'. Replacing existing blackbox module `\OFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:31.1-31.302. Generating RTLIL representation for module `\OFS1P3BX'. Replacing existing blackbox module `\OFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:32.1-32.302. Generating RTLIL representation for module `\OFS1P3DX'. Replacing existing blackbox module `\OFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:33.1-33.302. Generating RTLIL representation for module `\OFS1P3IX'. Replacing existing blackbox module `\OFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:34.1-34.302. Generating RTLIL representation for module `\OFS1P3JX'. Replacing existing blackbox module `\IB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:2.1-2.157. Generating RTLIL representation for module `\IB'. Replacing existing blackbox module `\IBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:3.1-3.157. Generating RTLIL representation for module `\IBPU'. Replacing existing blackbox module `\IBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:4.1-4.157. Generating RTLIL representation for module `\IBPD'. Replacing existing blackbox module `\OB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:5.1-5.157. Generating RTLIL representation for module `\OB'. Replacing existing blackbox module `\OBZ' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:6.1-6.164. Generating RTLIL representation for module `\OBZ'. Replacing existing blackbox module `\OBZPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:7.1-7.164. Generating RTLIL representation for module `\OBZPU'. Replacing existing blackbox module `\OBZPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:8.1-8.164. Generating RTLIL representation for module `\OBZPD'. Replacing existing blackbox module `\OBCO' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:9.1-9.90. Generating RTLIL representation for module `\OBCO'. Replacing existing blackbox module `\BB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:10.1-10.179. Generating RTLIL representation for module `\BB'. Replacing existing blackbox module `\BBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:11.1-11.179. Generating RTLIL representation for module `\BBPU'. Replacing existing blackbox module `\BBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:12.1-12.179. Generating RTLIL representation for module `\BBPD'. Replacing existing blackbox module `\ILVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:13.1-13.139. Generating RTLIL representation for module `\ILVDS'. Replacing existing blackbox module `\OLVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:14.1-14.146. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 2.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DCUA'. Successfully finished Verilog frontend. 2.3. Executing HIERARCHY pass (managing design hierarchy). 2.3.1. Analyzing design hierarchy.. Top module: \top_flopoco_add_we8_wf35_zynq7000_native_single_f300 Used module: \flopoco_add_we8_wf35_zynq7000_native_single_f300_Barch Used module: \intadder_46_freq300_uid11_Barch Used module: \normalizer_z_40_40_40_freq300_uid8_Barch Used module: \intadder_39_freq300_uid6_Barch Used module: \rightshiftersticky36_by_max_38_freq300_uid4_Barch 2.3.2. Analyzing design hierarchy.. Top module: \top_flopoco_add_we8_wf35_zynq7000_native_single_f300 Used module: \flopoco_add_we8_wf35_zynq7000_native_single_f300_Barch Used module: \intadder_46_freq300_uid11_Barch Used module: \normalizer_z_40_40_40_freq300_uid8_Barch Used module: \intadder_39_freq300_uid6_Barch Used module: \rightshiftersticky36_by_max_38_freq300_uid4_Barch Removed 0 unused modules. 2.4. Executing PROC pass (convert processes to netlists). 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 2.4.4. Executing PROC_INIT pass (extract init attributes). 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module intadder_46_freq300_uid11_Barch. Optimizing module normalizer_z_40_40_40_freq300_uid8_Barch. Optimizing module intadder_39_freq300_uid6_Barch. Optimizing module rightshiftersticky36_by_max_38_freq300_uid4_Barch. Optimizing module flopoco_add_we8_wf35_zynq7000_native_single_f300_Barch. Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.5. Executing CHECK pass (checking for obvious problems). Checking module intadder_46_freq300_uid11_Barch... Checking module normalizer_z_40_40_40_freq300_uid8_Barch... Checking module intadder_39_freq300_uid6_Barch... Checking module rightshiftersticky36_by_max_38_freq300_uid4_Barch... Checking module flopoco_add_we8_wf35_zynq7000_native_single_f300_Barch... Checking module top_flopoco_add_we8_wf35_zynq7000_native_single_f300... Found and reported 0 problems. 2.6. Executing FLATTEN pass (flatten design). Deleting now unused module intadder_46_freq300_uid11_Barch. Deleting now unused module normalizer_z_40_40_40_freq300_uid8_Barch. Deleting now unused module intadder_39_freq300_uid6_Barch. Deleting now unused module rightshiftersticky36_by_max_38_freq300_uid4_Barch. Deleting now unused module flopoco_add_we8_wf35_zynq7000_native_single_f300_Barch. 2.7. Executing TRIBUF pass. 2.8. Executing DEMINOUT pass (demote inout ports to input or output). 2.9. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.10. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Removed 16 unused cells and 147 unused wires. 2.11. Executing CHECK pass (checking for obvious problems). Checking module top_flopoco_add_we8_wf35_zynq7000_native_single_f300... Found and reported 0 problems. 2.12. Executing OPT pass (performing simple optimizations). 2.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 255 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 253 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 2 cells. 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell u_dut.lzcandshifter.:587: \u_dut.lzcandshifter.level1 -> { 1'1 \u_dut.lzcandshifter.level1 [38:0] } Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Performed a total of 0 changes. 2.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 253 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.12.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 38 on u_dut.:368 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 0 on u_dut.fracadder.:506 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 1 on u_dut.fracadder.:506 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 1-bit at position 37 on u_dut.fracadder.:506 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 38 on u_dut.fracadder.:506 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 0 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 1 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 2 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 3 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 4 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 5 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 6 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 7 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 8 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 9 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 10 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 11 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 12 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 13 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 14 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 15 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 16 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 17 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 18 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 19 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 20 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 21 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 22 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 23 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 24 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 25 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 26 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 27 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 28 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 29 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 30 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 31 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 32 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 33 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 34 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 35 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 36 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 37 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 38 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 39 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 40 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 41 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 42 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 43 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 44 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 45 on u_dut.roundingadder.:621 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Removed 0 unused cells and 2 unused wires. 2.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.12.9. Rerunning OPT passes. (Maybe there is more to do..) 2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Performed a total of 0 changes. 2.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 252 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.12.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.fracadder.:507 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 1 on u_dut.fracadder.:507 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 1-bit at position 37 on u_dut.fracadder.:507 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 38 on u_dut.fracadder.:507 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 0 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 1 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 2 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 3 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 4 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 5 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 6 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 7 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 8 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 9 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 10 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 11 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 12 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 13 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 14 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 15 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 16 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 17 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 18 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 19 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 20 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 21 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 22 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 23 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 24 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 25 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 26 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 27 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 28 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 29 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 30 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 31 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 32 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 33 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 34 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 35 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 36 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 37 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 38 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 39 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 40 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 41 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 42 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 43 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 44 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 45 on u_dut.roundingadder.:622 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. 2.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.12.16. Rerunning OPT passes. (Maybe there is more to do..) 2.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Performed a total of 0 changes. 2.12.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 251 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.12.20. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.fracadder.:508 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 1 on u_dut.fracadder.:508 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 1-bit at position 37 on u_dut.fracadder.:508 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 38 on u_dut.fracadder.:508 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 0 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 1 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 2 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 3 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 4 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 5 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 6 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 7 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 8 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 9 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 10 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 11 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 12 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 13 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 14 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 15 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 16 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 17 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 18 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 19 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 20 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 21 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 22 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 23 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 24 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 25 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 26 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 27 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 28 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 29 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 30 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 31 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 32 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 33 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 34 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 35 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 36 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 37 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 38 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 39 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 40 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 41 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 42 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 43 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 44 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 45 on u_dut.roundingadder.:623 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. 2.12.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.12.23. Rerunning OPT passes. (Maybe there is more to do..) 2.12.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Performed a total of 0 changes. 2.12.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 250 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.12.27. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 1 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 2 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 3 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 4 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 5 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 6 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 7 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 8 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 9 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 10 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 11 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 12 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 13 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 14 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 15 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 16 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 17 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 18 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 19 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 20 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 21 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 22 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 23 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 24 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 25 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 26 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 27 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 28 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 29 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 30 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 31 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 32 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 33 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 34 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 35 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 36 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 37 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 38 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 39 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 40 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 41 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 42 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 43 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 44 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 45 on u_dut.roundingadder.:624 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.12.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. 2.12.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.12.30. Rerunning OPT passes. (Maybe there is more to do..) 2.12.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Performed a total of 0 changes. 2.12.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 249 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.12.34. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 1 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 2 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 3 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 4 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 5 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 6 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 7 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 8 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 9 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 10 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 11 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 12 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 13 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 14 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 15 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 16 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 17 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 18 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 19 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 20 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 21 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 22 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 23 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 24 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 25 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 26 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 27 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 28 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 29 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 30 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 31 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 32 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 33 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 34 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 35 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 36 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 37 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 38 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 39 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 40 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 41 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 42 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 43 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 44 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 45 on u_dut.roundingadder.:625 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.12.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. 2.12.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.12.37. Rerunning OPT passes. (Maybe there is more to do..) 2.12.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Performed a total of 0 changes. 2.12.40. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 248 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.12.41. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 1 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 2 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 3 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 4 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 5 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 6 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 7 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 8 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 9 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 10 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 11 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 12 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 13 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 14 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 15 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 16 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 17 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 18 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 19 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 20 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 21 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 22 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 23 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 24 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 25 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 26 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 27 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 28 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 29 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 30 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 31 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 32 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 33 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 34 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 35 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 36 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 37 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 38 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 39 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 40 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 41 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 42 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 43 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 44 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 45 on u_dut.roundingadder.:626 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.12.42. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. 2.12.43. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.12.44. Rerunning OPT passes. (Maybe there is more to do..) 2.12.45. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.46. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Performed a total of 0 changes. 2.12.47. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 247 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.12.48. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 1 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 2 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 3 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 4 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 5 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 6 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 7 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 8 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 9 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 10 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 11 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 12 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 13 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 14 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 15 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 16 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 17 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 18 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 19 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 20 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 21 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 22 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 23 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 24 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 25 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 26 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 27 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 28 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 29 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 30 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 31 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 32 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 33 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 34 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 35 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 36 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 37 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 38 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 39 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 40 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 41 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 42 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 43 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 44 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Setting constant 0-bit at position 45 on u_dut.roundingadder.:627 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.12.49. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. 2.12.50. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.12.51. Rerunning OPT passes. (Maybe there is more to do..) 2.12.52. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.53. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Performed a total of 0 changes. 2.12.54. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 246 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.12.55. Executing OPT_DFF pass (perform DFF optimizations). 2.12.56. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Removed 0 unused cells and 1 unused wires. 2.12.57. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.12.58. Rerunning OPT passes. (Maybe there is more to do..) 2.12.59. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.12.60. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Performed a total of 0 changes. 2.12.61. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 245 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.12.62. Executing OPT_DFF pass (perform DFF optimizations). 2.12.63. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. 2.12.64. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.12.65. Finished fast OPT passes. (There is nothing left to do.) 2.13. Executing FSM pass (extract and optimize FSM). 2.13.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.excrt_d1 as FSM state register: Users of register don't seem to benefit from recoding. 2.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. 2.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2.14. Executing OPT pass (performing simple optimizations). 2.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 245 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Performed a total of 0 changes. 2.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 245 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.14.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on :11 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300 (D = \u_dut.excrt2, Q = \R_o [45:44], rval = 2'00). Adding SRST signal on u_dut.lzcandshifter.:604 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300 (D = \u_dut.lzcandshifter.level3 [3:0], Q = \u_dut.lzcandshifter.level2_d1 [3:0], rval = 4'0000). Adding SRST signal on u_dut.lzcandshifter.:601 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300 (D = \u_dut.lzcandshifter.level5 [15:0], Q = \u_dut.lzcandshifter.level4_d1 [15:0], rval = 16'0000000000000000). Adding SRST signal on $auto$ff.cc:337:slice$506 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300 (D = \u_dut.rightshiftercomponent.level1 [37], Q = \u_dut.fracypad_d1 [37], rval = 1'0). Adding SRST signal on u_dut.:383 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300 (D = \u_dut.signr_d5, Q = \u_dut.signr2_d1, rval = 1'0). Adding SRST signal on u_dut.:371 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300 (D = \u_dut.lzcandshifter.level1 [38], Q = \u_dut.shiftedfrac_d1 [39], rval = 1'1). Adding SRST signal on u_dut.:362 ($dff) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300 (D = \u_dut.signx_d1, Q = \u_dut.signr_d1, rval = 1'0). 2.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Removed 4 unused cells and 2 unused wires. 2.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.14.9. Rerunning OPT passes. (Maybe there is more to do..) 2.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Performed a total of 0 changes. 2.14.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 246 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.14.13. Executing OPT_DFF pass (perform DFF optimizations). 2.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. 2.14.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.14.16. Finished fast OPT passes. (There is nothing left to do.) 2.15. Executing WREDUCE pass (reducing word size of cells). Removed top 45 bits (of 46) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.roundingadder.:620 ($add). Removed top 1 bits (of 40) from mux cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.lzcandshifter.:587 ($mux). Removed top 38 bits (of 39) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.fracadder.:505 ($add). Removed top 37 bits (of 38) from FF cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.rightshiftercomponent.:493 ($dff). Removed top 1 bits (of 38) from mux cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.rightshiftercomponent.:484 ($mux). Removed top 2 bits (of 6) from FF cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.rightshiftercomponent.:488 ($dff). Removed top 30 bits (of 38) from FF cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.rightshiftercomponent.:490 ($dff). Removed top 34 bits (of 38) from FF cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.rightshiftercomponent.:491 ($dff). Removed top 36 bits (of 38) from FF cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.rightshiftercomponent.:492 ($dff). Removed top 38 bits (of 39) from FF cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:369 ($dff). Removed top 11 bits (of 46) from FF cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:342 ($dff). Removed top 1 bits (of 4) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:323 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:314 ($eq). Removed top 2 bits (of 4) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:312 ($eq). Removed top 3 bits (of 4) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:309 ($eq). Removed top 1 bits (of 4) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:293 ($eq). Removed top 1 bits (of 10) from port A of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:258 ($sub). Removed top 4 bits (of 10) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:258 ($sub). Removed top 1 bits (of 9) from port A of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:253 ($add). Removed top 8 bits (of 9) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:253 ($add). Removed top 1 bits (of 39) from port A of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.fracadder.:503 ($add). Removed top 1 bits (of 39) from port A of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:231 ($xor). Removed top 24 bits (of 32) from port A of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:215 ($gt). Removed top 26 bits (of 32) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:215 ($gt). Removed top 1 bits (of 6) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:209 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:194 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:191 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:182 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:179 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:170 ($eq). Removed top 4 bits (of 6) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:167 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:158 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:155 ($eq). Removed top 2 bits (of 6) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:152 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:140 ($eq). Removed top 5 bits (of 6) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:137 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:128 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:125 ($eq). Removed top 1 bits (of 6) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:116 ($eq). Removed top 3 bits (of 6) from port B of cell top_flopoco_add_we8_wf35_zynq7000_native_single_f300.u_dut.:114 ($eq). Removed top 2 bits (of 46) from wire top_flopoco_add_we8_wf35_zynq7000_native_single_f300.r_dut. 2.16. Executing PEEPOPT pass (run peephole optimizers). 2.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Removed 0 unused cells and 1 unused wires. 2.18. Executing SHARE pass (SAT-based resource sharing). 2.19. Executing TECHMAP pass (map to technology primitives). 2.19.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 2.19.2. Continuing TECHMAP pass. No more expansions possible. 2.20. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. 2.22. Executing TECHMAP pass (map to technology primitives). 2.22.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 2.22.2. Continuing TECHMAP pass. No more expansions possible. 2.23. Executing TECHMAP pass (map to technology primitives). 2.23.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. Generating RTLIL representation for module `$__MUL18X18'. Successfully finished Verilog frontend. 2.23.2. Continuing TECHMAP pass. No more expansions possible. 2.24. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top_flopoco_add_we8_wf35_zynq7000_native_single_f300: creating $macc model for u_dut.fracadder.:503 ($add). creating $macc model for u_dut.:253 ($add). creating $macc model for u_dut.:258 ($sub). creating $macc model for u_dut.fracadder.:505 ($add). creating $macc model for u_dut.:76 ($sub). creating $macc model for u_dut.:73 ($sub). creating $macc model for u_dut.roundingadder.:620 ($add). merging $macc model for u_dut.fracadder.:503 into u_dut.fracadder.:505. creating $alu model for $macc u_dut.:73. creating $alu model for $macc u_dut.:76. creating $alu model for $macc u_dut.fracadder.:505. creating $alu model for $macc u_dut.:258. creating $alu model for $macc u_dut.:253. creating $alu model for $macc u_dut.roundingadder.:620. creating $alu model for u_dut.:215 ($gt): new $alu creating $alu model for u_dut.:68 ($lt): new $alu creating $alu cell for u_dut.:68: $auto$alumacc.cc:512:replace_alu$526 creating $alu cell for u_dut.:215: $auto$alumacc.cc:512:replace_alu$531 creating $alu cell for u_dut.roundingadder.:620: $auto$alumacc.cc:512:replace_alu$542 creating $alu cell for u_dut.:253: $auto$alumacc.cc:512:replace_alu$545 creating $alu cell for u_dut.:258: $auto$alumacc.cc:512:replace_alu$548 creating $alu cell for u_dut.fracadder.:505: $auto$alumacc.cc:512:replace_alu$551 creating $alu cell for u_dut.:76: $auto$alumacc.cc:512:replace_alu$554 creating $alu cell for u_dut.:73: $auto$alumacc.cc:512:replace_alu$557 created 8 $alu and 0 $macc cells. 2.25. Executing OPT pass (performing simple optimizations). 2.25.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.25.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 251 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 250 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 1 cells. 2.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux \u_dut.:216. dead port 2/2 on $mux \u_dut.:216. dead port 1/2 on $mux \u_dut.:69. dead port 2/2 on $mux \u_dut.:69. Removed 4 multiplexer ports. 2.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Performed a total of 0 changes. 2.25.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 248 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.25.6. Executing OPT_DFF pass (perform DFF optimizations). 2.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Removed 3 unused cells and 7 unused wires. 2.25.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.25.9. Rerunning OPT passes. (Maybe there is more to do..) 2.25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Performed a total of 0 changes. 2.25.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 245 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.25.13. Executing OPT_DFF pass (perform DFF optimizations). 2.25.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. 2.25.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.25.16. Finished fast OPT passes. (There is nothing left to do.) 2.26. Executing MEMORY pass. 2.26.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 2.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 2.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 2.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 2.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 2.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. 2.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 2.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. 2.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2.27. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. 2.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). 2.29. Executing TECHMAP pass (map to technology primitives). 2.29.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 2.29.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v' to AST representation. Generating RTLIL representation for module `$__DP16KD_'. Generating RTLIL representation for module `$__PDPW16KD_'. Successfully finished Verilog frontend. 2.29.3. Continuing TECHMAP pass. No more expansions possible. 2.30. Executing OPT pass (performing simple optimizations). 2.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 232 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.30.3. Executing OPT_DFF pass (perform DFF optimizations). 2.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Removed 0 unused cells and 15 unused wires. 2.30.5. Finished fast OPT passes. 2.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 2.32. Executing OPT pass (performing simple optimizations). 2.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 232 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 2.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Performed a total of 0 changes. 2.32.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 232 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.32.6. Executing OPT_DFF pass (perform DFF optimizations). 2.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. 2.32.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.32.9. Finished fast OPT passes. (There is nothing left to do.) 2.33. Executing TECHMAP pass (map to technology primitives). 2.33.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 2.33.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. Generating RTLIL representation for module `\_80_ccu2c_alu'. Successfully finished Verilog frontend. 2.33.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $xor. Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\_80_ccu2c_alu for cells of type $alu. Using template $paramod$e4a1a075d8a4b86b4c532039fe17946751cd4a04\_80_ccu2c_alu for cells of type $alu. Using template $paramod$80d142c50200b0523574d48282c1414be7bb2660\_80_ccu2c_alu for cells of type $alu. Using template $paramod$a2af9b43308e3114c3b5dd3f4dc3329b2387395d\_80_ccu2c_alu for cells of type $alu. Using template $paramod$6aa5654f48c0d9997ace349db693b1718ed26b43\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $not. Using template $paramod$2ab0ff81670440372478bad90d3da37d43208ad1\_80_ccu2c_alu for cells of type $alu. Using template $paramod$b1f9526e0098bf1f451eff1f929263555cabc805\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $pmux. Using extmapper simplemap for cells of type $logic_or. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $pos. No more expansions possible. 2.34. Executing OPT pass (performing simple optimizations). 2.34.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.34.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 2520 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 2380 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 2292 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 2270 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 250 cells. 2.34.3. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:337:slice$2384 ($_DFF_P_) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300 (D = $auto$simplemap.cc:189:logic_reduce$2823, Q = \u_dut.excrt_d1 [1], rval = 1'1). Adding SRST signal on $auto$ff.cc:337:slice$2383 ($_DFF_P_) from module top_flopoco_add_we8_wf35_zynq7000_native_single_f300 (D = $auto$simplemap.cc:189:logic_reduce$2812, Q = \u_dut.excrt_d1 [0], rval = 1'1). 2.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Removed 519 unused cells and 790 unused wires. 2.34.5. Rerunning OPT passes. (Removed registers in this run.) 2.34.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.34.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 1751 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 0 cells. 2.34.8. Executing OPT_DFF pass (perform DFF optimizations). 2.34.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. 2.34.10. Finished fast OPT passes. 2.35. Executing ABC pass (technology mapping using ABC). 2.35.1. Summary of detected clock domains: 5 cells in clk={ }, en={ }, arst={ }, srst={ } 8 cells in clk=\clk, en={ }, arst={ }, srst=\u_dut.rightshiftercomponent.ps [0] 2 cells in clk=\clk, en={ }, arst={ }, srst=$flatten\u_dut.$auto$ghdl.cc:862:import_module$140 7 cells in clk=\clk, en={ }, arst={ }, srst=$flatten\u_dut.$auto$ghdl.cc:862:import_module$86 108 cells in clk=\clk, en={ }, arst={ }, srst=!$auto$simplemap.cc:189:logic_reduce$2802 51 cells in clk=\clk, en={ }, arst={ }, srst=\u_dut.lzcandshifter.count4 11 cells in clk=\clk, en={ }, arst={ }, srst=\u_dut.lzcandshifter.count2 42 cells in clk=\clk, en={ }, arst={ }, srst=$flatten\u_dut.$auto$ghdl.cc:862:import_module$138 1517 cells in clk=\clk, en={ }, arst={ }, srst={ } 2.35.2. Extracting gate netlist of module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 2.35.3. Extracting gate netlist of module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by \u_dut.rightshiftercomponent.ps [0] 2.35.3.1. Executed ABC. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 2.35.4. Extracting gate netlist of module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by $flatten\u_dut.$auto$ghdl.cc:862:import_module$140 2.35.5. Extracting gate netlist of module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by $flatten\u_dut.$auto$ghdl.cc:862:import_module$86 2.35.6. Extracting gate netlist of module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by !$auto$simplemap.cc:189:logic_reduce$2802 2.35.7. Extracting gate netlist of module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by \u_dut.lzcandshifter.count4 2.35.8. Extracting gate netlist of module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by \u_dut.lzcandshifter.count2 2.35.9. Extracting gate netlist of module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by $flatten\u_dut.$auto$ghdl.cc:862:import_module$138 2.35.10. Extracting gate netlist of module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300' to `/input.blif'.. Found matching posedge clock domain: \clk 2.35.10.1. Executed ABC. Extracted 8 gates and 18 wires to a netlist network with 9 inputs and 7 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.10.2. Re-integrating ABC results. ABC RESULTS: AND cells: 1 ABC RESULTS: ANDNOT cells: 6 ABC RESULTS: DFF cells: 1 ABC RESULTS: XOR cells: 1 ABC RESULTS: internal signals: 2 ABC RESULTS: input signals: 9 ABC RESULTS: output signals: 7 Removing temp directory. 2.35.10.1. Executed ABC. Extracted 2 gates and 5 wires to a netlist network with 3 inputs and 2 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.10.2. Re-integrating ABC results. ABC RESULTS: AND cells: 1 ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 1 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 3 ABC RESULTS: output signals: 2 Removing temp directory. 2.35.10.1. Executed ABC. Extracted 7 gates and 12 wires to a netlist network with 5 inputs and 5 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.10.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 1 ABC RESULTS: NOR cells: 2 ABC RESULTS: OR cells: 2 ABC RESULTS: internal signals: 2 ABC RESULTS: input signals: 5 ABC RESULTS: output signals: 5 Removing temp directory. 2.35.10.1. Executed ABC. Extracted 108 gates and 122 wires to a netlist network with 14 inputs and 3 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.10.2. Re-integrating ABC results. ABC RESULTS: AND cells: 8 ABC RESULTS: DFF cells: 2 ABC RESULTS: NAND cells: 5 ABC RESULTS: NOR cells: 2 ABC RESULTS: NOT cells: 2 ABC RESULTS: OR cells: 6 ABC RESULTS: internal signals: 105 ABC RESULTS: input signals: 14 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.10.1. Executed ABC. Extracted 51 gates and 74 wires to a netlist network with 22 inputs and 41 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.10.2. Re-integrating ABC results. ABC RESULTS: AND cells: 39 ABC RESULTS: BUF cells: 8 ABC RESULTS: DFF cells: 16 ABC RESULTS: MUX cells: 9 ABC RESULTS: NAND cells: 1 ABC RESULTS: NOR cells: 2 ABC RESULTS: internal signals: 11 ABC RESULTS: input signals: 22 ABC RESULTS: output signals: 41 Removing temp directory. 2.35.10.1. Executed ABC. Extracted 11 gates and 20 wires to a netlist network with 8 inputs and 8 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.10.2. Re-integrating ABC results. ABC RESULTS: AND cells: 4 ABC RESULTS: BUF cells: 4 ABC RESULTS: DFF cells: 4 ABC RESULTS: MUX cells: 3 ABC RESULTS: NOT cells: 1 ABC RESULTS: internal signals: 4 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 8 Removing temp directory. 2.35.10.1. Executed ABC. Extracted 42 gates and 54 wires to a netlist network with 11 inputs and 3 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.10.2. Re-integrating ABC results. ABC RESULTS: AND cells: 4 ABC RESULTS: DFF cells: 4 ABC RESULTS: NAND cells: 3 ABC RESULTS: NOR cells: 2 ABC RESULTS: NOT cells: 1 ABC RESULTS: OR cells: 5 ABC RESULTS: internal signals: 40 ABC RESULTS: input signals: 11 ABC RESULTS: output signals: 3 Removing temp directory. 2.35.10.1. Executed ABC. Extracted 1430 gates and 1694 wires to a netlist network with 262 inputs and 338 outputs. Running ABC script: /abc.script ABC: empty ABC: abc 10> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 668 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.35.10.2. Re-integrating ABC results. ABC RESULTS: AND cells: 176 ABC RESULTS: ANDNOT cells: 22 ABC RESULTS: BUF cells: 707 ABC RESULTS: DFF cells: 678 ABC RESULTS: MUX cells: 372 ABC RESULTS: NAND cells: 58 ABC RESULTS: NOR cells: 52 ABC RESULTS: NOT cells: 36 ABC RESULTS: OR cells: 40 ABC RESULTS: ORNOT cells: 28 ABC RESULTS: XNOR cells: 9 ABC RESULTS: XOR cells: 28 ABC RESULTS: internal signals: 1094 ABC RESULTS: input signals: 262 ABC RESULTS: output signals: 338 Removing temp directory. Removing global temp directory. 2.36. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Removed 0 unused cells and 1722 unused wires. 2.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2.38. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 1732 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Computing hashes of 1711 cells of `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Finding duplicate cells in `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Removed a total of 21 cells. 2.39. Executing TECHMAP pass (map to technology primitives). 2.39.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 2.39.2. Continuing TECHMAP pass. Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. No more expansions possible. 2.40. Executing OPT_EXPR pass (perform const folding). Optimizing module top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2.42. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.43. Executing ATTRMVCP pass (move or copy attributes). 2.44. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_flopoco_add_we8_wf35_zynq7000_native_single_f300.. Removed 0 unused cells and 2878 unused wires. 2.45. Executing ABC pass (technology mapping using ABC). 2.45.1. Extracting gate netlist of module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300' to `/input.blif'.. 2.45.1.1. Executed ABC. Extracted 912 gates and 1279 wires to a netlist network with 367 inputs and 309 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.45.1.2. Re-integrating ABC results. ABC RESULTS: AND cells: 134 ABC RESULTS: ANDNOT cells: 39 ABC RESULTS: BUF cells: 8 ABC RESULTS: MUX cells: 346 ABC RESULTS: NAND cells: 139 ABC RESULTS: NOR cells: 60 ABC RESULTS: NOT cells: 20 ABC RESULTS: OR cells: 36 ABC RESULTS: ORNOT cells: 18 ABC RESULTS: XNOR cells: 9 ABC RESULTS: XOR cells: 30 ABC RESULTS: internal signals: 603 ABC RESULTS: input signals: 367 ABC RESULTS: output signals: 309 Removing temp directory. Removing global temp directory. 2.46. Executing TECHMAP pass (map to technology primitives). 2.46.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v' to AST representation. Generating RTLIL representation for module `$_DLATCH_N_'. Generating RTLIL representation for module `$_DLATCH_P_'. Successfully finished Verilog frontend. 2.46.2. Continuing TECHMAP pass. No more expansions possible. 2.47. Executing ABC pass (technology mapping using ABC). 2.47.1. Summary of detected clock domains: 1630 cells in clk={ }, en={ }, arst={ }, srst={ } 2.47.2. Extracting gate netlist of module `\top_flopoco_add_we8_wf35_zynq7000_native_single_f300' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 2.47.2.1. Executed ABC. Extracted 831 gates and 1198 wires to a netlist network with 367 inputs and 301 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_lut /lutdefs.txt ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + dress /input.blif ABC: Total number of equiv classes = 453. ABC: Participating nodes from both networks = 916. ABC: Participating nodes from the first network = 453. ( 86.45 % of nodes) ABC: Participating nodes from the second network = 463. ( 88.36 % of nodes) ABC: Node pairs (any polarity) = 453. ( 86.45 % of names can be moved) ABC: Node pairs (same polarity) = 341. ( 65.08 % of names can be moved) ABC: Total runtime = 0.09 sec ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 2.47.2.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 523 ABC RESULTS: internal signals: 530 ABC RESULTS: input signals: 367 ABC RESULTS: output signals: 301 Removing temp directory. Removing global temp directory. Removed 0 unused cells and 2448 unused wires. 2.48. Executing TECHMAP pass (map to technology primitives). 2.48.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `$lut'. Successfully finished Verilog frontend. 2.48.2. Continuing TECHMAP pass. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod$ee19d45db61acb4c70d938b97483a4ed4b792645$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. Using template $paramod$525425bfbe66d72ee88210d059d9a74f55ab8de8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad$lut for cells of type $lut. Using template $paramod$88ce9346979e3d6a7f710b2c59abd0bda0ba7d2f$lut for cells of type $lut. Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110100 for cells of type $lut. Using template $paramod$4256c04bb9e86f873ba2a112f005a99a8ed41d05$lut for cells of type $lut. Using template $paramod$6a34cd5b50e324824168b4186d0b04ba5e83b039$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d$lut for cells of type $lut. Using template $paramod$b2de3da73df2fd28ff6f42e92fc7e17578e84fc4$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut. Using template $paramod$0348152e094248012a2d34eb139ae88e03b19011$lut for cells of type $lut. Using template $paramod$56d36648044d0bf0f892c2050a60c21ad090a3b1$lut for cells of type $lut. Using template $paramod$a7dad16c080c08c1647c7e1b9706a59a123d8bcd$lut for cells of type $lut. Using template $paramod$49eb50c63a5b5355fa8408239eeac288f1d9f4c3$lut for cells of type $lut. Using template $paramod$e4adb5a40bce606100fc00f292ff9d4f2f55953f$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut. Using template $paramod$ea0faad69a26c91786a25961ea149d0e0961eb1f$lut for cells of type $lut. Using template $paramod$84bef48419505c45080a829b4c4b6379a157eb8b$lut for cells of type $lut. Using template $paramod$e2e4d79bec18c28fa313e8bd8f4df6f8a38115b2$lut for cells of type $lut. Using template $paramod$441de597d9318495d3225f370c9f7379b3b0fd0d$lut for cells of type $lut. Using template $paramod$c9c145a3c6d085b43407e8d146c4cb593e0f20bb$lut for cells of type $lut. Using template $paramod$82acbc31fb96d049b296279a211fd4b4ff0d6451$lut for cells of type $lut. Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba$lut for cells of type $lut. Using template $paramod$ed6b0625315468ee964e10ed4aad4c6c9e54c472$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. Using template $paramod$6a0faddbb1877e236e8eb8130711942937277f4e$lut for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut. Using template $paramod$2e7a95e82db1d690ae9ba5d10f68b175fa2cb467$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod$fc31954e6a68a5c7448bf4aaf328f6c3950ec6c9$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut. Using template $paramod$239ebe5e1b04cc4382b3d7d25db8e84fefb36334$lut for cells of type $lut. Using template $paramod$e74af3ab7cc998ad8c7eee0a29bbd28f399eb453$lut for cells of type $lut. Using template $paramod$e84def7035a68a2d18569f5f9c6d146d821daa01$lut for cells of type $lut. Using template $paramod$b233ccc674ac6535f4d5b3a2192489ded5ad0a5f$lut for cells of type $lut. Using template $paramod$46bf72ab5810854c491462018c9e8bbb912e9006$lut for cells of type $lut. Using template $paramod$1ee2aa56865ceef8718c802e5129f35a1a3f9045$lut for cells of type $lut. Using template $paramod$48a34e0cc8ae39b7650b20005488476b259930f7$lut for cells of type $lut. Using template $paramod$69771af40142f9eb9b8fc2200828329efe745605$lut for cells of type $lut. Using template $paramod$0b26ddfb7924585308e8ededa24b1c7c22c72b08$lut for cells of type $lut. Using template $paramod$0f76e0cf60c7ca87732a612cae84668d1da1cfba$lut for cells of type $lut. Using template $paramod$e28b3072f25d7003fb4e43ba7eefa29740e101f6$lut for cells of type $lut. Using template $paramod$1b5734b5544c164538f3bf1df4733cb10eaa1b91$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$fe069c20df121452df84aab6a091eace3d40f1de$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod$7ea54e9ed89722b394a93168fda83637198532ab$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. Using template $paramod$38da4c7e1070dff9e29f8d4879ee740fdc560873$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. Using template $paramod$a2fa932fcfb6e02138f65e404b3e482c9b9a0c77$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$d9fa741d1c7ab9abf7160de73700d65b5d8e504d$lut for cells of type $lut. Using template $paramod$c7da182350c463dac9341b9202c767a484f2d529$lut for cells of type $lut. Using template $paramod$2f2d30ad17c33d465fc2bec4ac3d3e06dfa86191$lut for cells of type $lut. Using template $paramod$f90697a60a726982387d7d19843481b429801dc5$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$09d60b2e81893aee88f45a63a36cab01326b7fd3$lut for cells of type $lut. Using template $paramod$63f61ba721477ff7fa525222e7d64fb5629fc02e$lut for cells of type $lut. Using template $paramod$a7e7b155f27f423f1495a5a06dc3b15422f2d7ef$lut for cells of type $lut. Using template $paramod$ca1a0fe3461364dc91ed85eb44772608309fe7a6$lut for cells of type $lut. Using template $paramod$55668dfd6e901cbdb37e2cafeb410b9fc2f26615$lut for cells of type $lut. Using template $paramod$f7caa01c910cba1c02843a3b6c26d51fa10a63f5$lut for cells of type $lut. Using template $paramod$be3bf305f48d39cb0e8c634ad4f2bf75e40756f6$lut for cells of type $lut. Using template $paramod$2754a21a217ccdc1a0cbf27b2e8b19266cadc23f$lut for cells of type $lut. Using template $paramod$bebd8519b635f27d662e1f62360db155ec2d7349$lut for cells of type $lut. Using template $paramod$fe04f45b995a932c6ade7dfd42d32d2547497c10$lut for cells of type $lut. Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585$lut for cells of type $lut. Using template $paramod$376b64e1b363367ba758e2d4a9f90bb42b7b6248$lut for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut. Using template $paramod$ad823946862e656cf7f96d606b18b8f972dc6d6c$lut for cells of type $lut. Using template $paramod$664d4f6063c66290be5af3d205d1b83dcbdd49a3$lut for cells of type $lut. Using template $paramod$346842b88e407bf40d83dc890111dffae3530202$lut for cells of type $lut. Using template $paramod$60b758fd5679f6508bff32bea2afedb4f329e5f9$lut for cells of type $lut. Using template $paramod$6e0fd2dfc2b70a446e9beaceb3011ff5b00df705$lut for cells of type $lut. Using template $paramod$c752c925a2f2a50ce5b14ae0fe3f3a9d0ae03374$lut for cells of type $lut. Using template $paramod$d7cd89d86a18957bc4c7791642950ca494fc9ba5$lut for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut. Using template $paramod$243c00f5eb9faa1d5ce3478fdc389a56070781f8$lut for cells of type $lut. Using template $paramod$50c9ef09577c00a6e952c67044adc6178d920682$lut for cells of type $lut. Using template $paramod$a20b0c093af372402eecf32644de5f0208303079$lut for cells of type $lut. Using template $paramod$02fbd2dfd8b419c0d6fd5205680ad063cd40eac8$lut for cells of type $lut. Using template $paramod$256f3f936b752cf569dca900ae92c3ac452c7e57$lut for cells of type $lut. Using template $paramod$703a13a751e631ef123f38f7d2125aeabec0f94c$lut for cells of type $lut. Using template $paramod$52b0f43ae6cb52b5e726dd3244952f6f33bb5f19$lut for cells of type $lut. Using template $paramod$861eb78e09ea1cfbaa863db1d3135d3ddef062aa$lut for cells of type $lut. Using template $paramod$f10d6614b44088003e50763c883f04b3149b468b$lut for cells of type $lut. Using template $paramod$bd30352060eda40d6d7e1ed867e66b155bc1407b$lut for cells of type $lut. Using template $paramod$5b8f7b2cbcd9a11306d57ef0dafcaab052565b62$lut for cells of type $lut. Using template $paramod$bb1b7627e4e156e086009aa4b0b9f459ff6ddfb7$lut for cells of type $lut. Using template $paramod$d0bf26260eea0e8530fb2e72eb38c60e28a47da8$lut for cells of type $lut. Using template $paramod$42671f490270e6e075464851963798fa7f9d6a89$lut for cells of type $lut. Using template $paramod$10a096fcd66009cf8bdf006201a36b76f3a89ef9$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut. Using template $paramod$1de44515684aa8aea9bdebdc5793069f38e4f9c5$lut for cells of type $lut. Using template $paramod$d9ff7a04c5e767d1221b26c2df1f5910a9e00e0a$lut for cells of type $lut. Using template $paramod$e931cbf42f29aa0096abb676af28cf7aa272eb1c$lut for cells of type $lut. Using template $paramod$979a1540d9d84a1b978484dd3c1546222eff647c$lut for cells of type $lut. Using template $paramod$75bb2d74a13546c2edde2d13d10d2a7ccc79f674$lut for cells of type $lut. Using template $paramod$567c88aae42dccbe783883a6f4de8c08b68ec9b5$lut for cells of type $lut. Using template $paramod$d83937b7b81bdc747029a3d9ace36bcbff93ba93$lut for cells of type $lut. Using template $paramod$f5c5f595015aee4de78d8a59fd7b7003b8956fde$lut for cells of type $lut. Using template $paramod$19ec49f31a8d230a567aa44ce3ea81a03c101e2b$lut for cells of type $lut. Using template $paramod$4ef6e6098a3ccd9bd87660b261f7c8ebb6947c76$lut for cells of type $lut. Using template $paramod$7a988de7554d6c5e09a742c0a2d36472e50c73b1$lut for cells of type $lut. Using template $paramod$eb453e5c4284f97a8ffea70cb552841f9d2d6223$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod$d9d659141d075841677b673978285781f104f4c4$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110001 for cells of type $lut. Using template $paramod$2902eb8ec3ca272968b5d8a7010e48f85069ed0f$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut. No more expansions possible. 2.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in top_flopoco_add_we8_wf35_zynq7000_native_single_f300. Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8753.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8748.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8757.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8764.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8769.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8785.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8802.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8804.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8805.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8807.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8799.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8741.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8743.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8795.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8720.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8730.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8730.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8728.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9020.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9045.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9047.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9049.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9051.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9053.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8884.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8823.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8824.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8825.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8750.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8730.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8753.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8773.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8757.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8776.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8768.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8785.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8792.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8837.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8737.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8850.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8869.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8883.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8887.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9045.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9071.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9075.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9107.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9079.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9083.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9109.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9112.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9115.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9083.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$9196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$8684$auto$blifparse.cc:557:parse_blif$8691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Removed 0 unused cells and 1240 unused wires. 2.50. Executing AUTONAME pass. Renamed 3392 objects in module top_flopoco_add_we8_wf35_zynq7000_native_single_f300 (530 iterations). 2.51. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `top_flopoco_add_we8_wf35_zynq7000_native_single_f300'. Setting top module to top_flopoco_add_we8_wf35_zynq7000_native_single_f300. 2.51.1. Analyzing design hierarchy.. Top module: \top_flopoco_add_we8_wf35_zynq7000_native_single_f300 2.51.2. Analyzing design hierarchy.. Top module: \top_flopoco_add_we8_wf35_zynq7000_native_single_f300 Removed 0 unused modules. 2.52. Printing statistics. === top_flopoco_add_we8_wf35_zynq7000_native_single_f300 === +----------Local Count, excluding submodules. | 1514 wires 5816 wire bits 1514 public wires 5816 public wire bits 4 ports 139 port bits 5 cells 5 $scopeinfo 1993 submodules 87 CCU2C 100 L6MUX21 861 LUT4 238 PFUMX 707 TRELLIS_FF === design hierarchy === +----------Count including submodules. | 5 top_flopoco_add_we8_wf35_zynq7000_native_single_f300 +----------Count including submodules. | 1514 wires 5816 wire bits 1514 public wires 5816 public wire bits 4 ports 139 port bits - memories - memory bits - processes 5 cells 5 $scopeinfo 1993 submodules 87 CCU2C 100 L6MUX21 861 LUT4 238 PFUMX 707 TRELLIS_FF 2.53. Executing CHECK pass (checking for obvious problems). Checking module top_flopoco_add_we8_wf35_zynq7000_native_single_f300... Found and reported 0 problems. 2.54. Executing JSON backend. End of script. Logfile hash: 39970dac56, time: 4.39s, user: 3.14s, system: 0.13s, MEM: 114.35 MB peak Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3) Time spent: 30% 3x abc (1 sec), 25% 1x autoname (1 sec), ... $ yosys -m ghdl -s /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/flopoco_add_we8_wf35_zynq7000_native_single_f300/yosys.ys [exit code 0]