Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2025.2.1 (lin64) Build 6403652 Thu Mar 19 13:47:00 MDT 2026
| Date         : Sat May 23 22:43:36 2026
| Host         : deep-thought running 64-bit Manjaro Linux
| Command      : report_timing_summary -file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/zkf_div_w8_m36_base/timing_summary.rpt -max_paths 10 -nworst 10
| Design       : top_zkf_div_w8_m36_base
| Device       : 7s50-csga324
| Speed File   : -1  PRODUCTION 1.23 2018-06-13
| Design State : Routed
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (90)
6. checking no_output_delay (46)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (90)
-------------------------------
 There are 90 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (46)
--------------------------------
 There are 46 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.499        0.000                      0                 2335        0.058        0.000                      0                 2335        2.353        0.000                       0                  2424  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock  Waveform(ns)         Period(ns)      Frequency(MHz)
-----  ------------         ----------      --------------
clk    {0.000 3.333}        6.667           149.993         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
clk                 0.499        0.000                      0                 2335        0.058        0.000                      0                 2335        2.353        0.000                       0                  2424  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  clk
  To Clock:  clk

Setup :            0  Failing Endpoints,  Worst Slack        0.499ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.058ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.353ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.499ns  (required time - arrival time)
  Source:                 u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.159ns  (logic 2.866ns (46.534%)  route 3.293ns (53.466%))
  Logic Levels:           13  (CARRY4=10 LUT1=1 LUT3=1 LUT5=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.973     0.973    u_dut/u_core/clk
    SLICE_X9Y79          FDRE                                         r  u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y79          FDRE (Prop_fdre_C_Q)         0.456     1.429 f  u_dut/u_core/g_stage[16].r_den_reg[16][0]/Q
                         net (fo=5, routed)           0.641     2.070    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_0[0]
    SLICE_X8Y79          LUT1 (Prop_lut1_I0_O)        0.124     2.194 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7/O
                         net (fo=1, routed)           0.680     2.873    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7_n_0
    SLICE_X9Y85          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.580     3.453 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.453    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3_n_0
    SLICE_X9Y86          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.567 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.567    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8_n_0
    SLICE_X9Y87          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.681 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.681    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8_n_0
    SLICE_X9Y88          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.795 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.795    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8_n_0
    SLICE_X9Y89          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.909 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.909    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8_n_0
    SLICE_X9Y90          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.023 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.023    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8_n_0
    SLICE_X9Y91          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.137 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.137    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8_n_0
    SLICE_X9Y92          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.251 r  u_dut/u_core/g_stage[18].u_raw/i__i_15__15/CO[3]
                         net (fo=1, routed)           0.000     4.251    u_dut/u_core/g_stage[18].u_raw/i__i_15__15_n_0
    SLICE_X9Y93          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.365 r  u_dut/u_core/g_stage[18].u_raw/i__i_6__15/CO[3]
                         net (fo=1, routed)           0.000     4.365    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_n_0
    SLICE_X9Y94          CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     4.636 r  u_dut/u_core/g_stage[18].u_raw/i__i_2__15/CO[0]
                         net (fo=37, routed)          1.329     5.965    u_dut/u_core/g_stage[18].u_raw_n_1799
    SLICE_X13Y81         LUT5 (Prop_lut5_I3_O)        0.373     6.338 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_2/O
                         net (fo=1, routed)           0.643     6.982    u_dut/u_core/g_stage[17].r_rem[17][13]_i_2_n_0
    SLICE_X13Y81         LUT3 (Prop_lut3_I2_O)        0.150     7.132 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_1/O
                         net (fo=1, routed)           0.000     7.132    u_dut/u_core/g_stage[17].rem_next[13]
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=2423, unset)         0.924     7.591    u_dut/u_core/clk
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X13Y81         FDRE (Setup_fdre_C_D)        0.075     7.631    u_dut/u_core/g_stage[17].r_rem_reg[17][13]
  -------------------------------------------------------------------
                         required time                          7.631    
                         arrival time                          -7.132    
  -------------------------------------------------------------------
                         slack                                  0.499    

Slack (MET) :             0.499ns  (required time - arrival time)
  Source:                 u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.159ns  (logic 2.866ns (46.534%)  route 3.293ns (53.466%))
  Logic Levels:           13  (CARRY4=10 LUT1=1 LUT3=1 LUT5=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.973     0.973    u_dut/u_core/clk
    SLICE_X9Y79          FDRE                                         r  u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y79          FDRE (Prop_fdre_C_Q)         0.456     1.429 f  u_dut/u_core/g_stage[16].r_den_reg[16][0]/Q
                         net (fo=5, routed)           0.641     2.070    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_0[0]
    SLICE_X8Y79          LUT1 (Prop_lut1_I0_O)        0.124     2.194 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7/O
                         net (fo=1, routed)           0.680     2.873    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7_n_0
    SLICE_X9Y85          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.580     3.453 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.453    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3_n_0
    SLICE_X9Y86          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.567 f  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.567    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8_n_0
    SLICE_X9Y87          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.681 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.681    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8_n_0
    SLICE_X9Y88          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.795 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.795    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8_n_0
    SLICE_X9Y89          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.909 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.909    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8_n_0
    SLICE_X9Y90          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.023 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.023    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8_n_0
    SLICE_X9Y91          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.137 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.137    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8_n_0
    SLICE_X9Y92          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.251 r  u_dut/u_core/g_stage[18].u_raw/i__i_15__15/CO[3]
                         net (fo=1, routed)           0.000     4.251    u_dut/u_core/g_stage[18].u_raw/i__i_15__15_n_0
    SLICE_X9Y93          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.365 r  u_dut/u_core/g_stage[18].u_raw/i__i_6__15/CO[3]
                         net (fo=1, routed)           0.000     4.365    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_n_0
    SLICE_X9Y94          CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     4.636 r  u_dut/u_core/g_stage[18].u_raw/i__i_2__15/CO[0]
                         net (fo=37, routed)          1.329     5.965    u_dut/u_core/g_stage[18].u_raw_n_1799
    SLICE_X13Y81         LUT5 (Prop_lut5_I3_O)        0.373     6.338 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_2/O
                         net (fo=1, routed)           0.643     6.982    u_dut/u_core/g_stage[17].r_rem[17][13]_i_2_n_0
    SLICE_X13Y81         LUT3 (Prop_lut3_I2_O)        0.150     7.132 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_1/O
                         net (fo=1, routed)           0.000     7.132    u_dut/u_core/g_stage[17].rem_next[13]
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=2423, unset)         0.924     7.591    u_dut/u_core/clk
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X13Y81         FDRE (Setup_fdre_C_D)        0.075     7.631    u_dut/u_core/g_stage[17].r_rem_reg[17][13]
  -------------------------------------------------------------------
                         required time                          7.631    
                         arrival time                          -7.132    
  -------------------------------------------------------------------
                         slack                                  0.499    

Slack (MET) :             0.499ns  (required time - arrival time)
  Source:                 u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.159ns  (logic 2.866ns (46.534%)  route 3.293ns (53.466%))
  Logic Levels:           13  (CARRY4=10 LUT1=1 LUT3=1 LUT5=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.973     0.973    u_dut/u_core/clk
    SLICE_X9Y79          FDRE                                         r  u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y79          FDRE (Prop_fdre_C_Q)         0.456     1.429 f  u_dut/u_core/g_stage[16].r_den_reg[16][0]/Q
                         net (fo=5, routed)           0.641     2.070    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_0[0]
    SLICE_X8Y79          LUT1 (Prop_lut1_I0_O)        0.124     2.194 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7/O
                         net (fo=1, routed)           0.680     2.873    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7_n_0
    SLICE_X9Y85          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.580     3.453 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.453    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3_n_0
    SLICE_X9Y86          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.567 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.567    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8_n_0
    SLICE_X9Y87          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.681 f  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.681    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8_n_0
    SLICE_X9Y88          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.795 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.795    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8_n_0
    SLICE_X9Y89          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.909 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.909    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8_n_0
    SLICE_X9Y90          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.023 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.023    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8_n_0
    SLICE_X9Y91          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.137 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.137    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8_n_0
    SLICE_X9Y92          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.251 r  u_dut/u_core/g_stage[18].u_raw/i__i_15__15/CO[3]
                         net (fo=1, routed)           0.000     4.251    u_dut/u_core/g_stage[18].u_raw/i__i_15__15_n_0
    SLICE_X9Y93          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.365 r  u_dut/u_core/g_stage[18].u_raw/i__i_6__15/CO[3]
                         net (fo=1, routed)           0.000     4.365    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_n_0
    SLICE_X9Y94          CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     4.636 r  u_dut/u_core/g_stage[18].u_raw/i__i_2__15/CO[0]
                         net (fo=37, routed)          1.329     5.965    u_dut/u_core/g_stage[18].u_raw_n_1799
    SLICE_X13Y81         LUT5 (Prop_lut5_I3_O)        0.373     6.338 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_2/O
                         net (fo=1, routed)           0.643     6.982    u_dut/u_core/g_stage[17].r_rem[17][13]_i_2_n_0
    SLICE_X13Y81         LUT3 (Prop_lut3_I2_O)        0.150     7.132 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_1/O
                         net (fo=1, routed)           0.000     7.132    u_dut/u_core/g_stage[17].rem_next[13]
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=2423, unset)         0.924     7.591    u_dut/u_core/clk
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X13Y81         FDRE (Setup_fdre_C_D)        0.075     7.631    u_dut/u_core/g_stage[17].r_rem_reg[17][13]
  -------------------------------------------------------------------
                         required time                          7.631    
                         arrival time                          -7.132    
  -------------------------------------------------------------------
                         slack                                  0.499    

Slack (MET) :             0.499ns  (required time - arrival time)
  Source:                 u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.159ns  (logic 2.866ns (46.534%)  route 3.293ns (53.466%))
  Logic Levels:           13  (CARRY4=10 LUT1=1 LUT3=1 LUT5=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.973     0.973    u_dut/u_core/clk
    SLICE_X9Y79          FDRE                                         r  u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y79          FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/u_core/g_stage[16].r_den_reg[16][0]/Q
                         net (fo=5, routed)           0.641     2.070    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_0[0]
    SLICE_X8Y79          LUT1 (Prop_lut1_I0_O)        0.124     2.194 f  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7/O
                         net (fo=1, routed)           0.680     2.873    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7_n_0
    SLICE_X9Y85          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.580     3.453 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.453    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3_n_0
    SLICE_X9Y86          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.567 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.567    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8_n_0
    SLICE_X9Y87          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.681 f  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.681    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8_n_0
    SLICE_X9Y88          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.795 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.795    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8_n_0
    SLICE_X9Y89          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.909 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.909    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8_n_0
    SLICE_X9Y90          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.023 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.023    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8_n_0
    SLICE_X9Y91          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.137 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.137    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8_n_0
    SLICE_X9Y92          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.251 r  u_dut/u_core/g_stage[18].u_raw/i__i_15__15/CO[3]
                         net (fo=1, routed)           0.000     4.251    u_dut/u_core/g_stage[18].u_raw/i__i_15__15_n_0
    SLICE_X9Y93          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.365 r  u_dut/u_core/g_stage[18].u_raw/i__i_6__15/CO[3]
                         net (fo=1, routed)           0.000     4.365    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_n_0
    SLICE_X9Y94          CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     4.636 r  u_dut/u_core/g_stage[18].u_raw/i__i_2__15/CO[0]
                         net (fo=37, routed)          1.329     5.965    u_dut/u_core/g_stage[18].u_raw_n_1799
    SLICE_X13Y81         LUT5 (Prop_lut5_I3_O)        0.373     6.338 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_2/O
                         net (fo=1, routed)           0.643     6.982    u_dut/u_core/g_stage[17].r_rem[17][13]_i_2_n_0
    SLICE_X13Y81         LUT3 (Prop_lut3_I2_O)        0.150     7.132 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_1/O
                         net (fo=1, routed)           0.000     7.132    u_dut/u_core/g_stage[17].rem_next[13]
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=2423, unset)         0.924     7.591    u_dut/u_core/clk
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X13Y81         FDRE (Setup_fdre_C_D)        0.075     7.631    u_dut/u_core/g_stage[17].r_rem_reg[17][13]
  -------------------------------------------------------------------
                         required time                          7.631    
                         arrival time                          -7.132    
  -------------------------------------------------------------------
                         slack                                  0.499    

Slack (MET) :             0.499ns  (required time - arrival time)
  Source:                 u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.159ns  (logic 2.866ns (46.534%)  route 3.293ns (53.466%))
  Logic Levels:           13  (CARRY4=10 LUT1=1 LUT3=1 LUT5=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.973     0.973    u_dut/u_core/clk
    SLICE_X9Y79          FDRE                                         r  u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y79          FDRE (Prop_fdre_C_Q)         0.456     1.429 f  u_dut/u_core/g_stage[16].r_den_reg[16][0]/Q
                         net (fo=5, routed)           0.641     2.070    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_0[0]
    SLICE_X8Y79          LUT1 (Prop_lut1_I0_O)        0.124     2.194 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7/O
                         net (fo=1, routed)           0.680     2.873    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7_n_0
    SLICE_X9Y85          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.580     3.453 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.453    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3_n_0
    SLICE_X9Y86          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.567 f  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.567    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8_n_0
    SLICE_X9Y87          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.681 f  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.681    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8_n_0
    SLICE_X9Y88          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.795 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.795    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8_n_0
    SLICE_X9Y89          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.909 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.909    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8_n_0
    SLICE_X9Y90          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.023 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.023    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8_n_0
    SLICE_X9Y91          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.137 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.137    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8_n_0
    SLICE_X9Y92          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.251 r  u_dut/u_core/g_stage[18].u_raw/i__i_15__15/CO[3]
                         net (fo=1, routed)           0.000     4.251    u_dut/u_core/g_stage[18].u_raw/i__i_15__15_n_0
    SLICE_X9Y93          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.365 r  u_dut/u_core/g_stage[18].u_raw/i__i_6__15/CO[3]
                         net (fo=1, routed)           0.000     4.365    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_n_0
    SLICE_X9Y94          CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     4.636 r  u_dut/u_core/g_stage[18].u_raw/i__i_2__15/CO[0]
                         net (fo=37, routed)          1.329     5.965    u_dut/u_core/g_stage[18].u_raw_n_1799
    SLICE_X13Y81         LUT5 (Prop_lut5_I3_O)        0.373     6.338 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_2/O
                         net (fo=1, routed)           0.643     6.982    u_dut/u_core/g_stage[17].r_rem[17][13]_i_2_n_0
    SLICE_X13Y81         LUT3 (Prop_lut3_I2_O)        0.150     7.132 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_1/O
                         net (fo=1, routed)           0.000     7.132    u_dut/u_core/g_stage[17].rem_next[13]
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=2423, unset)         0.924     7.591    u_dut/u_core/clk
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X13Y81         FDRE (Setup_fdre_C_D)        0.075     7.631    u_dut/u_core/g_stage[17].r_rem_reg[17][13]
  -------------------------------------------------------------------
                         required time                          7.631    
                         arrival time                          -7.132    
  -------------------------------------------------------------------
                         slack                                  0.499    

Slack (MET) :             0.499ns  (required time - arrival time)
  Source:                 u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.159ns  (logic 2.866ns (46.534%)  route 3.293ns (53.466%))
  Logic Levels:           13  (CARRY4=10 LUT1=1 LUT3=1 LUT5=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.973     0.973    u_dut/u_core/clk
    SLICE_X9Y79          FDRE                                         r  u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y79          FDRE (Prop_fdre_C_Q)         0.456     1.429 f  u_dut/u_core/g_stage[16].r_den_reg[16][0]/Q
                         net (fo=5, routed)           0.641     2.070    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_0[0]
    SLICE_X8Y79          LUT1 (Prop_lut1_I0_O)        0.124     2.194 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7/O
                         net (fo=1, routed)           0.680     2.873    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7_n_0
    SLICE_X9Y85          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.580     3.453 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.453    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3_n_0
    SLICE_X9Y86          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.567 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.567    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8_n_0
    SLICE_X9Y87          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.681 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.681    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8_n_0
    SLICE_X9Y88          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.795 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.795    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8_n_0
    SLICE_X9Y89          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.909 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.909    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8_n_0
    SLICE_X9Y90          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.023 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.023    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8_n_0
    SLICE_X9Y91          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.137 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.137    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8_n_0
    SLICE_X9Y92          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.251 r  u_dut/u_core/g_stage[18].u_raw/i__i_15__15/CO[3]
                         net (fo=1, routed)           0.000     4.251    u_dut/u_core/g_stage[18].u_raw/i__i_15__15_n_0
    SLICE_X9Y93          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.365 f  u_dut/u_core/g_stage[18].u_raw/i__i_6__15/CO[3]
                         net (fo=1, routed)           0.000     4.365    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_n_0
    SLICE_X9Y94          CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     4.636 r  u_dut/u_core/g_stage[18].u_raw/i__i_2__15/CO[0]
                         net (fo=37, routed)          1.329     5.965    u_dut/u_core/g_stage[18].u_raw_n_1799
    SLICE_X13Y81         LUT5 (Prop_lut5_I3_O)        0.373     6.338 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_2/O
                         net (fo=1, routed)           0.643     6.982    u_dut/u_core/g_stage[17].r_rem[17][13]_i_2_n_0
    SLICE_X13Y81         LUT3 (Prop_lut3_I2_O)        0.150     7.132 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_1/O
                         net (fo=1, routed)           0.000     7.132    u_dut/u_core/g_stage[17].rem_next[13]
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=2423, unset)         0.924     7.591    u_dut/u_core/clk
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X13Y81         FDRE (Setup_fdre_C_D)        0.075     7.631    u_dut/u_core/g_stage[17].r_rem_reg[17][13]
  -------------------------------------------------------------------
                         required time                          7.631    
                         arrival time                          -7.132    
  -------------------------------------------------------------------
                         slack                                  0.499    

Slack (MET) :             0.499ns  (required time - arrival time)
  Source:                 u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.159ns  (logic 2.866ns (46.534%)  route 3.293ns (53.466%))
  Logic Levels:           13  (CARRY4=10 LUT1=1 LUT3=1 LUT5=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.973     0.973    u_dut/u_core/clk
    SLICE_X9Y79          FDRE                                         r  u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y79          FDRE (Prop_fdre_C_Q)         0.456     1.429 r  u_dut/u_core/g_stage[16].r_den_reg[16][0]/Q
                         net (fo=5, routed)           0.641     2.070    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_0[0]
    SLICE_X8Y79          LUT1 (Prop_lut1_I0_O)        0.124     2.194 f  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7/O
                         net (fo=1, routed)           0.680     2.873    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7_n_0
    SLICE_X9Y85          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.580     3.453 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.453    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3_n_0
    SLICE_X9Y86          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.567 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.567    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8_n_0
    SLICE_X9Y87          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.681 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.681    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8_n_0
    SLICE_X9Y88          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.795 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.795    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8_n_0
    SLICE_X9Y89          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.909 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.909    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8_n_0
    SLICE_X9Y90          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.023 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.023    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8_n_0
    SLICE_X9Y91          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.137 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.137    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8_n_0
    SLICE_X9Y92          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.251 r  u_dut/u_core/g_stage[18].u_raw/i__i_15__15/CO[3]
                         net (fo=1, routed)           0.000     4.251    u_dut/u_core/g_stage[18].u_raw/i__i_15__15_n_0
    SLICE_X9Y93          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.365 f  u_dut/u_core/g_stage[18].u_raw/i__i_6__15/CO[3]
                         net (fo=1, routed)           0.000     4.365    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_n_0
    SLICE_X9Y94          CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     4.636 r  u_dut/u_core/g_stage[18].u_raw/i__i_2__15/CO[0]
                         net (fo=37, routed)          1.329     5.965    u_dut/u_core/g_stage[18].u_raw_n_1799
    SLICE_X13Y81         LUT5 (Prop_lut5_I3_O)        0.373     6.338 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_2/O
                         net (fo=1, routed)           0.643     6.982    u_dut/u_core/g_stage[17].r_rem[17][13]_i_2_n_0
    SLICE_X13Y81         LUT3 (Prop_lut3_I2_O)        0.150     7.132 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_1/O
                         net (fo=1, routed)           0.000     7.132    u_dut/u_core/g_stage[17].rem_next[13]
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=2423, unset)         0.924     7.591    u_dut/u_core/clk
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X13Y81         FDRE (Setup_fdre_C_D)        0.075     7.631    u_dut/u_core/g_stage[17].r_rem_reg[17][13]
  -------------------------------------------------------------------
                         required time                          7.631    
                         arrival time                          -7.132    
  -------------------------------------------------------------------
                         slack                                  0.499    

Slack (MET) :             0.499ns  (required time - arrival time)
  Source:                 u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.159ns  (logic 2.866ns (46.534%)  route 3.293ns (53.466%))
  Logic Levels:           13  (CARRY4=10 LUT1=1 LUT3=1 LUT5=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.973     0.973    u_dut/u_core/clk
    SLICE_X9Y79          FDRE                                         r  u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y79          FDRE (Prop_fdre_C_Q)         0.456     1.429 f  u_dut/u_core/g_stage[16].r_den_reg[16][0]/Q
                         net (fo=5, routed)           0.641     2.070    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_0[0]
    SLICE_X8Y79          LUT1 (Prop_lut1_I0_O)        0.124     2.194 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7/O
                         net (fo=1, routed)           0.680     2.873    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7_n_0
    SLICE_X9Y85          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.580     3.453 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.453    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3_n_0
    SLICE_X9Y86          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.567 f  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.567    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8_n_0
    SLICE_X9Y87          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.681 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.681    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8_n_0
    SLICE_X9Y88          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.795 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.795    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8_n_0
    SLICE_X9Y89          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.909 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.909    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8_n_0
    SLICE_X9Y90          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.023 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.023    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8_n_0
    SLICE_X9Y91          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.137 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.137    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8_n_0
    SLICE_X9Y92          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.251 r  u_dut/u_core/g_stage[18].u_raw/i__i_15__15/CO[3]
                         net (fo=1, routed)           0.000     4.251    u_dut/u_core/g_stage[18].u_raw/i__i_15__15_n_0
    SLICE_X9Y93          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.365 f  u_dut/u_core/g_stage[18].u_raw/i__i_6__15/CO[3]
                         net (fo=1, routed)           0.000     4.365    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_n_0
    SLICE_X9Y94          CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     4.636 r  u_dut/u_core/g_stage[18].u_raw/i__i_2__15/CO[0]
                         net (fo=37, routed)          1.329     5.965    u_dut/u_core/g_stage[18].u_raw_n_1799
    SLICE_X13Y81         LUT5 (Prop_lut5_I3_O)        0.373     6.338 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_2/O
                         net (fo=1, routed)           0.643     6.982    u_dut/u_core/g_stage[17].r_rem[17][13]_i_2_n_0
    SLICE_X13Y81         LUT3 (Prop_lut3_I2_O)        0.150     7.132 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_1/O
                         net (fo=1, routed)           0.000     7.132    u_dut/u_core/g_stage[17].rem_next[13]
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=2423, unset)         0.924     7.591    u_dut/u_core/clk
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X13Y81         FDRE (Setup_fdre_C_D)        0.075     7.631    u_dut/u_core/g_stage[17].r_rem_reg[17][13]
  -------------------------------------------------------------------
                         required time                          7.631    
                         arrival time                          -7.132    
  -------------------------------------------------------------------
                         slack                                  0.499    

Slack (MET) :             0.499ns  (required time - arrival time)
  Source:                 u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.159ns  (logic 2.866ns (46.534%)  route 3.293ns (53.466%))
  Logic Levels:           13  (CARRY4=10 LUT1=1 LUT3=1 LUT5=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.973     0.973    u_dut/u_core/clk
    SLICE_X9Y79          FDRE                                         r  u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y79          FDRE (Prop_fdre_C_Q)         0.456     1.429 f  u_dut/u_core/g_stage[16].r_den_reg[16][0]/Q
                         net (fo=5, routed)           0.641     2.070    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_0[0]
    SLICE_X8Y79          LUT1 (Prop_lut1_I0_O)        0.124     2.194 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7/O
                         net (fo=1, routed)           0.680     2.873    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7_n_0
    SLICE_X9Y85          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.580     3.453 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.453    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3_n_0
    SLICE_X9Y86          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.567 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.567    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8_n_0
    SLICE_X9Y87          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.681 f  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.681    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8_n_0
    SLICE_X9Y88          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.795 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.795    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8_n_0
    SLICE_X9Y89          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.909 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.909    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8_n_0
    SLICE_X9Y90          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.023 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.023    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8_n_0
    SLICE_X9Y91          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.137 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.137    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8_n_0
    SLICE_X9Y92          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.251 r  u_dut/u_core/g_stage[18].u_raw/i__i_15__15/CO[3]
                         net (fo=1, routed)           0.000     4.251    u_dut/u_core/g_stage[18].u_raw/i__i_15__15_n_0
    SLICE_X9Y93          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.365 f  u_dut/u_core/g_stage[18].u_raw/i__i_6__15/CO[3]
                         net (fo=1, routed)           0.000     4.365    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_n_0
    SLICE_X9Y94          CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     4.636 r  u_dut/u_core/g_stage[18].u_raw/i__i_2__15/CO[0]
                         net (fo=37, routed)          1.329     5.965    u_dut/u_core/g_stage[18].u_raw_n_1799
    SLICE_X13Y81         LUT5 (Prop_lut5_I3_O)        0.373     6.338 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_2/O
                         net (fo=1, routed)           0.643     6.982    u_dut/u_core/g_stage[17].r_rem[17][13]_i_2_n_0
    SLICE_X13Y81         LUT3 (Prop_lut3_I2_O)        0.150     7.132 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_1/O
                         net (fo=1, routed)           0.000     7.132    u_dut/u_core/g_stage[17].rem_next[13]
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=2423, unset)         0.924     7.591    u_dut/u_core/clk
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X13Y81         FDRE (Setup_fdre_C_D)        0.075     7.631    u_dut/u_core/g_stage[17].r_rem_reg[17][13]
  -------------------------------------------------------------------
                         required time                          7.631    
                         arrival time                          -7.132    
  -------------------------------------------------------------------
                         slack                                  0.499    

Slack (MET) :             0.499ns  (required time - arrival time)
  Source:                 u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        6.159ns  (logic 2.866ns (46.534%)  route 3.293ns (53.466%))
  Logic Levels:           13  (CARRY4=10 LUT1=1 LUT3=1 LUT5=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.973     0.973    u_dut/u_core/clk
    SLICE_X9Y79          FDRE                                         r  u_dut/u_core/g_stage[16].r_den_reg[16][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y79          FDRE (Prop_fdre_C_Q)         0.456     1.429 f  u_dut/u_core/g_stage[16].r_den_reg[16][0]/Q
                         net (fo=5, routed)           0.641     2.070    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_0[0]
    SLICE_X8Y79          LUT1 (Prop_lut1_I0_O)        0.124     2.194 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7/O
                         net (fo=1, routed)           0.680     2.873    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem[17][1]_i_7_n_0
    SLICE_X9Y85          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.580     3.453 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3/CO[3]
                         net (fo=1, routed)           0.000     3.453    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][1]_i_3_n_0
    SLICE_X9Y86          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.567 f  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.567    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][8]_i_8_n_0
    SLICE_X9Y87          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.681 f  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.681    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][12]_i_8_n_0
    SLICE_X9Y88          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.795 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.795    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][16]_i_8_n_0
    SLICE_X9Y89          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.909 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8/CO[3]
                         net (fo=1, routed)           0.000     3.909    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][20]_i_8_n_0
    SLICE_X9Y90          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.023 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.023    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][24]_i_8_n_0
    SLICE_X9Y91          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.137 r  u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8/CO[3]
                         net (fo=1, routed)           0.000     4.137    u_dut/u_core/g_stage[18].u_raw/g_stage[17].r_rem_reg[17][28]_i_8_n_0
    SLICE_X9Y92          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.251 r  u_dut/u_core/g_stage[18].u_raw/i__i_15__15/CO[3]
                         net (fo=1, routed)           0.000     4.251    u_dut/u_core/g_stage[18].u_raw/i__i_15__15_n_0
    SLICE_X9Y93          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.365 f  u_dut/u_core/g_stage[18].u_raw/i__i_6__15/CO[3]
                         net (fo=1, routed)           0.000     4.365    u_dut/u_core/g_stage[18].u_raw/i__i_6__15_n_0
    SLICE_X9Y94          CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     4.636 r  u_dut/u_core/g_stage[18].u_raw/i__i_2__15/CO[0]
                         net (fo=37, routed)          1.329     5.965    u_dut/u_core/g_stage[18].u_raw_n_1799
    SLICE_X13Y81         LUT5 (Prop_lut5_I3_O)        0.373     6.338 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_2/O
                         net (fo=1, routed)           0.643     6.982    u_dut/u_core/g_stage[17].r_rem[17][13]_i_2_n_0
    SLICE_X13Y81         LUT3 (Prop_lut3_I2_O)        0.150     7.132 r  u_dut/u_core/g_stage[17].r_rem[17][13]_i_1/O
                         net (fo=1, routed)           0.000     7.132    u_dut/u_core/g_stage[17].rem_next[13]
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=2423, unset)         0.924     7.591    u_dut/u_core/clk
    SLICE_X13Y81         FDRE                                         r  u_dut/u_core/g_stage[17].r_rem_reg[17][13]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X13Y81         FDRE (Setup_fdre_C_D)        0.075     7.631    u_dut/u_core/g_stage[17].r_rem_reg[17][13]
  -------------------------------------------------------------------
                         required time                          7.631    
                         arrival time                          -7.132    
  -------------------------------------------------------------------
                         slack                                  0.499    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.058ns  (arrival time - required time)
  Source:                 u_dut/u_core/r_exp_unbiased_reg[0][4]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][4]_srl18/D
                            (rising edge-triggered cell SRLC32E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.410     0.410    u_dut/u_core/clk
    SLICE_X3Y120         FDRE                                         r  u_dut/u_core/r_exp_unbiased_reg[0][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y120         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/u_core/r_exp_unbiased_reg[0][4]/Q
                         net (fo=1, routed)           0.056     0.607    u_dut/u_core/r_exp_unbiased_reg_n_0_[0][4]
    SLICE_X2Y120         SRLC32E                                      r  u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][4]_srl18/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.432     0.432    u_dut/u_core/clk
    SLICE_X2Y120         SRLC32E                                      r  u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][4]_srl18/CLK
                         clock pessimism              0.000     0.432    
    SLICE_X2Y120         SRLC32E (Hold_srlc32e_CLK_D)
                                                      0.117     0.549    u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][4]_srl18
  -------------------------------------------------------------------
                         required time                         -0.549    
                         arrival time                           0.607    
  -------------------------------------------------------------------
                         slack                                  0.058    

Slack (MET) :             0.058ns  (arrival time - required time)
  Source:                 u_dut/u_core/r_exp_unbiased_reg[0][4]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][4]_srl18/D
                            (rising edge-triggered cell SRLC32E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.410     0.410    u_dut/u_core/clk
    SLICE_X3Y120         FDRE                                         r  u_dut/u_core/r_exp_unbiased_reg[0][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y120         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/u_core/r_exp_unbiased_reg[0][4]/Q
                         net (fo=1, routed)           0.056     0.607    u_dut/u_core/r_exp_unbiased_reg_n_0_[0][4]
    SLICE_X2Y120         SRLC32E                                      f  u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][4]_srl18/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.432     0.432    u_dut/u_core/clk
    SLICE_X2Y120         SRLC32E                                      r  u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][4]_srl18/CLK
                         clock pessimism              0.000     0.432    
    SLICE_X2Y120         SRLC32E (Hold_srlc32e_CLK_D)
                                                      0.117     0.549    u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][4]_srl18
  -------------------------------------------------------------------
                         required time                         -0.549    
                         arrival time                           0.607    
  -------------------------------------------------------------------
                         slack                                  0.058    

Slack (MET) :             0.112ns  (arrival time - required time)
  Source:                 u_dut/u_core/r_den3_reg[0][28]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[1].r_den3_reg[1][28]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.209ns  (logic 0.141ns (67.454%)  route 0.068ns (32.546%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.410     0.410    u_dut/u_core/clk
    SLICE_X33Y116        FDRE                                         r  u_dut/u_core/r_den3_reg[0][28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y116        FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/u_core/r_den3_reg[0][28]/Q
                         net (fo=2, routed)           0.068     0.619    u_dut/u_core/r_den3_reg_n_0_[0][28]
    SLICE_X33Y116        FDRE                                         r  u_dut/u_core/g_stage[1].r_den3_reg[1][28]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.432     0.432    u_dut/u_core/clk
    SLICE_X33Y116        FDRE                                         r  u_dut/u_core/g_stage[1].r_den3_reg[1][28]/C
                         clock pessimism              0.000     0.432    
    SLICE_X33Y116        FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/u_core/g_stage[1].r_den3_reg[1][28]
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.619    
  -------------------------------------------------------------------
                         slack                                  0.112    

Slack (MET) :             0.112ns  (arrival time - required time)
  Source:                 u_dut/u_core/r_den3_reg[0][28]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[1].r_den3_reg[1][28]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.209ns  (logic 0.141ns (67.454%)  route 0.068ns (32.546%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.410     0.410    u_dut/u_core/clk
    SLICE_X33Y116        FDRE                                         r  u_dut/u_core/r_den3_reg[0][28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y116        FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/u_core/r_den3_reg[0][28]/Q
                         net (fo=2, routed)           0.068     0.619    u_dut/u_core/r_den3_reg_n_0_[0][28]
    SLICE_X33Y116        FDRE                                         f  u_dut/u_core/g_stage[1].r_den3_reg[1][28]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.432     0.432    u_dut/u_core/clk
    SLICE_X33Y116        FDRE                                         r  u_dut/u_core/g_stage[1].r_den3_reg[1][28]/C
                         clock pessimism              0.000     0.432    
    SLICE_X33Y116        FDRE (Hold_fdre_C_D)         0.075     0.507    u_dut/u_core/g_stage[1].r_den3_reg[1][28]
  -------------------------------------------------------------------
                         required time                         -0.507    
                         arrival time                           0.619    
  -------------------------------------------------------------------
                         slack                                  0.112    

Slack (MET) :             0.137ns  (arrival time - required time)
  Source:                 u_dut/u_core/g_stage[17].r_den3_reg[17][4]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[18].r_den3_reg[18][4]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.241ns  (logic 0.141ns (58.456%)  route 0.100ns (41.544%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.410     0.410    u_dut/u_core/clk
    SLICE_X7Y78          FDRE                                         r  u_dut/u_core/g_stage[17].r_den3_reg[17][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X7Y78          FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/u_core/g_stage[17].r_den3_reg[17][4]/Q
                         net (fo=2, routed)           0.100     0.651    u_dut/u_core/g_stage[17].r_den3_reg_n_0_[17][4]
    SLICE_X6Y78          FDRE                                         r  u_dut/u_core/g_stage[18].r_den3_reg[18][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.432     0.432    u_dut/u_core/clk
    SLICE_X6Y78          FDRE                                         r  u_dut/u_core/g_stage[18].r_den3_reg[18][4]/C
                         clock pessimism              0.000     0.432    
    SLICE_X6Y78          FDRE (Hold_fdre_C_D)         0.083     0.515    u_dut/u_core/g_stage[18].r_den3_reg[18][4]
  -------------------------------------------------------------------
                         required time                         -0.515    
                         arrival time                           0.651    
  -------------------------------------------------------------------
                         slack                                  0.137    

Slack (MET) :             0.137ns  (arrival time - required time)
  Source:                 u_dut/u_core/g_stage[17].r_den3_reg[17][4]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[18].r_den3_reg[18][4]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.241ns  (logic 0.141ns (58.456%)  route 0.100ns (41.544%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.410     0.410    u_dut/u_core/clk
    SLICE_X7Y78          FDRE                                         r  u_dut/u_core/g_stage[17].r_den3_reg[17][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X7Y78          FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/u_core/g_stage[17].r_den3_reg[17][4]/Q
                         net (fo=2, routed)           0.100     0.651    u_dut/u_core/g_stage[17].r_den3_reg_n_0_[17][4]
    SLICE_X6Y78          FDRE                                         f  u_dut/u_core/g_stage[18].r_den3_reg[18][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.432     0.432    u_dut/u_core/clk
    SLICE_X6Y78          FDRE                                         r  u_dut/u_core/g_stage[18].r_den3_reg[18][4]/C
                         clock pessimism              0.000     0.432    
    SLICE_X6Y78          FDRE (Hold_fdre_C_D)         0.083     0.515    u_dut/u_core/g_stage[18].r_den3_reg[18][4]
  -------------------------------------------------------------------
                         required time                         -0.515    
                         arrival time                           0.651    
  -------------------------------------------------------------------
                         slack                                  0.137    

Slack (MET) :             0.146ns  (arrival time - required time)
  Source:                 u_dut/u_core/g_stage[14].r_den_reg[14][1]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[15].r_den_reg[15][1]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.252ns  (logic 0.141ns (55.856%)  route 0.111ns (44.144%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.410     0.410    u_dut/u_core/clk
    SLICE_X15Y85         FDRE                                         r  u_dut/u_core/g_stage[14].r_den_reg[14][1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y85         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/u_core/g_stage[14].r_den_reg[14][1]/Q
                         net (fo=3, routed)           0.111     0.663    u_dut/u_core/g_stage[14].r_den_reg_n_0_[14][1]
    SLICE_X14Y85         FDRE                                         r  u_dut/u_core/g_stage[15].r_den_reg[15][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.432     0.432    u_dut/u_core/clk
    SLICE_X14Y85         FDRE                                         r  u_dut/u_core/g_stage[15].r_den_reg[15][1]/C
                         clock pessimism              0.000     0.432    
    SLICE_X14Y85         FDRE (Hold_fdre_C_D)         0.085     0.517    u_dut/u_core/g_stage[15].r_den_reg[15][1]
  -------------------------------------------------------------------
                         required time                         -0.517    
                         arrival time                           0.663    
  -------------------------------------------------------------------
                         slack                                  0.146    

Slack (MET) :             0.146ns  (arrival time - required time)
  Source:                 u_dut/u_core/g_stage[14].r_den_reg[14][1]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[15].r_den_reg[15][1]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.252ns  (logic 0.141ns (55.856%)  route 0.111ns (44.144%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.410     0.410    u_dut/u_core/clk
    SLICE_X15Y85         FDRE                                         r  u_dut/u_core/g_stage[14].r_den_reg[14][1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y85         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/u_core/g_stage[14].r_den_reg[14][1]/Q
                         net (fo=3, routed)           0.111     0.663    u_dut/u_core/g_stage[14].r_den_reg_n_0_[14][1]
    SLICE_X14Y85         FDRE                                         f  u_dut/u_core/g_stage[15].r_den_reg[15][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.432     0.432    u_dut/u_core/clk
    SLICE_X14Y85         FDRE                                         r  u_dut/u_core/g_stage[15].r_den_reg[15][1]/C
                         clock pessimism              0.000     0.432    
    SLICE_X14Y85         FDRE (Hold_fdre_C_D)         0.085     0.517    u_dut/u_core/g_stage[15].r_den_reg[15][1]
  -------------------------------------------------------------------
                         required time                         -0.517    
                         arrival time                           0.663    
  -------------------------------------------------------------------
                         slack                                  0.146    

Slack (MET) :             0.166ns  (arrival time - required time)
  Source:                 u_dut/u_core/r_den3_reg[0][34]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[1].r_den3_reg[1][34]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.263ns  (logic 0.141ns (53.571%)  route 0.122ns (46.429%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.410     0.410    u_dut/u_core/clk
    SLICE_X33Y117        FDRE                                         r  u_dut/u_core/r_den3_reg[0][34]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y117        FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/u_core/r_den3_reg[0][34]/Q
                         net (fo=2, routed)           0.122     0.673    u_dut/u_core/r_den3_reg_n_0_[0][34]
    SLICE_X33Y116        FDRE                                         r  u_dut/u_core/g_stage[1].r_den3_reg[1][34]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.432     0.432    u_dut/u_core/clk
    SLICE_X33Y116        FDRE                                         r  u_dut/u_core/g_stage[1].r_den3_reg[1][34]/C
                         clock pessimism              0.000     0.432    
    SLICE_X33Y116        FDRE (Hold_fdre_C_D)         0.076     0.508    u_dut/u_core/g_stage[1].r_den3_reg[1][34]
  -------------------------------------------------------------------
                         required time                         -0.508    
                         arrival time                           0.673    
  -------------------------------------------------------------------
                         slack                                  0.166    

Slack (MET) :             0.166ns  (arrival time - required time)
  Source:                 u_dut/u_core/r_den3_reg[0][34]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[1].r_den3_reg[1][34]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.263ns  (logic 0.141ns (53.571%)  route 0.122ns (46.429%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.410     0.410    u_dut/u_core/clk
    SLICE_X33Y117        FDRE                                         r  u_dut/u_core/r_den3_reg[0][34]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y117        FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/u_core/r_den3_reg[0][34]/Q
                         net (fo=2, routed)           0.122     0.673    u_dut/u_core/r_den3_reg_n_0_[0][34]
    SLICE_X33Y116        FDRE                                         f  u_dut/u_core/g_stage[1].r_den3_reg[1][34]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=2423, unset)         0.432     0.432    u_dut/u_core/clk
    SLICE_X33Y116        FDRE                                         r  u_dut/u_core/g_stage[1].r_den3_reg[1][34]/C
                         clock pessimism              0.000     0.432    
    SLICE_X33Y116        FDRE (Hold_fdre_C_D)         0.076     0.508    u_dut/u_core/g_stage[1].r_den3_reg[1][34]
  -------------------------------------------------------------------
                         required time                         -0.508    
                         arrival time                           0.673    
  -------------------------------------------------------------------
                         slack                                  0.166    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.667
Sources:            { clk }

Check Type        Corner  Lib Pin      Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X41Y112  a_r_reg[0]/C
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X41Y113  a_r_reg[10]/C
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X41Y113  a_r_reg[11]/C
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X41Y113  a_r_reg[12]/C
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X40Y113  a_r_reg[13]/C
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X41Y113  a_r_reg[14]/C
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X40Y113  a_r_reg[15]/C
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X41Y114  a_r_reg[16]/C
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X41Y114  a_r_reg[17]/C
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X41Y114  a_r_reg[18]/C
Low Pulse Width   Slow    SRLC32E/CLK  n/a            0.980         3.333       2.353      SLICE_X2Y118   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][0]_srl18/CLK
Low Pulse Width   Fast    SRLC32E/CLK  n/a            0.980         3.334       2.354      SLICE_X2Y118   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][0]_srl18/CLK
Low Pulse Width   Slow    SRLC32E/CLK  n/a            0.980         3.333       2.353      SLICE_X2Y118   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][1]_srl18/CLK
Low Pulse Width   Fast    SRLC32E/CLK  n/a            0.980         3.334       2.354      SLICE_X2Y118   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][1]_srl18/CLK
Low Pulse Width   Slow    SRLC32E/CLK  n/a            0.980         3.333       2.353      SLICE_X2Y116   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][2]_srl18/CLK
Low Pulse Width   Fast    SRLC32E/CLK  n/a            0.980         3.334       2.354      SLICE_X2Y116   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][2]_srl18/CLK
Low Pulse Width   Slow    SRLC32E/CLK  n/a            0.980         3.333       2.353      SLICE_X2Y118   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][3]_srl18/CLK
Low Pulse Width   Fast    SRLC32E/CLK  n/a            0.980         3.334       2.354      SLICE_X2Y118   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][3]_srl18/CLK
Low Pulse Width   Slow    SRLC32E/CLK  n/a            0.980         3.333       2.353      SLICE_X2Y120   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][4]_srl18/CLK
Low Pulse Width   Fast    SRLC32E/CLK  n/a            0.980         3.334       2.354      SLICE_X2Y120   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][4]_srl18/CLK
High Pulse Width  Slow    SRLC32E/CLK  n/a            0.980         3.334       2.354      SLICE_X2Y118   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][0]_srl18/CLK
High Pulse Width  Fast    SRLC32E/CLK  n/a            0.980         3.333       2.353      SLICE_X2Y118   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][0]_srl18/CLK
High Pulse Width  Slow    SRLC32E/CLK  n/a            0.980         3.334       2.354      SLICE_X2Y118   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][1]_srl18/CLK
High Pulse Width  Fast    SRLC32E/CLK  n/a            0.980         3.333       2.353      SLICE_X2Y118   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][1]_srl18/CLK
High Pulse Width  Slow    SRLC32E/CLK  n/a            0.980         3.334       2.354      SLICE_X2Y116   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][2]_srl18/CLK
High Pulse Width  Fast    SRLC32E/CLK  n/a            0.980         3.333       2.353      SLICE_X2Y116   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][2]_srl18/CLK
High Pulse Width  Slow    SRLC32E/CLK  n/a            0.980         3.334       2.354      SLICE_X2Y118   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][3]_srl18/CLK
High Pulse Width  Fast    SRLC32E/CLK  n/a            0.980         3.333       2.353      SLICE_X2Y118   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][3]_srl18/CLK
High Pulse Width  Slow    SRLC32E/CLK  n/a            0.980         3.334       2.354      SLICE_X2Y120   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][4]_srl18/CLK
High Pulse Width  Fast    SRLC32E/CLK  n/a            0.980         3.333       2.353      SLICE_X2Y120   u_dut/u_core/g_stage[18].r_exp_unbiased_reg[18][4]_srl18/CLK



