Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2025.2.1 (lin64) Build 6403652 Thu Mar 19 13:47:00 MDT 2026
| Date         : Sat May 23 22:42:16 2026
| Host         : deep-thought running 64-bit Manjaro Linux
| Command      : report_timing_summary -file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/zkf_div_w8_m18_base/timing_summary.rpt -max_paths 10 -nworst 10
| Design       : top_zkf_div_w8_m18_base
| Device       : 7s50-csga324
| Speed File   : -1  PRODUCTION 1.23 2018-06-13
| Design State : Routed
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (54)
6. checking no_output_delay (28)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (54)
-------------------------------
 There are 54 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (28)
--------------------------------
 There are 28 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      1.245        0.000                      0                  715        0.108        0.000                      0                  715        2.353        0.000                       0                   768  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock  Waveform(ns)         Period(ns)      Frequency(MHz)
-----  ------------         ----------      --------------
clk    {0.000 3.333}        6.667           149.993         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
clk                 1.245        0.000                      0                  715        0.108        0.000                      0                  715        2.353        0.000                       0                   768  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  clk
  To Clock:  clk

Setup :            0  Failing Endpoints,  Worst Slack        1.245ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.108ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.353ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.245ns  (required time - arrival time)
  Source:                 u_dut/u_core/r_den3_reg[0][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.286ns  (logic 2.338ns (44.229%)  route 2.948ns (55.771%))
  Logic Levels:           7  (CARRY4=5 LUT1=1 LUT3=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.973     0.973    u_dut/u_core/clk
    SLICE_X2Y93          FDRE                                         r  u_dut/u_core/r_den3_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X2Y93          FDRE (Prop_fdre_C_Q)         0.518     1.491 f  u_dut/u_core/r_den3_reg[0][0]/Q
                         net (fo=3, routed)           0.855     2.346    u_dut/u_core/g_stage[9].u_raw/i__i_1_0[0]
    SLICE_X4Y94          LUT1 (Prop_lut1_I0_O)        0.149     2.495 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4/O
                         net (fo=1, routed)           0.531     3.026    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4_n_0
    SLICE_X4Y95          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.788     3.814 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.814    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2_n_0
    SLICE_X4Y96          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.928 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.928    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2_n_0
    SLICE_X4Y97          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.042 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.042    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2_n_0
    SLICE_X4Y98          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.156 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.156    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2_n_0
    SLICE_X4Y99          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.228     4.384 r  u_dut/u_core/g_stage[9].u_raw/i__i_1/CO[2]
                         net (fo=19, routed)          0.831     5.215    u_dut/u_core/g_stage[1].u_raw/raw_next_reg[18][0]
    SLICE_X4Y93          LUT3 (Prop_lut3_I2_O)        0.313     5.528 r  u_dut/u_core/g_stage[1].u_raw/raw_next_reg/i_/O
                         net (fo=1, routed)           0.732     6.259    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[18]
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=767, unset)          0.924     7.591    u_dut/u_core/g_stage[9].u_raw/clk
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X10Y92         SRL16E (Setup_srl16e_CLK_D)
                                                     -0.052     7.504    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9
  -------------------------------------------------------------------
                         required time                          7.504    
                         arrival time                          -6.259    
  -------------------------------------------------------------------
                         slack                                  1.245    

Slack (MET) :             1.245ns  (required time - arrival time)
  Source:                 u_dut/u_core/r_den3_reg[0][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.286ns  (logic 2.338ns (44.229%)  route 2.948ns (55.771%))
  Logic Levels:           7  (CARRY4=5 LUT1=1 LUT3=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.973     0.973    u_dut/u_core/clk
    SLICE_X2Y93          FDRE                                         r  u_dut/u_core/r_den3_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X2Y93          FDRE (Prop_fdre_C_Q)         0.518     1.491 f  u_dut/u_core/r_den3_reg[0][0]/Q
                         net (fo=3, routed)           0.855     2.346    u_dut/u_core/g_stage[9].u_raw/i__i_1_0[0]
    SLICE_X4Y94          LUT1 (Prop_lut1_I0_O)        0.149     2.495 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4/O
                         net (fo=1, routed)           0.531     3.026    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4_n_0
    SLICE_X4Y95          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.788     3.814 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.814    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2_n_0
    SLICE_X4Y96          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.928 f  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.928    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2_n_0
    SLICE_X4Y97          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.042 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.042    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2_n_0
    SLICE_X4Y98          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.156 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.156    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2_n_0
    SLICE_X4Y99          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.228     4.384 r  u_dut/u_core/g_stage[9].u_raw/i__i_1/CO[2]
                         net (fo=19, routed)          0.831     5.215    u_dut/u_core/g_stage[1].u_raw/raw_next_reg[18][0]
    SLICE_X4Y93          LUT3 (Prop_lut3_I2_O)        0.313     5.528 r  u_dut/u_core/g_stage[1].u_raw/raw_next_reg/i_/O
                         net (fo=1, routed)           0.732     6.259    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[18]
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=767, unset)          0.924     7.591    u_dut/u_core/g_stage[9].u_raw/clk
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X10Y92         SRL16E (Setup_srl16e_CLK_D)
                                                     -0.052     7.504    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9
  -------------------------------------------------------------------
                         required time                          7.504    
                         arrival time                          -6.259    
  -------------------------------------------------------------------
                         slack                                  1.245    

Slack (MET) :             1.245ns  (required time - arrival time)
  Source:                 u_dut/u_core/r_den3_reg[0][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.286ns  (logic 2.338ns (44.229%)  route 2.948ns (55.771%))
  Logic Levels:           7  (CARRY4=5 LUT1=1 LUT3=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.973     0.973    u_dut/u_core/clk
    SLICE_X2Y93          FDRE                                         r  u_dut/u_core/r_den3_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X2Y93          FDRE (Prop_fdre_C_Q)         0.518     1.491 f  u_dut/u_core/r_den3_reg[0][0]/Q
                         net (fo=3, routed)           0.855     2.346    u_dut/u_core/g_stage[9].u_raw/i__i_1_0[0]
    SLICE_X4Y94          LUT1 (Prop_lut1_I0_O)        0.149     2.495 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4/O
                         net (fo=1, routed)           0.531     3.026    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4_n_0
    SLICE_X4Y95          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.788     3.814 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.814    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2_n_0
    SLICE_X4Y96          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.928 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.928    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2_n_0
    SLICE_X4Y97          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.042 f  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.042    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2_n_0
    SLICE_X4Y98          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.156 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.156    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2_n_0
    SLICE_X4Y99          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.228     4.384 r  u_dut/u_core/g_stage[9].u_raw/i__i_1/CO[2]
                         net (fo=19, routed)          0.831     5.215    u_dut/u_core/g_stage[1].u_raw/raw_next_reg[18][0]
    SLICE_X4Y93          LUT3 (Prop_lut3_I2_O)        0.313     5.528 r  u_dut/u_core/g_stage[1].u_raw/raw_next_reg/i_/O
                         net (fo=1, routed)           0.732     6.259    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[18]
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=767, unset)          0.924     7.591    u_dut/u_core/g_stage[9].u_raw/clk
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X10Y92         SRL16E (Setup_srl16e_CLK_D)
                                                     -0.052     7.504    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9
  -------------------------------------------------------------------
                         required time                          7.504    
                         arrival time                          -6.259    
  -------------------------------------------------------------------
                         slack                                  1.245    

Slack (MET) :             1.245ns  (required time - arrival time)
  Source:                 u_dut/u_core/r_den3_reg[0][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.286ns  (logic 2.338ns (44.229%)  route 2.948ns (55.771%))
  Logic Levels:           7  (CARRY4=5 LUT1=1 LUT3=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.973     0.973    u_dut/u_core/clk
    SLICE_X2Y93          FDRE                                         r  u_dut/u_core/r_den3_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X2Y93          FDRE (Prop_fdre_C_Q)         0.518     1.491 f  u_dut/u_core/r_den3_reg[0][0]/Q
                         net (fo=3, routed)           0.855     2.346    u_dut/u_core/g_stage[9].u_raw/i__i_1_0[0]
    SLICE_X4Y94          LUT1 (Prop_lut1_I0_O)        0.149     2.495 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4/O
                         net (fo=1, routed)           0.531     3.026    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4_n_0
    SLICE_X4Y95          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.788     3.814 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.814    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2_n_0
    SLICE_X4Y96          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.928 f  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.928    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2_n_0
    SLICE_X4Y97          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.042 f  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.042    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2_n_0
    SLICE_X4Y98          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.156 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.156    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2_n_0
    SLICE_X4Y99          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.228     4.384 r  u_dut/u_core/g_stage[9].u_raw/i__i_1/CO[2]
                         net (fo=19, routed)          0.831     5.215    u_dut/u_core/g_stage[1].u_raw/raw_next_reg[18][0]
    SLICE_X4Y93          LUT3 (Prop_lut3_I2_O)        0.313     5.528 r  u_dut/u_core/g_stage[1].u_raw/raw_next_reg/i_/O
                         net (fo=1, routed)           0.732     6.259    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[18]
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=767, unset)          0.924     7.591    u_dut/u_core/g_stage[9].u_raw/clk
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X10Y92         SRL16E (Setup_srl16e_CLK_D)
                                                     -0.052     7.504    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9
  -------------------------------------------------------------------
                         required time                          7.504    
                         arrival time                          -6.259    
  -------------------------------------------------------------------
                         slack                                  1.245    

Slack (MET) :             1.245ns  (required time - arrival time)
  Source:                 u_dut/u_core/r_den3_reg[0][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.286ns  (logic 2.338ns (44.229%)  route 2.948ns (55.771%))
  Logic Levels:           7  (CARRY4=5 LUT1=1 LUT3=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.973     0.973    u_dut/u_core/clk
    SLICE_X2Y93          FDRE                                         r  u_dut/u_core/r_den3_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X2Y93          FDRE (Prop_fdre_C_Q)         0.518     1.491 f  u_dut/u_core/r_den3_reg[0][0]/Q
                         net (fo=3, routed)           0.855     2.346    u_dut/u_core/g_stage[9].u_raw/i__i_1_0[0]
    SLICE_X4Y94          LUT1 (Prop_lut1_I0_O)        0.149     2.495 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4/O
                         net (fo=1, routed)           0.531     3.026    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4_n_0
    SLICE_X4Y95          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.788     3.814 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.814    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2_n_0
    SLICE_X4Y96          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.928 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.928    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2_n_0
    SLICE_X4Y97          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.042 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.042    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2_n_0
    SLICE_X4Y98          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.156 f  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.156    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2_n_0
    SLICE_X4Y99          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.228     4.384 r  u_dut/u_core/g_stage[9].u_raw/i__i_1/CO[2]
                         net (fo=19, routed)          0.831     5.215    u_dut/u_core/g_stage[1].u_raw/raw_next_reg[18][0]
    SLICE_X4Y93          LUT3 (Prop_lut3_I2_O)        0.313     5.528 r  u_dut/u_core/g_stage[1].u_raw/raw_next_reg/i_/O
                         net (fo=1, routed)           0.732     6.259    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[18]
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=767, unset)          0.924     7.591    u_dut/u_core/g_stage[9].u_raw/clk
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X10Y92         SRL16E (Setup_srl16e_CLK_D)
                                                     -0.052     7.504    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9
  -------------------------------------------------------------------
                         required time                          7.504    
                         arrival time                          -6.259    
  -------------------------------------------------------------------
                         slack                                  1.245    

Slack (MET) :             1.245ns  (required time - arrival time)
  Source:                 u_dut/u_core/r_den3_reg[0][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.286ns  (logic 2.338ns (44.229%)  route 2.948ns (55.771%))
  Logic Levels:           7  (CARRY4=5 LUT1=1 LUT3=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.973     0.973    u_dut/u_core/clk
    SLICE_X2Y93          FDRE                                         r  u_dut/u_core/r_den3_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X2Y93          FDRE (Prop_fdre_C_Q)         0.518     1.491 r  u_dut/u_core/r_den3_reg[0][0]/Q
                         net (fo=3, routed)           0.855     2.346    u_dut/u_core/g_stage[9].u_raw/i__i_1_0[0]
    SLICE_X4Y94          LUT1 (Prop_lut1_I0_O)        0.149     2.495 f  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4/O
                         net (fo=1, routed)           0.531     3.026    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4_n_0
    SLICE_X4Y95          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.788     3.814 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.814    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2_n_0
    SLICE_X4Y96          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.928 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.928    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2_n_0
    SLICE_X4Y97          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.042 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.042    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2_n_0
    SLICE_X4Y98          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.156 f  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.156    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2_n_0
    SLICE_X4Y99          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.228     4.384 r  u_dut/u_core/g_stage[9].u_raw/i__i_1/CO[2]
                         net (fo=19, routed)          0.831     5.215    u_dut/u_core/g_stage[1].u_raw/raw_next_reg[18][0]
    SLICE_X4Y93          LUT3 (Prop_lut3_I2_O)        0.313     5.528 r  u_dut/u_core/g_stage[1].u_raw/raw_next_reg/i_/O
                         net (fo=1, routed)           0.732     6.259    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[18]
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=767, unset)          0.924     7.591    u_dut/u_core/g_stage[9].u_raw/clk
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X10Y92         SRL16E (Setup_srl16e_CLK_D)
                                                     -0.052     7.504    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9
  -------------------------------------------------------------------
                         required time                          7.504    
                         arrival time                          -6.259    
  -------------------------------------------------------------------
                         slack                                  1.245    

Slack (MET) :             1.245ns  (required time - arrival time)
  Source:                 u_dut/u_core/r_den3_reg[0][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.286ns  (logic 2.338ns (44.229%)  route 2.948ns (55.771%))
  Logic Levels:           7  (CARRY4=5 LUT1=1 LUT3=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.973     0.973    u_dut/u_core/clk
    SLICE_X2Y93          FDRE                                         r  u_dut/u_core/r_den3_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X2Y93          FDRE (Prop_fdre_C_Q)         0.518     1.491 f  u_dut/u_core/r_den3_reg[0][0]/Q
                         net (fo=3, routed)           0.855     2.346    u_dut/u_core/g_stage[9].u_raw/i__i_1_0[0]
    SLICE_X4Y94          LUT1 (Prop_lut1_I0_O)        0.149     2.495 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4/O
                         net (fo=1, routed)           0.531     3.026    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4_n_0
    SLICE_X4Y95          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.788     3.814 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.814    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2_n_0
    SLICE_X4Y96          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.928 f  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.928    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2_n_0
    SLICE_X4Y97          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.042 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.042    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2_n_0
    SLICE_X4Y98          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.156 f  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.156    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2_n_0
    SLICE_X4Y99          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.228     4.384 r  u_dut/u_core/g_stage[9].u_raw/i__i_1/CO[2]
                         net (fo=19, routed)          0.831     5.215    u_dut/u_core/g_stage[1].u_raw/raw_next_reg[18][0]
    SLICE_X4Y93          LUT3 (Prop_lut3_I2_O)        0.313     5.528 r  u_dut/u_core/g_stage[1].u_raw/raw_next_reg/i_/O
                         net (fo=1, routed)           0.732     6.259    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[18]
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=767, unset)          0.924     7.591    u_dut/u_core/g_stage[9].u_raw/clk
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X10Y92         SRL16E (Setup_srl16e_CLK_D)
                                                     -0.052     7.504    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9
  -------------------------------------------------------------------
                         required time                          7.504    
                         arrival time                          -6.259    
  -------------------------------------------------------------------
                         slack                                  1.245    

Slack (MET) :             1.245ns  (required time - arrival time)
  Source:                 u_dut/u_core/r_den3_reg[0][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.286ns  (logic 2.338ns (44.229%)  route 2.948ns (55.771%))
  Logic Levels:           7  (CARRY4=5 LUT1=1 LUT3=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.973     0.973    u_dut/u_core/clk
    SLICE_X2Y93          FDRE                                         r  u_dut/u_core/r_den3_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X2Y93          FDRE (Prop_fdre_C_Q)         0.518     1.491 r  u_dut/u_core/r_den3_reg[0][0]/Q
                         net (fo=3, routed)           0.855     2.346    u_dut/u_core/g_stage[9].u_raw/i__i_1_0[0]
    SLICE_X4Y94          LUT1 (Prop_lut1_I0_O)        0.149     2.495 f  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4/O
                         net (fo=1, routed)           0.531     3.026    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4_n_0
    SLICE_X4Y95          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.788     3.814 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.814    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2_n_0
    SLICE_X4Y96          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.928 f  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.928    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2_n_0
    SLICE_X4Y97          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.042 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.042    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2_n_0
    SLICE_X4Y98          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.156 f  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.156    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2_n_0
    SLICE_X4Y99          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.228     4.384 r  u_dut/u_core/g_stage[9].u_raw/i__i_1/CO[2]
                         net (fo=19, routed)          0.831     5.215    u_dut/u_core/g_stage[1].u_raw/raw_next_reg[18][0]
    SLICE_X4Y93          LUT3 (Prop_lut3_I2_O)        0.313     5.528 r  u_dut/u_core/g_stage[1].u_raw/raw_next_reg/i_/O
                         net (fo=1, routed)           0.732     6.259    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[18]
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=767, unset)          0.924     7.591    u_dut/u_core/g_stage[9].u_raw/clk
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X10Y92         SRL16E (Setup_srl16e_CLK_D)
                                                     -0.052     7.504    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9
  -------------------------------------------------------------------
                         required time                          7.504    
                         arrival time                          -6.259    
  -------------------------------------------------------------------
                         slack                                  1.245    

Slack (MET) :             1.245ns  (required time - arrival time)
  Source:                 u_dut/u_core/r_den3_reg[0][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.286ns  (logic 2.338ns (44.229%)  route 2.948ns (55.771%))
  Logic Levels:           7  (CARRY4=5 LUT1=1 LUT3=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.973     0.973    u_dut/u_core/clk
    SLICE_X2Y93          FDRE                                         r  u_dut/u_core/r_den3_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X2Y93          FDRE (Prop_fdre_C_Q)         0.518     1.491 f  u_dut/u_core/r_den3_reg[0][0]/Q
                         net (fo=3, routed)           0.855     2.346    u_dut/u_core/g_stage[9].u_raw/i__i_1_0[0]
    SLICE_X4Y94          LUT1 (Prop_lut1_I0_O)        0.149     2.495 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4/O
                         net (fo=1, routed)           0.531     3.026    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4_n_0
    SLICE_X4Y95          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.788     3.814 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.814    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2_n_0
    SLICE_X4Y96          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.928 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.928    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2_n_0
    SLICE_X4Y97          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.042 f  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.042    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2_n_0
    SLICE_X4Y98          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.156 f  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.156    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2_n_0
    SLICE_X4Y99          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.228     4.384 r  u_dut/u_core/g_stage[9].u_raw/i__i_1/CO[2]
                         net (fo=19, routed)          0.831     5.215    u_dut/u_core/g_stage[1].u_raw/raw_next_reg[18][0]
    SLICE_X4Y93          LUT3 (Prop_lut3_I2_O)        0.313     5.528 r  u_dut/u_core/g_stage[1].u_raw/raw_next_reg/i_/O
                         net (fo=1, routed)           0.732     6.259    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[18]
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=767, unset)          0.924     7.591    u_dut/u_core/g_stage[9].u_raw/clk
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X10Y92         SRL16E (Setup_srl16e_CLK_D)
                                                     -0.052     7.504    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9
  -------------------------------------------------------------------
                         required time                          7.504    
                         arrival time                          -6.259    
  -------------------------------------------------------------------
                         slack                                  1.245    

Slack (MET) :             1.245ns  (required time - arrival time)
  Source:                 u_dut/u_core/r_den3_reg[0][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.286ns  (logic 2.338ns (44.229%)  route 2.948ns (55.771%))
  Logic Levels:           7  (CARRY4=5 LUT1=1 LUT3=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.973     0.973    u_dut/u_core/clk
    SLICE_X2Y93          FDRE                                         r  u_dut/u_core/r_den3_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X2Y93          FDRE (Prop_fdre_C_Q)         0.518     1.491 f  u_dut/u_core/r_den3_reg[0][0]/Q
                         net (fo=3, routed)           0.855     2.346    u_dut/u_core/g_stage[9].u_raw/i__i_1_0[0]
    SLICE_X4Y94          LUT1 (Prop_lut1_I0_O)        0.149     2.495 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4/O
                         net (fo=1, routed)           0.531     3.026    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem[1][4]_i_4_n_0
    SLICE_X4Y95          CARRY4 (Prop_carry4_CYINIT_CO[3])
                                                      0.788     3.814 r  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.814    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][4]_i_2_n_0
    SLICE_X4Y96          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.928 f  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2/CO[3]
                         net (fo=1, routed)           0.000     3.928    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][8]_i_2_n_0
    SLICE_X4Y97          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.042 f  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.042    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][12]_i_2_n_0
    SLICE_X4Y98          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.156 f  u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.156    u_dut/u_core/g_stage[9].u_raw/g_stage[1].r_rem_reg[1][16]_i_2_n_0
    SLICE_X4Y99          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.228     4.384 r  u_dut/u_core/g_stage[9].u_raw/i__i_1/CO[2]
                         net (fo=19, routed)          0.831     5.215    u_dut/u_core/g_stage[1].u_raw/raw_next_reg[18][0]
    SLICE_X4Y93          LUT3 (Prop_lut3_I2_O)        0.313     5.528 r  u_dut/u_core/g_stage[1].u_raw/raw_next_reg/i_/O
                         net (fo=1, routed)           0.732     6.259    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[18]
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=767, unset)          0.924     7.591    u_dut/u_core/g_stage[9].u_raw/clk
    SLICE_X10Y92         SRL16E                                       r  u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X10Y92         SRL16E (Setup_srl16e_CLK_D)
                                                     -0.052     7.504    u_dut/u_core/g_stage[9].u_raw/raw_next_reg[16]_srl9
  -------------------------------------------------------------------
                         required time                          7.504    
                         arrival time                          -6.259    
  -------------------------------------------------------------------
                         slack                                  1.245    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.108ns  (arrival time - required time)
  Source:                 u_dut/u_core/r_exp_unbiased_reg[0][7]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][7]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.312ns  (logic 0.141ns (45.172%)  route 0.171ns (54.828%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.410     0.410    u_dut/u_core/clk
    SLICE_X15Y95         FDRE                                         r  u_dut/u_core/r_exp_unbiased_reg[0][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y95         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/u_core/r_exp_unbiased_reg[0][7]/Q
                         net (fo=1, routed)           0.171     0.722    u_dut/u_core/r_exp_unbiased_reg_n_0_[0][7]
    SLICE_X14Y94         SRL16E                                       r  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][7]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.432     0.432    u_dut/u_core/clk
    SLICE_X14Y94         SRL16E                                       r  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][7]_srl9/CLK
                         clock pessimism              0.000     0.432    
    SLICE_X14Y94         SRL16E (Hold_srl16e_CLK_D)
                                                      0.183     0.615    u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][7]_srl9
  -------------------------------------------------------------------
                         required time                         -0.615    
                         arrival time                           0.722    
  -------------------------------------------------------------------
                         slack                                  0.108    

Slack (MET) :             0.108ns  (arrival time - required time)
  Source:                 u_dut/u_core/r_exp_unbiased_reg[0][7]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][7]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.312ns  (logic 0.141ns (45.172%)  route 0.171ns (54.828%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.410     0.410    u_dut/u_core/clk
    SLICE_X15Y95         FDRE                                         r  u_dut/u_core/r_exp_unbiased_reg[0][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y95         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/u_core/r_exp_unbiased_reg[0][7]/Q
                         net (fo=1, routed)           0.171     0.722    u_dut/u_core/r_exp_unbiased_reg_n_0_[0][7]
    SLICE_X14Y94         SRL16E                                       f  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][7]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.432     0.432    u_dut/u_core/clk
    SLICE_X14Y94         SRL16E                                       r  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][7]_srl9/CLK
                         clock pessimism              0.000     0.432    
    SLICE_X14Y94         SRL16E (Hold_srl16e_CLK_D)
                                                      0.183     0.615    u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][7]_srl9
  -------------------------------------------------------------------
                         required time                         -0.615    
                         arrival time                           0.722    
  -------------------------------------------------------------------
                         slack                                  0.108    

Slack (MET) :             0.112ns  (arrival time - required time)
  Source:                 u_dut/u_core/r_exp_unbiased_reg[0][4]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][4]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.251ns  (logic 0.141ns (56.174%)  route 0.110ns (43.826%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.410     0.410    u_dut/u_core/clk
    SLICE_X15Y95         FDRE                                         r  u_dut/u_core/r_exp_unbiased_reg[0][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y95         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/u_core/r_exp_unbiased_reg[0][4]/Q
                         net (fo=1, routed)           0.110     0.661    u_dut/u_core/r_exp_unbiased_reg_n_0_[0][4]
    SLICE_X14Y94         SRL16E                                       r  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][4]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.432     0.432    u_dut/u_core/clk
    SLICE_X14Y94         SRL16E                                       r  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][4]_srl9/CLK
                         clock pessimism              0.000     0.432    
    SLICE_X14Y94         SRL16E (Hold_srl16e_CLK_D)
                                                      0.117     0.549    u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][4]_srl9
  -------------------------------------------------------------------
                         required time                         -0.549    
                         arrival time                           0.661    
  -------------------------------------------------------------------
                         slack                                  0.112    

Slack (MET) :             0.112ns  (arrival time - required time)
  Source:                 u_dut/u_core/r_exp_unbiased_reg[0][4]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][4]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.251ns  (logic 0.141ns (56.174%)  route 0.110ns (43.826%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.410     0.410    u_dut/u_core/clk
    SLICE_X15Y95         FDRE                                         r  u_dut/u_core/r_exp_unbiased_reg[0][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y95         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/u_core/r_exp_unbiased_reg[0][4]/Q
                         net (fo=1, routed)           0.110     0.661    u_dut/u_core/r_exp_unbiased_reg_n_0_[0][4]
    SLICE_X14Y94         SRL16E                                       f  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][4]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.432     0.432    u_dut/u_core/clk
    SLICE_X14Y94         SRL16E                                       r  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][4]_srl9/CLK
                         clock pessimism              0.000     0.432    
    SLICE_X14Y94         SRL16E (Hold_srl16e_CLK_D)
                                                      0.117     0.549    u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][4]_srl9
  -------------------------------------------------------------------
                         required time                         -0.549    
                         arrival time                           0.661    
  -------------------------------------------------------------------
                         slack                                  0.112    

Slack (MET) :             0.114ns  (arrival time - required time)
  Source:                 u_dut/u_core/r_exp_unbiased_reg[0][5]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][5]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.251ns  (logic 0.141ns (56.174%)  route 0.110ns (43.826%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.410     0.410    u_dut/u_core/clk
    SLICE_X15Y95         FDRE                                         r  u_dut/u_core/r_exp_unbiased_reg[0][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y95         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/u_core/r_exp_unbiased_reg[0][5]/Q
                         net (fo=1, routed)           0.110     0.661    u_dut/u_core/r_exp_unbiased_reg_n_0_[0][5]
    SLICE_X14Y94         SRL16E                                       r  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][5]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.432     0.432    u_dut/u_core/clk
    SLICE_X14Y94         SRL16E                                       r  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][5]_srl9/CLK
                         clock pessimism              0.000     0.432    
    SLICE_X14Y94         SRL16E (Hold_srl16e_CLK_D)
                                                      0.115     0.547    u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][5]_srl9
  -------------------------------------------------------------------
                         required time                         -0.547    
                         arrival time                           0.661    
  -------------------------------------------------------------------
                         slack                                  0.114    

Slack (MET) :             0.114ns  (arrival time - required time)
  Source:                 u_dut/u_core/r_exp_unbiased_reg[0][5]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][5]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.251ns  (logic 0.141ns (56.174%)  route 0.110ns (43.826%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.410     0.410    u_dut/u_core/clk
    SLICE_X15Y95         FDRE                                         r  u_dut/u_core/r_exp_unbiased_reg[0][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y95         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/u_core/r_exp_unbiased_reg[0][5]/Q
                         net (fo=1, routed)           0.110     0.661    u_dut/u_core/r_exp_unbiased_reg_n_0_[0][5]
    SLICE_X14Y94         SRL16E                                       f  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][5]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.432     0.432    u_dut/u_core/clk
    SLICE_X14Y94         SRL16E                                       r  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][5]_srl9/CLK
                         clock pessimism              0.000     0.432    
    SLICE_X14Y94         SRL16E (Hold_srl16e_CLK_D)
                                                      0.115     0.547    u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][5]_srl9
  -------------------------------------------------------------------
                         required time                         -0.547    
                         arrival time                           0.661    
  -------------------------------------------------------------------
                         slack                                  0.114    

Slack (MET) :             0.120ns  (arrival time - required time)
  Source:                 u_dut/u_core/r_exp_unbiased_reg[0][6]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][6]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.251ns  (logic 0.141ns (56.174%)  route 0.110ns (43.826%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.410     0.410    u_dut/u_core/clk
    SLICE_X15Y95         FDRE                                         r  u_dut/u_core/r_exp_unbiased_reg[0][6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y95         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/u_core/r_exp_unbiased_reg[0][6]/Q
                         net (fo=1, routed)           0.110     0.661    u_dut/u_core/r_exp_unbiased_reg_n_0_[0][6]
    SLICE_X14Y94         SRL16E                                       r  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][6]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.432     0.432    u_dut/u_core/clk
    SLICE_X14Y94         SRL16E                                       r  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][6]_srl9/CLK
                         clock pessimism              0.000     0.432    
    SLICE_X14Y94         SRL16E (Hold_srl16e_CLK_D)
                                                      0.109     0.541    u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][6]_srl9
  -------------------------------------------------------------------
                         required time                         -0.541    
                         arrival time                           0.661    
  -------------------------------------------------------------------
                         slack                                  0.120    

Slack (MET) :             0.120ns  (arrival time - required time)
  Source:                 u_dut/u_core/r_exp_unbiased_reg[0][6]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][6]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.251ns  (logic 0.141ns (56.174%)  route 0.110ns (43.826%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.410     0.410    u_dut/u_core/clk
    SLICE_X15Y95         FDRE                                         r  u_dut/u_core/r_exp_unbiased_reg[0][6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y95         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/u_core/r_exp_unbiased_reg[0][6]/Q
                         net (fo=1, routed)           0.110     0.661    u_dut/u_core/r_exp_unbiased_reg_n_0_[0][6]
    SLICE_X14Y94         SRL16E                                       f  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][6]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.432     0.432    u_dut/u_core/clk
    SLICE_X14Y94         SRL16E                                       r  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][6]_srl9/CLK
                         clock pessimism              0.000     0.432    
    SLICE_X14Y94         SRL16E (Hold_srl16e_CLK_D)
                                                      0.109     0.541    u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][6]_srl9
  -------------------------------------------------------------------
                         required time                         -0.541    
                         arrival time                           0.661    
  -------------------------------------------------------------------
                         slack                                  0.120    

Slack (MET) :             0.134ns  (arrival time - required time)
  Source:                 u_dut/u_core/r_exp_unbiased_reg[0][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][0]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.257ns  (logic 0.141ns (54.828%)  route 0.116ns (45.172%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.410     0.410    u_dut/u_core/clk
    SLICE_X15Y94         FDRE                                         r  u_dut/u_core/r_exp_unbiased_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y94         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/u_core/r_exp_unbiased_reg[0][0]/Q
                         net (fo=1, routed)           0.116     0.667    u_dut/u_core/r_exp_unbiased_reg_n_0_[0][0]
    SLICE_X14Y94         SRL16E                                       r  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][0]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.432     0.432    u_dut/u_core/clk
    SLICE_X14Y94         SRL16E                                       r  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][0]_srl9/CLK
                         clock pessimism              0.000     0.432    
    SLICE_X14Y94         SRL16E (Hold_srl16e_CLK_D)
                                                      0.102     0.534    u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][0]_srl9
  -------------------------------------------------------------------
                         required time                         -0.534    
                         arrival time                           0.667    
  -------------------------------------------------------------------
                         slack                                  0.134    

Slack (MET) :             0.134ns  (arrival time - required time)
  Source:                 u_dut/u_core/r_exp_unbiased_reg[0][0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][0]_srl9/D
                            (rising edge-triggered cell SRL16E clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.257ns  (logic 0.141ns (54.828%)  route 0.116ns (45.172%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.410     0.410    u_dut/u_core/clk
    SLICE_X15Y94         FDRE                                         r  u_dut/u_core/r_exp_unbiased_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y94         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/u_core/r_exp_unbiased_reg[0][0]/Q
                         net (fo=1, routed)           0.116     0.667    u_dut/u_core/r_exp_unbiased_reg_n_0_[0][0]
    SLICE_X14Y94         SRL16E                                       f  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][0]_srl9/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=767, unset)          0.432     0.432    u_dut/u_core/clk
    SLICE_X14Y94         SRL16E                                       r  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][0]_srl9/CLK
                         clock pessimism              0.000     0.432    
    SLICE_X14Y94         SRL16E (Hold_srl16e_CLK_D)
                                                      0.102     0.534    u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][0]_srl9
  -------------------------------------------------------------------
                         required time                         -0.534    
                         arrival time                           0.667    
  -------------------------------------------------------------------
                         slack                                  0.134    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.667
Sources:            { clk }

Check Type        Corner  Lib Pin     Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X1Y98   a_r_reg[0]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X3Y99   a_r_reg[10]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X2Y99   a_r_reg[11]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X1Y99   a_r_reg[12]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X1Y99   a_r_reg[13]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X1Y99   a_r_reg[14]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X2Y99   a_r_reg[15]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X3Y100  a_r_reg[16]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X13Y94  a_r_reg[17]/C
Min Period        n/a     FDRE/C      n/a            1.000         6.667       5.667      SLICE_X13Y94  a_r_reg[18]/C
Low Pulse Width   Slow    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X10Y99  u_dut/u_core/g_stage[10].r_div0_reg[10]_srl11/CLK
Low Pulse Width   Fast    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X10Y99  u_dut/u_core/g_stage[10].r_div0_reg[10]_srl11/CLK
Low Pulse Width   Slow    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X14Y95  u_dut/u_core/g_stage[10].r_force_inf_reg[10]_srl11/CLK
Low Pulse Width   Fast    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X14Y95  u_dut/u_core/g_stage[10].r_force_inf_reg[10]_srl11/CLK
Low Pulse Width   Slow    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X14Y95  u_dut/u_core/g_stage[10].r_force_zero_reg[10]_srl11/CLK
Low Pulse Width   Fast    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X14Y95  u_dut/u_core/g_stage[10].r_force_zero_reg[10]_srl11/CLK
Low Pulse Width   Slow    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X10Y99  u_dut/u_core/g_stage[10].r_sign_reg[10]_srl11/CLK
Low Pulse Width   Fast    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X10Y99  u_dut/u_core/g_stage[10].r_sign_reg[10]_srl11/CLK
Low Pulse Width   Slow    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X14Y94  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][0]_srl9/CLK
Low Pulse Width   Fast    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X14Y94  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][0]_srl9/CLK
High Pulse Width  Slow    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X10Y99  u_dut/u_core/g_stage[10].r_div0_reg[10]_srl11/CLK
High Pulse Width  Fast    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X10Y99  u_dut/u_core/g_stage[10].r_div0_reg[10]_srl11/CLK
High Pulse Width  Slow    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X14Y95  u_dut/u_core/g_stage[10].r_force_inf_reg[10]_srl11/CLK
High Pulse Width  Fast    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X14Y95  u_dut/u_core/g_stage[10].r_force_inf_reg[10]_srl11/CLK
High Pulse Width  Slow    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X14Y95  u_dut/u_core/g_stage[10].r_force_zero_reg[10]_srl11/CLK
High Pulse Width  Fast    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X14Y95  u_dut/u_core/g_stage[10].r_force_zero_reg[10]_srl11/CLK
High Pulse Width  Slow    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X10Y99  u_dut/u_core/g_stage[10].r_sign_reg[10]_srl11/CLK
High Pulse Width  Fast    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X10Y99  u_dut/u_core/g_stage[10].r_sign_reg[10]_srl11/CLK
High Pulse Width  Slow    SRL16E/CLK  n/a            0.980         3.334       2.354      SLICE_X14Y94  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][0]_srl9/CLK
High Pulse Width  Fast    SRL16E/CLK  n/a            0.980         3.333       2.353      SLICE_X14Y94  u_dut/u_core/g_stage[9].r_exp_unbiased_reg[9][0]_srl9/CLK



