Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2025.2.1 (lin64) Build 6403652 Thu Mar 19 13:47:00 MDT 2026
| Date         : Sat May 23 22:41:48 2026
| Host         : deep-thought running 64-bit Manjaro Linux
| Command      : report_timing_summary -file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/zkf_mul_w8_m18_base/timing_summary.rpt -max_paths 10 -nworst 10
| Design       : top_zkf_mul_w8_m18_base
| Device       : 7s50-csga324
| Speed File   : -1  PRODUCTION 1.23 2018-06-13
| Design State : Routed
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (54)
6. checking no_output_delay (27)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (54)
-------------------------------
 There are 54 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (27)
--------------------------------
 There are 27 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.907        0.000                      0                   92        0.164        0.000                      0                   92        2.833        0.000                       0                    95  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock  Waveform(ns)         Period(ns)      Frequency(MHz)
-----  ------------         ----------      --------------
clk    {0.000 3.333}        6.667           149.993         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
clk                 0.907        0.000                      0                   92        0.164        0.000                      0                   92        2.833        0.000                       0                    95  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  clk
  To Clock:  clk

Setup :            0  Failing Endpoints,  Worst Slack        0.907ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.164ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.833ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.907ns  (required time - arrival time)
  Source:                 u_dut/s1_mag_reg/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.705ns  (logic 2.575ns (45.137%)  route 3.130ns (54.863%))
  Logic Levels:           10  (CARRY4=5 LUT3=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.973     0.973    u_dut/clk
    DSP48_X0Y28          DSP48E1                                      r  u_dut/s1_mag_reg/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X0Y28          DSP48E1 (Prop_dsp48e1_CLK_P[17])
                                                      0.434     1.407 r  u_dut/s1_mag_reg/P[17]
                         net (fo=4, routed)           0.980     2.387    u_dut/s1_guard_hi
    SLICE_X12Y72         LUT3 (Prop_lut3_I0_O)        0.150     2.537 r  u_dut/y[3]_INST_0_i_10/O
                         net (fo=3, routed)           0.600     3.136    u_dut/y[3]_INST_0_i_10_n_0
    SLICE_X12Y70         LUT6 (Prop_lut6_I4_O)        0.328     3.464 r  u_dut/y[3]_INST_0_i_9/O
                         net (fo=1, routed)           0.568     4.032    u_dut/y[3]_INST_0_i_9_n_0
    SLICE_X11Y71         LUT6 (Prop_lut6_I5_O)        0.124     4.156 r  u_dut/y[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     4.156    u_dut/y[3]_INST_0_i_6_n_0
    SLICE_X11Y71         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     4.688 r  u_dut/y[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.688    u_dut/y[3]_INST_0_i_1_n_0
    SLICE_X11Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.802 r  u_dut/y[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.802    u_dut/y[7]_INST_0_i_1_n_0
    SLICE_X11Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.916 r  u_dut/y[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.916    u_dut/y[11]_INST_0_i_1_n_0
    SLICE_X11Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     5.030 r  u_dut/y[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     5.039    u_dut/y[15]_INST_0_i_1_n_0
    SLICE_X11Y75         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     5.278 r  u_dut/y[18]_INST_0_i_1/O[2]
                         net (fo=2, routed)           0.489     5.767    u_dut/y[18]_INST_0_i_1_n_5
    SLICE_X9Y74          LUT5 (Prop_lut5_I0_O)        0.302     6.069 r  u_dut/y[17]_INST_0_i_2/O
                         net (fo=1, routed)           0.485     6.554    u_dut/y[17]_INST_0_i_2_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     6.678 r  u_dut/y[17]_INST_0/O
                         net (fo=1, routed)           0.000     6.678    dut_y[17]
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=94, unset)           0.924     7.591    clk
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X9Y74          FDRE (Setup_fdre_C_D)        0.029     7.585    y_r_reg[17]
  -------------------------------------------------------------------
                         required time                          7.585    
                         arrival time                          -6.678    
  -------------------------------------------------------------------
                         slack                                  0.907    

Slack (MET) :             0.907ns  (required time - arrival time)
  Source:                 u_dut/s1_mag_reg/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.705ns  (logic 2.575ns (45.137%)  route 3.130ns (54.863%))
  Logic Levels:           10  (CARRY4=5 LUT3=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.973     0.973    u_dut/clk
    DSP48_X0Y28          DSP48E1                                      r  u_dut/s1_mag_reg/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X0Y28          DSP48E1 (Prop_dsp48e1_CLK_P[17])
                                                      0.434     1.407 r  u_dut/s1_mag_reg/P[17]
                         net (fo=4, routed)           0.980     2.387    u_dut/s1_guard_hi
    SLICE_X12Y72         LUT3 (Prop_lut3_I0_O)        0.150     2.537 r  u_dut/y[3]_INST_0_i_10/O
                         net (fo=3, routed)           0.600     3.136    u_dut/y[3]_INST_0_i_10_n_0
    SLICE_X12Y70         LUT6 (Prop_lut6_I4_O)        0.328     3.464 r  u_dut/y[3]_INST_0_i_9/O
                         net (fo=1, routed)           0.568     4.032    u_dut/y[3]_INST_0_i_9_n_0
    SLICE_X11Y71         LUT6 (Prop_lut6_I5_O)        0.124     4.156 r  u_dut/y[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     4.156    u_dut/y[3]_INST_0_i_6_n_0
    SLICE_X11Y71         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     4.688 r  u_dut/y[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.688    u_dut/y[3]_INST_0_i_1_n_0
    SLICE_X11Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.802 f  u_dut/y[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.802    u_dut/y[7]_INST_0_i_1_n_0
    SLICE_X11Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.916 r  u_dut/y[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.916    u_dut/y[11]_INST_0_i_1_n_0
    SLICE_X11Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     5.030 r  u_dut/y[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     5.039    u_dut/y[15]_INST_0_i_1_n_0
    SLICE_X11Y75         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     5.278 r  u_dut/y[18]_INST_0_i_1/O[2]
                         net (fo=2, routed)           0.489     5.767    u_dut/y[18]_INST_0_i_1_n_5
    SLICE_X9Y74          LUT5 (Prop_lut5_I0_O)        0.302     6.069 r  u_dut/y[17]_INST_0_i_2/O
                         net (fo=1, routed)           0.485     6.554    u_dut/y[17]_INST_0_i_2_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     6.678 r  u_dut/y[17]_INST_0/O
                         net (fo=1, routed)           0.000     6.678    dut_y[17]
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=94, unset)           0.924     7.591    clk
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X9Y74          FDRE (Setup_fdre_C_D)        0.029     7.585    y_r_reg[17]
  -------------------------------------------------------------------
                         required time                          7.585    
                         arrival time                          -6.678    
  -------------------------------------------------------------------
                         slack                                  0.907    

Slack (MET) :             0.907ns  (required time - arrival time)
  Source:                 u_dut/s1_mag_reg/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.705ns  (logic 2.575ns (45.137%)  route 3.130ns (54.863%))
  Logic Levels:           10  (CARRY4=5 LUT3=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.973     0.973    u_dut/clk
    DSP48_X0Y28          DSP48E1                                      r  u_dut/s1_mag_reg/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X0Y28          DSP48E1 (Prop_dsp48e1_CLK_P[17])
                                                      0.434     1.407 r  u_dut/s1_mag_reg/P[17]
                         net (fo=4, routed)           0.980     2.387    u_dut/s1_guard_hi
    SLICE_X12Y72         LUT3 (Prop_lut3_I0_O)        0.150     2.537 r  u_dut/y[3]_INST_0_i_10/O
                         net (fo=3, routed)           0.600     3.136    u_dut/y[3]_INST_0_i_10_n_0
    SLICE_X12Y70         LUT6 (Prop_lut6_I4_O)        0.328     3.464 r  u_dut/y[3]_INST_0_i_9/O
                         net (fo=1, routed)           0.568     4.032    u_dut/y[3]_INST_0_i_9_n_0
    SLICE_X11Y71         LUT6 (Prop_lut6_I5_O)        0.124     4.156 f  u_dut/y[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     4.156    u_dut/y[3]_INST_0_i_6_n_0
    SLICE_X11Y71         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     4.688 r  u_dut/y[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.688    u_dut/y[3]_INST_0_i_1_n_0
    SLICE_X11Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.802 f  u_dut/y[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.802    u_dut/y[7]_INST_0_i_1_n_0
    SLICE_X11Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.916 r  u_dut/y[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.916    u_dut/y[11]_INST_0_i_1_n_0
    SLICE_X11Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     5.030 r  u_dut/y[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     5.039    u_dut/y[15]_INST_0_i_1_n_0
    SLICE_X11Y75         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     5.278 r  u_dut/y[18]_INST_0_i_1/O[2]
                         net (fo=2, routed)           0.489     5.767    u_dut/y[18]_INST_0_i_1_n_5
    SLICE_X9Y74          LUT5 (Prop_lut5_I0_O)        0.302     6.069 r  u_dut/y[17]_INST_0_i_2/O
                         net (fo=1, routed)           0.485     6.554    u_dut/y[17]_INST_0_i_2_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     6.678 r  u_dut/y[17]_INST_0/O
                         net (fo=1, routed)           0.000     6.678    dut_y[17]
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=94, unset)           0.924     7.591    clk
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X9Y74          FDRE (Setup_fdre_C_D)        0.029     7.585    y_r_reg[17]
  -------------------------------------------------------------------
                         required time                          7.585    
                         arrival time                          -6.678    
  -------------------------------------------------------------------
                         slack                                  0.907    

Slack (MET) :             0.907ns  (required time - arrival time)
  Source:                 u_dut/s1_mag_reg/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.705ns  (logic 2.575ns (45.137%)  route 3.130ns (54.863%))
  Logic Levels:           10  (CARRY4=5 LUT3=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.973     0.973    u_dut/clk
    DSP48_X0Y28          DSP48E1                                      r  u_dut/s1_mag_reg/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X0Y28          DSP48E1 (Prop_dsp48e1_CLK_P[17])
                                                      0.434     1.407 r  u_dut/s1_mag_reg/P[17]
                         net (fo=4, routed)           0.980     2.387    u_dut/s1_guard_hi
    SLICE_X12Y72         LUT3 (Prop_lut3_I0_O)        0.150     2.537 r  u_dut/y[3]_INST_0_i_10/O
                         net (fo=3, routed)           0.600     3.136    u_dut/y[3]_INST_0_i_10_n_0
    SLICE_X12Y70         LUT6 (Prop_lut6_I4_O)        0.328     3.464 r  u_dut/y[3]_INST_0_i_9/O
                         net (fo=1, routed)           0.568     4.032    u_dut/y[3]_INST_0_i_9_n_0
    SLICE_X11Y71         LUT6 (Prop_lut6_I5_O)        0.124     4.156 r  u_dut/y[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     4.156    u_dut/y[3]_INST_0_i_6_n_0
    SLICE_X11Y71         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     4.688 r  u_dut/y[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.688    u_dut/y[3]_INST_0_i_1_n_0
    SLICE_X11Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.802 r  u_dut/y[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.802    u_dut/y[7]_INST_0_i_1_n_0
    SLICE_X11Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.916 f  u_dut/y[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.916    u_dut/y[11]_INST_0_i_1_n_0
    SLICE_X11Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     5.030 r  u_dut/y[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     5.039    u_dut/y[15]_INST_0_i_1_n_0
    SLICE_X11Y75         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     5.278 r  u_dut/y[18]_INST_0_i_1/O[2]
                         net (fo=2, routed)           0.489     5.767    u_dut/y[18]_INST_0_i_1_n_5
    SLICE_X9Y74          LUT5 (Prop_lut5_I0_O)        0.302     6.069 r  u_dut/y[17]_INST_0_i_2/O
                         net (fo=1, routed)           0.485     6.554    u_dut/y[17]_INST_0_i_2_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     6.678 r  u_dut/y[17]_INST_0/O
                         net (fo=1, routed)           0.000     6.678    dut_y[17]
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=94, unset)           0.924     7.591    clk
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X9Y74          FDRE (Setup_fdre_C_D)        0.029     7.585    y_r_reg[17]
  -------------------------------------------------------------------
                         required time                          7.585    
                         arrival time                          -6.678    
  -------------------------------------------------------------------
                         slack                                  0.907    

Slack (MET) :             0.907ns  (required time - arrival time)
  Source:                 u_dut/s1_mag_reg/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.705ns  (logic 2.575ns (45.137%)  route 3.130ns (54.863%))
  Logic Levels:           10  (CARRY4=5 LUT3=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.973     0.973    u_dut/clk
    DSP48_X0Y28          DSP48E1                                      r  u_dut/s1_mag_reg/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X0Y28          DSP48E1 (Prop_dsp48e1_CLK_P[17])
                                                      0.434     1.407 r  u_dut/s1_mag_reg/P[17]
                         net (fo=4, routed)           0.980     2.387    u_dut/s1_guard_hi
    SLICE_X12Y72         LUT3 (Prop_lut3_I0_O)        0.150     2.537 r  u_dut/y[3]_INST_0_i_10/O
                         net (fo=3, routed)           0.600     3.136    u_dut/y[3]_INST_0_i_10_n_0
    SLICE_X12Y70         LUT6 (Prop_lut6_I4_O)        0.328     3.464 r  u_dut/y[3]_INST_0_i_9/O
                         net (fo=1, routed)           0.568     4.032    u_dut/y[3]_INST_0_i_9_n_0
    SLICE_X11Y71         LUT6 (Prop_lut6_I5_O)        0.124     4.156 r  u_dut/y[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     4.156    u_dut/y[3]_INST_0_i_6_n_0
    SLICE_X11Y71         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     4.688 r  u_dut/y[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.688    u_dut/y[3]_INST_0_i_1_n_0
    SLICE_X11Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.802 f  u_dut/y[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.802    u_dut/y[7]_INST_0_i_1_n_0
    SLICE_X11Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.916 f  u_dut/y[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.916    u_dut/y[11]_INST_0_i_1_n_0
    SLICE_X11Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     5.030 r  u_dut/y[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     5.039    u_dut/y[15]_INST_0_i_1_n_0
    SLICE_X11Y75         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     5.278 r  u_dut/y[18]_INST_0_i_1/O[2]
                         net (fo=2, routed)           0.489     5.767    u_dut/y[18]_INST_0_i_1_n_5
    SLICE_X9Y74          LUT5 (Prop_lut5_I0_O)        0.302     6.069 r  u_dut/y[17]_INST_0_i_2/O
                         net (fo=1, routed)           0.485     6.554    u_dut/y[17]_INST_0_i_2_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     6.678 r  u_dut/y[17]_INST_0/O
                         net (fo=1, routed)           0.000     6.678    dut_y[17]
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=94, unset)           0.924     7.591    clk
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X9Y74          FDRE (Setup_fdre_C_D)        0.029     7.585    y_r_reg[17]
  -------------------------------------------------------------------
                         required time                          7.585    
                         arrival time                          -6.678    
  -------------------------------------------------------------------
                         slack                                  0.907    

Slack (MET) :             0.907ns  (required time - arrival time)
  Source:                 u_dut/s1_mag_reg/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.705ns  (logic 2.575ns (45.137%)  route 3.130ns (54.863%))
  Logic Levels:           10  (CARRY4=5 LUT3=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.973     0.973    u_dut/clk
    DSP48_X0Y28          DSP48E1                                      r  u_dut/s1_mag_reg/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X0Y28          DSP48E1 (Prop_dsp48e1_CLK_P[17])
                                                      0.434     1.407 r  u_dut/s1_mag_reg/P[17]
                         net (fo=4, routed)           0.980     2.387    u_dut/s1_guard_hi
    SLICE_X12Y72         LUT3 (Prop_lut3_I0_O)        0.150     2.537 r  u_dut/y[3]_INST_0_i_10/O
                         net (fo=3, routed)           0.600     3.136    u_dut/y[3]_INST_0_i_10_n_0
    SLICE_X12Y70         LUT6 (Prop_lut6_I4_O)        0.328     3.464 r  u_dut/y[3]_INST_0_i_9/O
                         net (fo=1, routed)           0.568     4.032    u_dut/y[3]_INST_0_i_9_n_0
    SLICE_X11Y71         LUT6 (Prop_lut6_I5_O)        0.124     4.156 f  u_dut/y[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     4.156    u_dut/y[3]_INST_0_i_6_n_0
    SLICE_X11Y71         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     4.688 r  u_dut/y[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.688    u_dut/y[3]_INST_0_i_1_n_0
    SLICE_X11Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.802 f  u_dut/y[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.802    u_dut/y[7]_INST_0_i_1_n_0
    SLICE_X11Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.916 f  u_dut/y[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.916    u_dut/y[11]_INST_0_i_1_n_0
    SLICE_X11Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     5.030 r  u_dut/y[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     5.039    u_dut/y[15]_INST_0_i_1_n_0
    SLICE_X11Y75         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     5.278 r  u_dut/y[18]_INST_0_i_1/O[2]
                         net (fo=2, routed)           0.489     5.767    u_dut/y[18]_INST_0_i_1_n_5
    SLICE_X9Y74          LUT5 (Prop_lut5_I0_O)        0.302     6.069 r  u_dut/y[17]_INST_0_i_2/O
                         net (fo=1, routed)           0.485     6.554    u_dut/y[17]_INST_0_i_2_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     6.678 r  u_dut/y[17]_INST_0/O
                         net (fo=1, routed)           0.000     6.678    dut_y[17]
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=94, unset)           0.924     7.591    clk
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X9Y74          FDRE (Setup_fdre_C_D)        0.029     7.585    y_r_reg[17]
  -------------------------------------------------------------------
                         required time                          7.585    
                         arrival time                          -6.678    
  -------------------------------------------------------------------
                         slack                                  0.907    

Slack (MET) :             0.907ns  (required time - arrival time)
  Source:                 u_dut/s1_mag_reg/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.705ns  (logic 2.575ns (45.137%)  route 3.130ns (54.863%))
  Logic Levels:           10  (CARRY4=5 LUT3=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.973     0.973    u_dut/clk
    DSP48_X0Y28          DSP48E1                                      r  u_dut/s1_mag_reg/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X0Y28          DSP48E1 (Prop_dsp48e1_CLK_P[17])
                                                      0.434     1.407 r  u_dut/s1_mag_reg/P[17]
                         net (fo=4, routed)           0.980     2.387    u_dut/s1_guard_hi
    SLICE_X12Y72         LUT3 (Prop_lut3_I0_O)        0.150     2.537 r  u_dut/y[3]_INST_0_i_10/O
                         net (fo=3, routed)           0.600     3.136    u_dut/y[3]_INST_0_i_10_n_0
    SLICE_X12Y70         LUT6 (Prop_lut6_I4_O)        0.328     3.464 r  u_dut/y[3]_INST_0_i_9/O
                         net (fo=1, routed)           0.568     4.032    u_dut/y[3]_INST_0_i_9_n_0
    SLICE_X11Y71         LUT6 (Prop_lut6_I5_O)        0.124     4.156 r  u_dut/y[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     4.156    u_dut/y[3]_INST_0_i_6_n_0
    SLICE_X11Y71         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     4.688 r  u_dut/y[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.688    u_dut/y[3]_INST_0_i_1_n_0
    SLICE_X11Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.802 r  u_dut/y[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.802    u_dut/y[7]_INST_0_i_1_n_0
    SLICE_X11Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.916 r  u_dut/y[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.916    u_dut/y[11]_INST_0_i_1_n_0
    SLICE_X11Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     5.030 f  u_dut/y[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     5.039    u_dut/y[15]_INST_0_i_1_n_0
    SLICE_X11Y75         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     5.278 r  u_dut/y[18]_INST_0_i_1/O[2]
                         net (fo=2, routed)           0.489     5.767    u_dut/y[18]_INST_0_i_1_n_5
    SLICE_X9Y74          LUT5 (Prop_lut5_I0_O)        0.302     6.069 r  u_dut/y[17]_INST_0_i_2/O
                         net (fo=1, routed)           0.485     6.554    u_dut/y[17]_INST_0_i_2_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     6.678 r  u_dut/y[17]_INST_0/O
                         net (fo=1, routed)           0.000     6.678    dut_y[17]
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=94, unset)           0.924     7.591    clk
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X9Y74          FDRE (Setup_fdre_C_D)        0.029     7.585    y_r_reg[17]
  -------------------------------------------------------------------
                         required time                          7.585    
                         arrival time                          -6.678    
  -------------------------------------------------------------------
                         slack                                  0.907    

Slack (MET) :             0.907ns  (required time - arrival time)
  Source:                 u_dut/s1_mag_reg/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.705ns  (logic 2.575ns (45.137%)  route 3.130ns (54.863%))
  Logic Levels:           10  (CARRY4=5 LUT3=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.973     0.973    u_dut/clk
    DSP48_X0Y28          DSP48E1                                      r  u_dut/s1_mag_reg/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X0Y28          DSP48E1 (Prop_dsp48e1_CLK_P[17])
                                                      0.434     1.407 r  u_dut/s1_mag_reg/P[17]
                         net (fo=4, routed)           0.980     2.387    u_dut/s1_guard_hi
    SLICE_X12Y72         LUT3 (Prop_lut3_I0_O)        0.150     2.537 r  u_dut/y[3]_INST_0_i_10/O
                         net (fo=3, routed)           0.600     3.136    u_dut/y[3]_INST_0_i_10_n_0
    SLICE_X12Y70         LUT6 (Prop_lut6_I4_O)        0.328     3.464 r  u_dut/y[3]_INST_0_i_9/O
                         net (fo=1, routed)           0.568     4.032    u_dut/y[3]_INST_0_i_9_n_0
    SLICE_X11Y71         LUT6 (Prop_lut6_I5_O)        0.124     4.156 r  u_dut/y[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     4.156    u_dut/y[3]_INST_0_i_6_n_0
    SLICE_X11Y71         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     4.688 r  u_dut/y[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.688    u_dut/y[3]_INST_0_i_1_n_0
    SLICE_X11Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.802 f  u_dut/y[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.802    u_dut/y[7]_INST_0_i_1_n_0
    SLICE_X11Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.916 r  u_dut/y[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.916    u_dut/y[11]_INST_0_i_1_n_0
    SLICE_X11Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     5.030 f  u_dut/y[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     5.039    u_dut/y[15]_INST_0_i_1_n_0
    SLICE_X11Y75         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     5.278 r  u_dut/y[18]_INST_0_i_1/O[2]
                         net (fo=2, routed)           0.489     5.767    u_dut/y[18]_INST_0_i_1_n_5
    SLICE_X9Y74          LUT5 (Prop_lut5_I0_O)        0.302     6.069 r  u_dut/y[17]_INST_0_i_2/O
                         net (fo=1, routed)           0.485     6.554    u_dut/y[17]_INST_0_i_2_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     6.678 r  u_dut/y[17]_INST_0/O
                         net (fo=1, routed)           0.000     6.678    dut_y[17]
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=94, unset)           0.924     7.591    clk
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X9Y74          FDRE (Setup_fdre_C_D)        0.029     7.585    y_r_reg[17]
  -------------------------------------------------------------------
                         required time                          7.585    
                         arrival time                          -6.678    
  -------------------------------------------------------------------
                         slack                                  0.907    

Slack (MET) :             0.907ns  (required time - arrival time)
  Source:                 u_dut/s1_mag_reg/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.705ns  (logic 2.575ns (45.137%)  route 3.130ns (54.863%))
  Logic Levels:           10  (CARRY4=5 LUT3=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.973     0.973    u_dut/clk
    DSP48_X0Y28          DSP48E1                                      r  u_dut/s1_mag_reg/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X0Y28          DSP48E1 (Prop_dsp48e1_CLK_P[17])
                                                      0.434     1.407 r  u_dut/s1_mag_reg/P[17]
                         net (fo=4, routed)           0.980     2.387    u_dut/s1_guard_hi
    SLICE_X12Y72         LUT3 (Prop_lut3_I0_O)        0.150     2.537 r  u_dut/y[3]_INST_0_i_10/O
                         net (fo=3, routed)           0.600     3.136    u_dut/y[3]_INST_0_i_10_n_0
    SLICE_X12Y70         LUT6 (Prop_lut6_I4_O)        0.328     3.464 r  u_dut/y[3]_INST_0_i_9/O
                         net (fo=1, routed)           0.568     4.032    u_dut/y[3]_INST_0_i_9_n_0
    SLICE_X11Y71         LUT6 (Prop_lut6_I5_O)        0.124     4.156 r  u_dut/y[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     4.156    u_dut/y[3]_INST_0_i_6_n_0
    SLICE_X11Y71         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     4.688 r  u_dut/y[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.688    u_dut/y[3]_INST_0_i_1_n_0
    SLICE_X11Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.802 r  u_dut/y[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.802    u_dut/y[7]_INST_0_i_1_n_0
    SLICE_X11Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.916 f  u_dut/y[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.916    u_dut/y[11]_INST_0_i_1_n_0
    SLICE_X11Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     5.030 f  u_dut/y[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     5.039    u_dut/y[15]_INST_0_i_1_n_0
    SLICE_X11Y75         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     5.278 r  u_dut/y[18]_INST_0_i_1/O[2]
                         net (fo=2, routed)           0.489     5.767    u_dut/y[18]_INST_0_i_1_n_5
    SLICE_X9Y74          LUT5 (Prop_lut5_I0_O)        0.302     6.069 r  u_dut/y[17]_INST_0_i_2/O
                         net (fo=1, routed)           0.485     6.554    u_dut/y[17]_INST_0_i_2_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     6.678 r  u_dut/y[17]_INST_0/O
                         net (fo=1, routed)           0.000     6.678    dut_y[17]
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=94, unset)           0.924     7.591    clk
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X9Y74          FDRE (Setup_fdre_C_D)        0.029     7.585    y_r_reg[17]
  -------------------------------------------------------------------
                         required time                          7.585    
                         arrival time                          -6.678    
  -------------------------------------------------------------------
                         slack                                  0.907    

Slack (MET) :             0.907ns  (required time - arrival time)
  Source:                 u_dut/s1_mag_reg/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        5.705ns  (logic 2.575ns (45.137%)  route 3.130ns (54.863%))
  Logic Levels:           10  (CARRY4=5 LUT3=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.973     0.973    u_dut/clk
    DSP48_X0Y28          DSP48E1                                      r  u_dut/s1_mag_reg/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X0Y28          DSP48E1 (Prop_dsp48e1_CLK_P[17])
                                                      0.434     1.407 r  u_dut/s1_mag_reg/P[17]
                         net (fo=4, routed)           0.980     2.387    u_dut/s1_guard_hi
    SLICE_X12Y72         LUT3 (Prop_lut3_I0_O)        0.150     2.537 r  u_dut/y[3]_INST_0_i_10/O
                         net (fo=3, routed)           0.600     3.136    u_dut/y[3]_INST_0_i_10_n_0
    SLICE_X12Y70         LUT6 (Prop_lut6_I4_O)        0.328     3.464 r  u_dut/y[3]_INST_0_i_9/O
                         net (fo=1, routed)           0.568     4.032    u_dut/y[3]_INST_0_i_9_n_0
    SLICE_X11Y71         LUT6 (Prop_lut6_I5_O)        0.124     4.156 r  u_dut/y[3]_INST_0_i_6/O
                         net (fo=1, routed)           0.000     4.156    u_dut/y[3]_INST_0_i_6_n_0
    SLICE_X11Y71         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     4.688 r  u_dut/y[3]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.688    u_dut/y[3]_INST_0_i_1_n_0
    SLICE_X11Y72         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.802 f  u_dut/y[7]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.802    u_dut/y[7]_INST_0_i_1_n_0
    SLICE_X11Y73         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.916 f  u_dut/y[11]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.916    u_dut/y[11]_INST_0_i_1_n_0
    SLICE_X11Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     5.030 f  u_dut/y[15]_INST_0_i_1/CO[3]
                         net (fo=1, routed)           0.009     5.039    u_dut/y[15]_INST_0_i_1_n_0
    SLICE_X11Y75         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     5.278 r  u_dut/y[18]_INST_0_i_1/O[2]
                         net (fo=2, routed)           0.489     5.767    u_dut/y[18]_INST_0_i_1_n_5
    SLICE_X9Y74          LUT5 (Prop_lut5_I0_O)        0.302     6.069 r  u_dut/y[17]_INST_0_i_2/O
                         net (fo=1, routed)           0.485     6.554    u_dut/y[17]_INST_0_i_2_n_0
    SLICE_X9Y74          LUT6 (Prop_lut6_I1_O)        0.124     6.678 r  u_dut/y[17]_INST_0/O
                         net (fo=1, routed)           0.000     6.678    dut_y[17]
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=94, unset)           0.924     7.591    clk
    SLICE_X9Y74          FDRE                                         r  y_r_reg[17]/C
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    SLICE_X9Y74          FDRE (Setup_fdre_C_D)        0.029     7.585    y_r_reg[17]
  -------------------------------------------------------------------
                         required time                          7.585    
                         arrival time                          -6.678    
  -------------------------------------------------------------------
                         slack                                  0.907    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.164ns  (arrival time - required time)
  Source:                 a_r_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_sign_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.305ns  (logic 0.246ns (80.588%)  route 0.059ns (19.412%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.410     0.410    clk
    SLICE_X8Y75          FDRE                                         r  a_r_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y75          FDRE (Prop_fdre_C_Q)         0.148     0.558 r  a_r_reg[25]/Q
                         net (fo=1, routed)           0.059     0.617    u_dut/a[25]
    SLICE_X8Y75          LUT2 (Prop_lut2_I1_O)        0.098     0.715 r  u_dut/s1_sign_i_1/O
                         net (fo=1, routed)           0.000     0.715    u_dut/mag_src_sign
    SLICE_X8Y75          FDRE                                         r  u_dut/s1_sign_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.432     0.432    u_dut/clk
    SLICE_X8Y75          FDRE                                         r  u_dut/s1_sign_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X8Y75          FDRE (Hold_fdre_C_D)         0.120     0.552    u_dut/s1_sign_reg
  -------------------------------------------------------------------
                         required time                         -0.552    
                         arrival time                           0.715    
  -------------------------------------------------------------------
                         slack                                  0.164    

Slack (MET) :             0.164ns  (arrival time - required time)
  Source:                 a_r_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_sign_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.305ns  (logic 0.246ns (80.588%)  route 0.059ns (19.412%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.410     0.410    clk
    SLICE_X8Y75          FDRE                                         r  a_r_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y75          FDRE (Prop_fdre_C_Q)         0.148     0.558 f  a_r_reg[25]/Q
                         net (fo=1, routed)           0.059     0.617    u_dut/a[25]
    SLICE_X8Y75          LUT2 (Prop_lut2_I1_O)        0.098     0.715 r  u_dut/s1_sign_i_1/O
                         net (fo=1, routed)           0.000     0.715    u_dut/mag_src_sign
    SLICE_X8Y75          FDRE                                         r  u_dut/s1_sign_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.432     0.432    u_dut/clk
    SLICE_X8Y75          FDRE                                         r  u_dut/s1_sign_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X8Y75          FDRE (Hold_fdre_C_D)         0.120     0.552    u_dut/s1_sign_reg
  -------------------------------------------------------------------
                         required time                         -0.552    
                         arrival time                           0.715    
  -------------------------------------------------------------------
                         slack                                  0.164    

Slack (MET) :             0.164ns  (arrival time - required time)
  Source:                 a_r_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_sign_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.305ns  (logic 0.246ns (80.588%)  route 0.059ns (19.412%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.410     0.410    clk
    SLICE_X8Y75          FDRE                                         r  a_r_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y75          FDRE (Prop_fdre_C_Q)         0.148     0.558 r  a_r_reg[25]/Q
                         net (fo=1, routed)           0.059     0.617    u_dut/a[25]
    SLICE_X8Y75          LUT2 (Prop_lut2_I1_O)        0.098     0.715 f  u_dut/s1_sign_i_1/O
                         net (fo=1, routed)           0.000     0.715    u_dut/mag_src_sign
    SLICE_X8Y75          FDRE                                         f  u_dut/s1_sign_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.432     0.432    u_dut/clk
    SLICE_X8Y75          FDRE                                         r  u_dut/s1_sign_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X8Y75          FDRE (Hold_fdre_C_D)         0.120     0.552    u_dut/s1_sign_reg
  -------------------------------------------------------------------
                         required time                         -0.552    
                         arrival time                           0.715    
  -------------------------------------------------------------------
                         slack                                  0.164    

Slack (MET) :             0.164ns  (arrival time - required time)
  Source:                 a_r_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_sign_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.305ns  (logic 0.246ns (80.588%)  route 0.059ns (19.412%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.410     0.410    clk
    SLICE_X8Y75          FDRE                                         r  a_r_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y75          FDRE (Prop_fdre_C_Q)         0.148     0.558 f  a_r_reg[25]/Q
                         net (fo=1, routed)           0.059     0.617    u_dut/a[25]
    SLICE_X8Y75          LUT2 (Prop_lut2_I1_O)        0.098     0.715 f  u_dut/s1_sign_i_1/O
                         net (fo=1, routed)           0.000     0.715    u_dut/mag_src_sign
    SLICE_X8Y75          FDRE                                         f  u_dut/s1_sign_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.432     0.432    u_dut/clk
    SLICE_X8Y75          FDRE                                         r  u_dut/s1_sign_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X8Y75          FDRE (Hold_fdre_C_D)         0.120     0.552    u_dut/s1_sign_reg
  -------------------------------------------------------------------
                         required time                         -0.552    
                         arrival time                           0.715    
  -------------------------------------------------------------------
                         slack                                  0.164    

Slack (MET) :             0.190ns  (arrival time - required time)
  Source:                 u_dut/s1_sign_reg/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.302ns  (logic 0.209ns (69.158%)  route 0.093ns (30.842%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.410     0.410    u_dut/clk
    SLICE_X8Y75          FDRE                                         r  u_dut/s1_sign_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y75          FDRE (Prop_fdre_C_Q)         0.164     0.574 r  u_dut/s1_sign_reg/Q
                         net (fo=2, routed)           0.093     0.667    u_dut/s1_sign
    SLICE_X9Y75          LUT6 (Prop_lut6_I1_O)        0.045     0.712 r  u_dut/y[25]_INST_0/O
                         net (fo=1, routed)           0.000     0.712    dut_y[25]
    SLICE_X9Y75          FDRE                                         r  y_r_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.432     0.432    clk
    SLICE_X9Y75          FDRE                                         r  y_r_reg[25]/C
                         clock pessimism              0.000     0.432    
    SLICE_X9Y75          FDRE (Hold_fdre_C_D)         0.091     0.523    y_r_reg[25]
  -------------------------------------------------------------------
                         required time                         -0.523    
                         arrival time                           0.712    
  -------------------------------------------------------------------
                         slack                                  0.190    

Slack (MET) :             0.190ns  (arrival time - required time)
  Source:                 u_dut/s1_sign_reg/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            y_r_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.302ns  (logic 0.209ns (69.158%)  route 0.093ns (30.842%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.410     0.410    u_dut/clk
    SLICE_X8Y75          FDRE                                         r  u_dut/s1_sign_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y75          FDRE (Prop_fdre_C_Q)         0.164     0.574 f  u_dut/s1_sign_reg/Q
                         net (fo=2, routed)           0.093     0.667    u_dut/s1_sign
    SLICE_X9Y75          LUT6 (Prop_lut6_I1_O)        0.045     0.712 f  u_dut/y[25]_INST_0/O
                         net (fo=1, routed)           0.000     0.712    dut_y[25]
    SLICE_X9Y75          FDRE                                         f  y_r_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.432     0.432    clk
    SLICE_X9Y75          FDRE                                         r  y_r_reg[25]/C
                         clock pessimism              0.000     0.432    
    SLICE_X9Y75          FDRE (Hold_fdre_C_D)         0.091     0.523    y_r_reg[25]
  -------------------------------------------------------------------
                         required time                         -0.523    
                         arrival time                           0.712    
  -------------------------------------------------------------------
                         slack                                  0.190    

Slack (MET) :             0.258ns  (arrival time - required time)
  Source:                 b_r_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_exp_unbiased_base_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.384ns  (logic 0.279ns (72.618%)  route 0.105ns (27.382%))
  Logic Levels:           2  (CARRY4=1 LUT4=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.410     0.410    clk
    SLICE_X12Y76         FDRE                                         r  b_r_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y76         FDRE (Prop_fdre_C_Q)         0.164     0.574 r  b_r_reg[20]/Q
                         net (fo=5, routed)           0.105     0.679    u_dut/b[20]
    SLICE_X13Y76         LUT4 (Prop_lut4_I1_O)        0.045     0.724 r  u_dut/s1_exp_unbiased_base[7]_i_9/O
                         net (fo=1, routed)           0.000     0.724    u_dut/s1_exp_unbiased_base[7]_i_9_n_0
    SLICE_X13Y76         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.070     0.794 r  u_dut/s1_exp_unbiased_base_reg[7]_i_1/O[0]
                         net (fo=1, routed)           0.000     0.794    u_dut/exp_unbiased_in[4]
    SLICE_X13Y76         FDRE                                         r  u_dut/s1_exp_unbiased_base_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.432     0.432    u_dut/clk
    SLICE_X13Y76         FDRE                                         r  u_dut/s1_exp_unbiased_base_reg[4]/C
                         clock pessimism              0.000     0.432    
    SLICE_X13Y76         FDRE (Hold_fdre_C_D)         0.105     0.537    u_dut/s1_exp_unbiased_base_reg[4]
  -------------------------------------------------------------------
                         required time                         -0.537    
                         arrival time                           0.794    
  -------------------------------------------------------------------
                         slack                                  0.258    

Slack (MET) :             0.258ns  (arrival time - required time)
  Source:                 b_r_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_exp_unbiased_base_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.384ns  (logic 0.279ns (72.618%)  route 0.105ns (27.382%))
  Logic Levels:           2  (CARRY4=1 LUT4=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.410     0.410    clk
    SLICE_X12Y76         FDRE                                         r  b_r_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y76         FDRE (Prop_fdre_C_Q)         0.164     0.574 f  b_r_reg[20]/Q
                         net (fo=5, routed)           0.105     0.679    u_dut/b[20]
    SLICE_X13Y76         LUT4 (Prop_lut4_I1_O)        0.045     0.724 r  u_dut/s1_exp_unbiased_base[7]_i_9/O
                         net (fo=1, routed)           0.000     0.724    u_dut/s1_exp_unbiased_base[7]_i_9_n_0
    SLICE_X13Y76         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.070     0.794 r  u_dut/s1_exp_unbiased_base_reg[7]_i_1/O[0]
                         net (fo=1, routed)           0.000     0.794    u_dut/exp_unbiased_in[4]
    SLICE_X13Y76         FDRE                                         r  u_dut/s1_exp_unbiased_base_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.432     0.432    u_dut/clk
    SLICE_X13Y76         FDRE                                         r  u_dut/s1_exp_unbiased_base_reg[4]/C
                         clock pessimism              0.000     0.432    
    SLICE_X13Y76         FDRE (Hold_fdre_C_D)         0.105     0.537    u_dut/s1_exp_unbiased_base_reg[4]
  -------------------------------------------------------------------
                         required time                         -0.537    
                         arrival time                           0.794    
  -------------------------------------------------------------------
                         slack                                  0.258    

Slack (MET) :             0.258ns  (arrival time - required time)
  Source:                 b_r_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_exp_unbiased_base_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.384ns  (logic 0.279ns (72.618%)  route 0.105ns (27.382%))
  Logic Levels:           2  (CARRY4=1 LUT4=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.410     0.410    clk
    SLICE_X12Y76         FDRE                                         r  b_r_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y76         FDRE (Prop_fdre_C_Q)         0.164     0.574 r  b_r_reg[20]/Q
                         net (fo=5, routed)           0.105     0.679    u_dut/b[20]
    SLICE_X13Y76         LUT4 (Prop_lut4_I1_O)        0.045     0.724 f  u_dut/s1_exp_unbiased_base[7]_i_9/O
                         net (fo=1, routed)           0.000     0.724    u_dut/s1_exp_unbiased_base[7]_i_9_n_0
    SLICE_X13Y76         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.070     0.794 r  u_dut/s1_exp_unbiased_base_reg[7]_i_1/O[0]
                         net (fo=1, routed)           0.000     0.794    u_dut/exp_unbiased_in[4]
    SLICE_X13Y76         FDRE                                         r  u_dut/s1_exp_unbiased_base_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.432     0.432    u_dut/clk
    SLICE_X13Y76         FDRE                                         r  u_dut/s1_exp_unbiased_base_reg[4]/C
                         clock pessimism              0.000     0.432    
    SLICE_X13Y76         FDRE (Hold_fdre_C_D)         0.105     0.537    u_dut/s1_exp_unbiased_base_reg[4]
  -------------------------------------------------------------------
                         required time                         -0.537    
                         arrival time                           0.794    
  -------------------------------------------------------------------
                         slack                                  0.258    

Slack (MET) :             0.258ns  (arrival time - required time)
  Source:                 b_r_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/s1_exp_unbiased_base_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.384ns  (logic 0.279ns (72.618%)  route 0.105ns (27.382%))
  Logic Levels:           2  (CARRY4=1 LUT4=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.410     0.410    clk
    SLICE_X12Y76         FDRE                                         r  b_r_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y76         FDRE (Prop_fdre_C_Q)         0.164     0.574 f  b_r_reg[20]/Q
                         net (fo=5, routed)           0.105     0.679    u_dut/b[20]
    SLICE_X13Y76         LUT4 (Prop_lut4_I1_O)        0.045     0.724 f  u_dut/s1_exp_unbiased_base[7]_i_9/O
                         net (fo=1, routed)           0.000     0.724    u_dut/s1_exp_unbiased_base[7]_i_9_n_0
    SLICE_X13Y76         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.070     0.794 r  u_dut/s1_exp_unbiased_base_reg[7]_i_1/O[0]
                         net (fo=1, routed)           0.000     0.794    u_dut/exp_unbiased_in[4]
    SLICE_X13Y76         FDRE                                         r  u_dut/s1_exp_unbiased_base_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=94, unset)           0.432     0.432    u_dut/clk
    SLICE_X13Y76         FDRE                                         r  u_dut/s1_exp_unbiased_base_reg[4]/C
                         clock pessimism              0.000     0.432    
    SLICE_X13Y76         FDRE (Hold_fdre_C_D)         0.105     0.537    u_dut/s1_exp_unbiased_base_reg[4]
  -------------------------------------------------------------------
                         required time                         -0.537    
                         arrival time                           0.794    
  -------------------------------------------------------------------
                         slack                                  0.258    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.667
Sources:            { clk }

Check Type        Corner  Lib Pin      Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     DSP48E1/CLK  n/a            2.154         6.667       4.513      DSP48_X0Y28   u_dut/s1_mag_reg/CLK
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X13Y73  a_r_reg[0]/C
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X13Y71  a_r_reg[10]/C
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X13Y72  a_r_reg[11]/C
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X13Y73  a_r_reg[12]/C
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X13Y73  a_r_reg[13]/C
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X13Y72  a_r_reg[14]/C
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X11Y73  a_r_reg[15]/C
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X12Y74  a_r_reg[16]/C
Min Period        n/a     FDRE/C       n/a            1.000         6.667       5.667      SLICE_X12Y75  a_r_reg[17]/C
Low Pulse Width   Slow    FDRE/C       n/a            0.500         3.333       2.833      SLICE_X13Y73  a_r_reg[0]/C
Low Pulse Width   Fast    FDRE/C       n/a            0.500         3.334       2.834      SLICE_X13Y73  a_r_reg[0]/C
Low Pulse Width   Slow    FDRE/C       n/a            0.500         3.333       2.833      SLICE_X13Y71  a_r_reg[10]/C
Low Pulse Width   Fast    FDRE/C       n/a            0.500         3.334       2.834      SLICE_X13Y71  a_r_reg[10]/C
Low Pulse Width   Slow    FDRE/C       n/a            0.500         3.333       2.833      SLICE_X13Y72  a_r_reg[11]/C
Low Pulse Width   Fast    FDRE/C       n/a            0.500         3.334       2.834      SLICE_X13Y72  a_r_reg[11]/C
Low Pulse Width   Slow    FDRE/C       n/a            0.500         3.333       2.833      SLICE_X13Y73  a_r_reg[12]/C
Low Pulse Width   Fast    FDRE/C       n/a            0.500         3.334       2.834      SLICE_X13Y73  a_r_reg[12]/C
Low Pulse Width   Slow    FDRE/C       n/a            0.500         3.333       2.833      SLICE_X13Y73  a_r_reg[13]/C
Low Pulse Width   Fast    FDRE/C       n/a            0.500         3.334       2.834      SLICE_X13Y73  a_r_reg[13]/C
High Pulse Width  Slow    FDRE/C       n/a            0.500         3.334       2.834      SLICE_X13Y73  a_r_reg[0]/C
High Pulse Width  Fast    FDRE/C       n/a            0.500         3.333       2.833      SLICE_X13Y73  a_r_reg[0]/C
High Pulse Width  Slow    FDRE/C       n/a            0.500         3.334       2.834      SLICE_X13Y71  a_r_reg[10]/C
High Pulse Width  Fast    FDRE/C       n/a            0.500         3.333       2.833      SLICE_X13Y71  a_r_reg[10]/C
High Pulse Width  Slow    FDRE/C       n/a            0.500         3.334       2.834      SLICE_X13Y72  a_r_reg[11]/C
High Pulse Width  Fast    FDRE/C       n/a            0.500         3.333       2.833      SLICE_X13Y72  a_r_reg[11]/C
High Pulse Width  Slow    FDRE/C       n/a            0.500         3.334       2.834      SLICE_X13Y73  a_r_reg[12]/C
High Pulse Width  Fast    FDRE/C       n/a            0.500         3.333       2.833      SLICE_X13Y73  a_r_reg[12]/C
High Pulse Width  Slow    FDRE/C       n/a            0.500         3.334       2.834      SLICE_X13Y73  a_r_reg[13]/C
High Pulse Width  Fast    FDRE/C       n/a            0.500         3.333       2.833      SLICE_X13Y73  a_r_reg[13]/C



