/----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2026 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3) -- Executing script file `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/yosys.ys' -- 1. Executing Verilog-2005 frontend: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v Parsing SystemVerilog input from `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v' to AST representation. Generating RTLIL representation for module `\FpxxAdd'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/top_tommath_add_e8_m35_round_even_sticky_p3.v Parsing SystemVerilog input from `/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/top_tommath_add_e8_m35_round_even_sticky_p3.v' to AST representation. Generating RTLIL representation for module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Successfully finished Verilog frontend. 3. Executing SYNTH_LATTICE pass. 3.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\VLO'. Generating RTLIL representation for module `\VHI'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\DP16KD'. Replacing existing blackbox module `\FD1P3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:2.1-2.261. Generating RTLIL representation for module `\FD1P3AX'. Replacing existing blackbox module `\FD1P3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:3.1-3.261. Generating RTLIL representation for module `\FD1P3AY'. Replacing existing blackbox module `\FD1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:4.1-4.261. Generating RTLIL representation for module `\FD1P3BX'. Replacing existing blackbox module `\FD1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:5.1-5.261. Generating RTLIL representation for module `\FD1P3DX'. Replacing existing blackbox module `\FD1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:6.1-6.261. Generating RTLIL representation for module `\FD1P3IX'. Replacing existing blackbox module `\FD1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:7.1-7.261. Generating RTLIL representation for module `\FD1P3JX'. Replacing existing blackbox module `\FD1S3AX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:8.1-8.261. Generating RTLIL representation for module `\FD1S3AX'. Replacing existing blackbox module `\FD1S3AY' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:9.1-9.261. Generating RTLIL representation for module `\FD1S3AY'. Replacing existing blackbox module `\FD1S3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:10.1-10.261. Generating RTLIL representation for module `\FD1S3BX'. Replacing existing blackbox module `\FD1S3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:11.1-11.261. Generating RTLIL representation for module `\FD1S3DX'. Replacing existing blackbox module `\FD1S3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:12.1-12.261. Generating RTLIL representation for module `\FD1S3IX'. Replacing existing blackbox module `\FD1S3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:13.1-13.261. Generating RTLIL representation for module `\FD1S3JX'. Replacing existing blackbox module `\IFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:26.1-26.301. Generating RTLIL representation for module `\IFS1P3BX'. Replacing existing blackbox module `\IFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:27.1-27.301. Generating RTLIL representation for module `\IFS1P3DX'. Replacing existing blackbox module `\IFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:28.1-28.301. Generating RTLIL representation for module `\IFS1P3IX'. Replacing existing blackbox module `\IFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:29.1-29.301. Generating RTLIL representation for module `\IFS1P3JX'. Replacing existing blackbox module `\OFS1P3BX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:31.1-31.302. Generating RTLIL representation for module `\OFS1P3BX'. Replacing existing blackbox module `\OFS1P3DX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:32.1-32.302. Generating RTLIL representation for module `\OFS1P3DX'. Replacing existing blackbox module `\OFS1P3IX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:33.1-33.302. Generating RTLIL representation for module `\OFS1P3IX'. Replacing existing blackbox module `\OFS1P3JX' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_ff.vh:34.1-34.302. Generating RTLIL representation for module `\OFS1P3JX'. Replacing existing blackbox module `\IB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:2.1-2.157. Generating RTLIL representation for module `\IB'. Replacing existing blackbox module `\IBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:3.1-3.157. Generating RTLIL representation for module `\IBPU'. Replacing existing blackbox module `\IBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:4.1-4.157. Generating RTLIL representation for module `\IBPD'. Replacing existing blackbox module `\OB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:5.1-5.157. Generating RTLIL representation for module `\OB'. Replacing existing blackbox module `\OBZ' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:6.1-6.164. Generating RTLIL representation for module `\OBZ'. Replacing existing blackbox module `\OBZPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:7.1-7.164. Generating RTLIL representation for module `\OBZPU'. Replacing existing blackbox module `\OBZPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:8.1-8.164. Generating RTLIL representation for module `\OBZPD'. Replacing existing blackbox module `\OBCO' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:9.1-9.90. Generating RTLIL representation for module `\OBCO'. Replacing existing blackbox module `\BB' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:10.1-10.179. Generating RTLIL representation for module `\BB'. Replacing existing blackbox module `\BBPU' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:11.1-11.179. Generating RTLIL representation for module `\BBPU'. Replacing existing blackbox module `\BBPD' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:12.1-12.179. Generating RTLIL representation for module `\BBPD'. Replacing existing blackbox module `\ILVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:13.1-13.139. Generating RTLIL representation for module `\ILVDS'. Replacing existing blackbox module `\OLVDS' at /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_io.vh:14.1-14.146. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 3.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DCUA'. Successfully finished Verilog frontend. 3.3. Executing HIERARCHY pass (managing design hierarchy). 3.3.1. Analyzing design hierarchy.. Top module: \top_tommath_add_e8_m35_round_even_sticky_p3 Used module: \FpxxAdd 3.3.2. Analyzing design hierarchy.. Top module: \top_tommath_add_e8_m35_round_even_sticky_p3 Used module: \FpxxAdd Removed 0 unused modules. 3.4. Executing PROC pass (convert processes to netlists). 3.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/top_tommath_add_e8_m35_round_even_sticky_p3.v:43$147 in module top_tommath_add_e8_m35_round_even_sticky_p3. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1393$145 in module FpxxAdd. Marked 2 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1354$138 in module FpxxAdd. Marked 2 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1342$133 in module FpxxAdd. Marked 2 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1330$132 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1319$128 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1311$126 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1297$120 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1288$117 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1280$115 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1266$114 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1250$113 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1234$112 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1218$111 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1201$110 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1185$109 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1169$108 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1151$107 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1135$106 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1119$105 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1103$104 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1087$103 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1071$102 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1054$101 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1038$100 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1022$99 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1004$98 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:988$97 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:972$96 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:956$95 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:939$94 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:923$93 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:907$92 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:888$91 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:872$90 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:856$89 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:840$88 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:824$87 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:807$86 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:791$85 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:775$84 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:757$83 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:741$82 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:725$81 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:709$80 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:692$79 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:676$78 in module FpxxAdd. Marked 1 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:660$77 in module FpxxAdd. Marked 2 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:636$73 in module FpxxAdd. Marked 2 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:624$71 in module FpxxAdd. Marked 2 switch rules as full_case in process $proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:612$70 in module FpxxAdd. Removed a total of 0 dead cases. 3.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 5 redundant assignments. Promoted 78 assignments to connections. 3.4.4. Executing PROC_INIT pass (extract init attributes). 3.4.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \reset in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1393$145'. 3.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\top_tommath_add_e8_m35_round_even_sticky_p3.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/top_tommath_add_e8_m35_round_even_sticky_p3.v:43$147'. 1/2: $0\out_valid_r[0:0] 2/2: $0\in_valid_r[0:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1393$145'. 1/3: $0\n4_valid[0:0] 2/3: $0\n2_valid[0:0] 3/3: $0\n1_valid[0:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1354$138'. 1/3: $2\n5_mant_final[34:0] 2/3: $1\n5_mant_final[34:0] [34] 3/3: $1\n5_mant_final[34:0] [33:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1342$133'. 1/2: $2\n5_exp_final[7:0] 2/2: $1\n5_exp_final[7:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1330$132'. 1/2: $2\n5_sign_final[0:0] 2/2: $1\n5_sign_final[0:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1319$128'. 1/1: $1\_zz_n5_mant_rounded[36:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1311$126'. 1/1: $1\_zz_n5_mant_rounded_1[36:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1297$120'. 1/1: $1\n4__exp_add_adj[7:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1288$117'. 1/2: $1\n4__mant_add_adj[38:0] [38:1] 2/2: $1\n4__mant_add_adj[38:0] [0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1280$115'. 1/1: $1\n4__lz[5:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1266$114'. 1/1: $1\_zz_n4__lz[6:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1250$113'. 1/1: $1\_zz_switch_Misc_l241_92[3:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1234$112'. 1/1: $1\_zz_switch_Misc_l241_90[2:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1218$111'. 1/1: $1\_zz_switch_Misc_l241_88[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1201$110'. 1/1: $1\_zz_switch_Misc_l241_85[2:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1185$109'. 1/1: $1\_zz_switch_Misc_l241_83[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1169$108'. 1/1: $1\_zz_switch_Misc_l241_81[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1151$107'. 1/1: $1\_zz_switch_Misc_l241_77[5:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1135$106'. 1/1: $1\_zz_switch_Misc_l241_75[4:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1119$105'. 1/1: $1\_zz_switch_Misc_l241_73[3:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1103$104'. 1/1: $1\_zz_switch_Misc_l241_71[2:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1087$103'. 1/1: $1\_zz_switch_Misc_l241_69[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1071$102'. 1/1: $1\_zz_switch_Misc_l241_67[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1054$101'. 1/1: $1\_zz_switch_Misc_l241_64[2:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1038$100'. 1/1: $1\_zz_switch_Misc_l241_62[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1022$99'. 1/1: $1\_zz_switch_Misc_l241_60[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1004$98'. 1/1: $1\_zz_switch_Misc_l241_56[3:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:988$97'. 1/1: $1\_zz_switch_Misc_l241_54[2:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:972$96'. 1/1: $1\_zz_switch_Misc_l241_52[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:956$95'. 1/1: $1\_zz_switch_Misc_l241_50[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:939$94'. 1/1: $1\_zz_switch_Misc_l241_47[2:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:923$93'. 1/1: $1\_zz_switch_Misc_l241_45[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:907$92'. 1/1: $1\_zz_switch_Misc_l241_43[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:888$91'. 1/1: $1\_zz_switch_Misc_l241_38[4:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:872$90'. 1/1: $1\_zz_switch_Misc_l241_36[3:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:856$89'. 1/1: $1\_zz_switch_Misc_l241_34[2:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:840$88'. 1/1: $1\_zz_switch_Misc_l241_32[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:824$87'. 1/1: $1\_zz_switch_Misc_l241_30[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:807$86'. 1/1: $1\_zz_switch_Misc_l241_27[2:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:791$85'. 1/1: $1\_zz_switch_Misc_l241_25[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:775$84'. 1/1: $1\_zz_switch_Misc_l241_23[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:757$83'. 1/1: $1\_zz_switch_Misc_l241_19[3:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:741$82'. 1/1: $1\_zz_switch_Misc_l241_17[2:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:725$81'. 1/1: $1\_zz_switch_Misc_l241_15[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:709$80'. 1/1: $1\_zz_switch_Misc_l241_13[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:692$79'. 1/1: $1\_zz_switch_Misc_l241_10[2:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:676$78'. 1/1: $1\_zz_switch_Misc_l241_8[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:660$77'. 1/1: $1\_zz_switch_Misc_l241_6[1:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:636$73'. 1/2: $2\n2__mant_b_opt_inv[40:0] 2/2: $1\n2__mant_b_opt_inv[40:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:624$71'. 1/2: $2\n2__mant_a_opt_inv[40:0] 2/2: $1\n2__mant_a_opt_inv[40:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:612$70'. 1/2: $2\n2__sign_add[0:0] 2/2: $1\n2__sign_add[0:0] Creating decoders for process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:602$60'. 3.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `\FpxxAdd.\n5_mant_final' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1354$138'. No latch inferred for signal `\FpxxAdd.\n5_exp_final' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1342$133'. No latch inferred for signal `\FpxxAdd.\n5_sign_final' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1330$132'. No latch inferred for signal `\FpxxAdd.\_zz_n5_mant_rounded' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1319$128'. No latch inferred for signal `\FpxxAdd.\_zz_n5_mant_rounded_1' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1311$126'. No latch inferred for signal `\FpxxAdd.\n4__exp_add_adj' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1297$120'. No latch inferred for signal `\FpxxAdd.\n4__mant_add_adj' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1288$117'. No latch inferred for signal `\FpxxAdd.\n4__lz' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1280$115'. No latch inferred for signal `\FpxxAdd.\_zz_n4__lz' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1266$114'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_92' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1250$113'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_90' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1234$112'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_88' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1218$111'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_85' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1201$110'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_83' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1185$109'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_81' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1169$108'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_77' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1151$107'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_75' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1135$106'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_73' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1119$105'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_71' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1103$104'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_69' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1087$103'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_67' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1071$102'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_64' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1054$101'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_62' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1038$100'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_60' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1022$99'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_56' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1004$98'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_54' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:988$97'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_52' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:972$96'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_50' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:956$95'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_47' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:939$94'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_45' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:923$93'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_43' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:907$92'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_38' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:888$91'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_36' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:872$90'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_34' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:856$89'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_32' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:840$88'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_30' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:824$87'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_27' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:807$86'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_25' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:791$85'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_23' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:775$84'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_19' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:757$83'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_17' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:741$82'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_15' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:725$81'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_13' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:709$80'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_10' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:692$79'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_8' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:676$78'. No latch inferred for signal `\FpxxAdd.\_zz_switch_Misc_l241_6' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:660$77'. No latch inferred for signal `\FpxxAdd.\n2__mant_b_opt_inv' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:636$73'. No latch inferred for signal `\FpxxAdd.\n2__mant_a_opt_inv' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:624$71'. No latch inferred for signal `\FpxxAdd.\n2__sign_add' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:612$70'. No latch inferred for signal `\FpxxAdd.\n1__mant_b_shift' from process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:602$60'. 3.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\top_tommath_add_e8_m35_round_even_sticky_p3.\a_r' using process `\top_tommath_add_e8_m35_round_even_sticky_p3.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/top_tommath_add_e8_m35_round_even_sticky_p3.v:43$147'. created $dff cell `$procdff$605' with positive edge clock. Creating register for signal `\top_tommath_add_e8_m35_round_even_sticky_p3.\b_r' using process `\top_tommath_add_e8_m35_round_even_sticky_p3.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/top_tommath_add_e8_m35_round_even_sticky_p3.v:43$147'. created $dff cell `$procdff$606' with positive edge clock. Creating register for signal `\top_tommath_add_e8_m35_round_even_sticky_p3.\in_valid_r' using process `\top_tommath_add_e8_m35_round_even_sticky_p3.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/top_tommath_add_e8_m35_round_even_sticky_p3.v:43$147'. created $dff cell `$procdff$607' with positive edge clock. Creating register for signal `\top_tommath_add_e8_m35_round_even_sticky_p3.\y_r' using process `\top_tommath_add_e8_m35_round_even_sticky_p3.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/top_tommath_add_e8_m35_round_even_sticky_p3.v:43$147'. created $dff cell `$procdff$608' with positive edge clock. Creating register for signal `\top_tommath_add_e8_m35_round_even_sticky_p3.\out_valid_r' using process `\top_tommath_add_e8_m35_round_even_sticky_p3.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/top_tommath_add_e8_m35_round_even_sticky_p3.v:43$147'. created $dff cell `$procdff$609' with positive edge clock. Creating register for signal `\FpxxAdd.\n4_n2_sign_add' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$610' with positive edge clock. Creating register for signal `\FpxxAdd.\n4_n0_is_inf' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$611' with positive edge clock. Creating register for signal `\FpxxAdd.\n4_n0_is_nan' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$612' with positive edge clock. Creating register for signal `\FpxxAdd.\n2_n0_exp_add' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$613' with positive edge clock. Creating register for signal `\FpxxAdd.\n2_n0_is_inf' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$614' with positive edge clock. Creating register for signal `\FpxxAdd.\n2_n0_is_nan' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$615' with positive edge clock. Creating register for signal `\FpxxAdd.\n2_n0_is_zero' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$616' with positive edge clock. Creating register for signal `\FpxxAdd.\n1_n0_exp_add' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$617' with positive edge clock. Creating register for signal `\FpxxAdd.\n1_n0_sign_b_swap' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$618' with positive edge clock. Creating register for signal `\FpxxAdd.\n1_n0_sign_a_swap' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$619' with positive edge clock. Creating register for signal `\FpxxAdd.\n1_n0_is_inf' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$620' with positive edge clock. Creating register for signal `\FpxxAdd.\n1_n0_is_nan' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$621' with positive edge clock. Creating register for signal `\FpxxAdd.\n1_n0_is_zero' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$622' with positive edge clock. Creating register for signal `\FpxxAdd.\n4_n0_exp_add' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$623' with positive edge clock. Creating register for signal `\FpxxAdd.\n4_n3_mant_add' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$624' with positive edge clock. Creating register for signal `\FpxxAdd.\n4_n0_is_zero' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$625' with positive edge clock. Creating register for signal `\FpxxAdd.\n2_n1_mant_b_adj' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$626' with positive edge clock. Creating register for signal `\FpxxAdd.\n2_n1_mant_a_adj' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$627' with positive edge clock. Creating register for signal `\FpxxAdd.\n2_n0_sign_b_swap' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$628' with positive edge clock. Creating register for signal `\FpxxAdd.\n2_n0_sign_a_swap' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$629' with positive edge clock. Creating register for signal `\FpxxAdd.\n1_n0_exp_diff_ovfl' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$630' with positive edge clock. Creating register for signal `\FpxxAdd.\n1_n0_exp_diff' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$631' with positive edge clock. Creating register for signal `\FpxxAdd.\n1_n0_mant_b_swap' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$632' with positive edge clock. Creating register for signal `\FpxxAdd.\n1_n0_mant_a_swap' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. created $dff cell `$procdff$633' with positive edge clock. Creating register for signal `\FpxxAdd.\n4_valid' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1393$145'. created $adff cell `$procdff$636' with positive edge clock and positive level reset. Creating register for signal `\FpxxAdd.\n2_valid' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1393$145'. created $adff cell `$procdff$639' with positive edge clock and positive level reset. Creating register for signal `\FpxxAdd.\n1_valid' using process `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1393$145'. created $adff cell `$procdff$642' with positive edge clock and positive level reset. 3.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\top_tommath_add_e8_m35_round_even_sticky_p3.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/top_tommath_add_e8_m35_round_even_sticky_p3.v:43$147'. Removing empty process `top_tommath_add_e8_m35_round_even_sticky_p3.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/top_tommath_add_e8_m35_round_even_sticky_p3.v:43$147'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1405$146'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1393$145'. Found and cleaned up 2 empty switches in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1354$138'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1354$138'. Found and cleaned up 2 empty switches in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1342$133'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1342$133'. Found and cleaned up 2 empty switches in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1330$132'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1330$132'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1319$128'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1319$128'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1311$126'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1311$126'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1297$120'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1297$120'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1288$117'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1288$117'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1280$115'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1280$115'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1266$114'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1266$114'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1250$113'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1250$113'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1234$112'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1234$112'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1218$111'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1218$111'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1201$110'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1201$110'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1185$109'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1185$109'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1169$108'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1169$108'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1151$107'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1151$107'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1135$106'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1135$106'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1119$105'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1119$105'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1103$104'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1103$104'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1087$103'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1087$103'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1071$102'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1071$102'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1054$101'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1054$101'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1038$100'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1038$100'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1022$99'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1022$99'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1004$98'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1004$98'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:988$97'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:988$97'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:972$96'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:972$96'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:956$95'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:956$95'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:939$94'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:939$94'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:923$93'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:923$93'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:907$92'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:907$92'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:888$91'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:888$91'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:872$90'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:872$90'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:856$89'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:856$89'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:840$88'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:840$88'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:824$87'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:824$87'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:807$86'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:807$86'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:791$85'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:791$85'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:775$84'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:775$84'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:757$83'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:757$83'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:741$82'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:741$82'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:725$81'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:725$81'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:709$80'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:709$80'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:692$79'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:692$79'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:676$78'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:676$78'. Found and cleaned up 1 empty switch in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:660$77'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:660$77'. Found and cleaned up 2 empty switches in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:636$73'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:636$73'. Found and cleaned up 2 empty switches in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:624$71'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:624$71'. Found and cleaned up 2 empty switches in `\FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:612$70'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:612$70'. Removing empty process `FpxxAdd.$proc$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:602$60'. Cleaned up 56 empty switches. 3.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.5. Executing CHECK pass (checking for obvious problems). Checking module top_tommath_add_e8_m35_round_even_sticky_p3... Checking module FpxxAdd... Found and reported 0 problems. 3.6. Executing FLATTEN pass (flatten design). Keeping top_tommath_add_e8_m35_round_even_sticky_p3.u_dut (found keep_hierarchy attribute). 3.7. Executing TRIBUF pass. 3.8. Executing DEMINOUT pass (demote inout ports to input or output). 3.9. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.10. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. Removed 1 unused cells and 267 unused wires. 3.11. Executing CHECK pass (checking for obvious problems). Checking module top_tommath_add_e8_m35_round_even_sticky_p3... Checking module FpxxAdd... Found and reported 0 problems. 3.12. Executing OPT pass (performing simple optimizations). 3.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 8 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 248 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Computing hashes of 241 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 7 cells. 3.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_add_e8_m35_round_even_sticky_p3.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \FpxxAdd.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $procmux$418: \n4_n3_mant_add [39:2] -> { 1'1 \n4_n3_mant_add [38:2] } Replacing known input bits on port A of cell $procmux$412: { 1'0 \n5_mant_renormed [38:3] } -> { 1'0 \n5_mant_renormed [38:4] 1'0 } Replacing known input bits on port A of cell $ternary$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:438$9: \_zz_n1__mant_b_shift_2 -> { 1'0 \_zz_n1__mant_b_shift_2 [5:0] } Analyzing evaluation results. dead port 1/2 on $mux $procmux$600. dead port 1/2 on $mux $procmux$591. dead port 1/2 on $mux $procmux$582. dead port 2/3 on $pmux $procmux$435. dead port 2/3 on $pmux $procmux$427. dead port 1/2 on $mux $procmux$403. dead port 1/2 on $mux $procmux$395. dead port 1/2 on $mux $procmux$383. Removed 8 multiplexer ports. 3.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing cells in module \FpxxAdd. Performed a total of 0 changes. 3.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 8 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 235 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 0 cells. 3.12.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $procdff$627 ($dff) from module FpxxAdd. Setting constant 0-bit at position 1 on $procdff$627 ($dff) from module FpxxAdd. Setting constant 0-bit at position 2 on $procdff$627 ($dff) from module FpxxAdd. Setting constant 0-bit at position 39 on $procdff$627 ($dff) from module FpxxAdd. 3.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. Removed 0 unused cells and 17 unused wires. 3.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.12.9. Rerunning OPT passes. (Maybe there is more to do..) 3.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_add_e8_m35_round_even_sticky_p3.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \FpxxAdd.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing cells in module \FpxxAdd. Performed a total of 0 changes. 3.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 8 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 235 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 0 cells. 3.12.13. Executing OPT_DFF pass (perform DFF optimizations). 3.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. 3.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.12.16. Finished fast OPT passes. (There is nothing left to do.) 3.13. Executing FSM pass (extract and optimize FSM). 3.13.1. Executing FSM_DETECT pass (finding FSMs in design). 3.13.2. Executing FSM_EXTRACT pass (extracting FSM from design). 3.13.3. Executing FSM_OPT pass (simple optimizations of FSMs). 3.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. 3.13.5. Executing FSM_OPT pass (simple optimizations of FSMs). 3.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 3.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 3.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 3.14. Executing OPT pass (performing simple optimizations). 3.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 8 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 235 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 0 cells. 3.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_add_e8_m35_round_even_sticky_p3.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \FpxxAdd.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing cells in module \FpxxAdd. Performed a total of 0 changes. 3.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 8 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 235 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 0 cells. 3.14.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $procdff$607 ($dff) from module top_tommath_add_e8_m35_round_even_sticky_p3 (D = \in_valid_i, Q = \in_valid_r, rval = 1'0). Adding SRST signal on $procdff$609 ($dff) from module top_tommath_add_e8_m35_round_even_sticky_p3 (D = \dut_valid, Q = \out_valid_r, rval = 1'0). Adding SRST signal on $procdff$626 ($dff) from module FpxxAdd (D = { \_zz_n1__mant_b_shift_3 [38:1] \n1__mant_b_shift [0] }, Q = \n2_n1_mant_b_adj [38:0], rval = 39'000000000000000000000000000000000000000). 3.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. Removed 2 unused cells and 2 unused wires. 3.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.14.9. Rerunning OPT passes. (Maybe there is more to do..) 3.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_add_e8_m35_round_even_sticky_p3.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \FpxxAdd.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing cells in module \FpxxAdd. Performed a total of 0 changes. 3.14.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 6 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 236 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 0 cells. 3.14.13. Executing OPT_DFF pass (perform DFF optimizations). 3.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. 3.14.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.14.16. Finished fast OPT passes. (There is nothing left to do.) 3.15. Executing WREDUCE pass (reducing word size of cells). Removed top 3 bits (of 9) from mux cell FpxxAdd.$ternary$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:426$1 ($mux). Removed top 4 bits (of 7) from port B of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:431$5 ($sub). Converting cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:431$5 ($sub) from signed to unsigned. Removed top 1 bits (of 7) from port A of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:431$5 ($sub). Removed top 1 bits (of 3) from port B of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:431$5 ($sub). Removed top 63 bits (of 64) from port B of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:433$6 ($sub). Removed top 28 bits (of 64) from port Y of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:433$6 ($sub). Removed top 28 bits (of 64) from port A of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:433$6 ($sub). Removed top 63 bits (of 64) from port A of cell FpxxAdd.$sshl$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:435$7 ($sshl). Removed top 28 bits (of 64) from port Y of cell FpxxAdd.$sshl$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:435$7 ($sshl). Removed top 6 bits (of 7) from port B of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:436$8 ($add). Removed top 1 bits (of 7) from port Y of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:436$8 ($add). Removed top 1 bits (of 7) from port A of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:436$8 ($add). Removed top 1 bits (of 7) from mux cell FpxxAdd.$ternary$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:438$9 ($mux). Removed top 1 bits (of 7) from port Y of cell FpxxAdd.$not$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:439$10 ($not). Removed top 1 bits (of 7) from port A of cell FpxxAdd.$not$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:439$10 ($not). Removed top 1 bits (of 38) from port A of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:563$12 ($add). Removed top 37 bits (of 38) from port B of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:563$12 ($add). Removed top 2 bits (of 9) from port B of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:564$13 ($sub). Converting cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:564$13 ($sub) from signed to unsigned. Removed top 1 bits (of 9) from port A of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:564$13 ($sub). Removed top 1 bits (of 7) from port B of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:564$13 ($sub). Removed top 1 bits (of 36) from mux cell FpxxAdd.$ternary$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:589$46 ($mux). Removed top 1 bits (of 36) from mux cell FpxxAdd.$ternary$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:590$48 ($mux). Converting cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:591$49 ($sub) from signed to unsigned. Removed top 1 bits (of 9) from port A of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:591$49 ($sub). Removed top 1 bits (of 9) from port B of cell FpxxAdd.$sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:591$49 ($sub). Removed top 8 bits (of 9) from port A of cell FpxxAdd.$le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:593$51 ($le). Removed top 2 bits (of 9) from port A of cell FpxxAdd.$lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:597$55 ($lt). Removed top 2 bits (of 8) from port A of cell FpxxAdd.$lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:597$56 ($lt). Removed top 1 bits (of 36) from mux cell FpxxAdd.$ternary$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:599$58 ($mux). Removed top 1 bits (of 36) from mux cell FpxxAdd.$ternary$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:600$59 ($mux). Removed top 5 bits (of 7) from port B of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:607$63 ($add). Removed top 6 bits (of 7) from port B of cell FpxxAdd.$lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:608$64 ($lt). Removed cell FpxxAdd.$ternary$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:610$68 ($mux). Removed top 1 bits (of 40) from port A of cell FpxxAdd.$not$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:631$72 ($not). Removed top 1 bits (of 40) from port B of cell FpxxAdd.$le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:648$75 ($le). Removed top 7 bits (of 8) from port B of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1299$121 ($add). Removed top 1 bits (of 37) from port A of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1313$127 ($add). Removed top 36 bits (of 37) from port B of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1313$127 ($add). Removed top 7 bits (of 9) from port B of cell FpxxAdd.$add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1328$130 ($add). Removed top 2 bits (of 8) from port B of cell FpxxAdd.$eq$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1329$131 ($eq). Removed top 1 bits (of 7) from mux cell FpxxAdd.$procmux$427 ($mux). Removed top 1 bits (of 3) from mux cell FpxxAdd.$procmux$435 ($mux). Removed top 1 bits (of 36) from FF cell FpxxAdd.$procdff$632 ($dff). Removed top 1 bits (of 36) from FF cell FpxxAdd.$procdff$633 ($dff). Removed top 1 bits (of 36) from FF cell FpxxAdd.$auto$ff.cc:337:slice$643 ($dff). Removed top 1 bits (of 39) from port A of cell FpxxAdd.$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3 ($sshr). Removed top 1 bits (of 36) from port B of cell FpxxAdd.$and$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:604$61 ($and). Removed top 1 bits (of 39) from port A of cell FpxxAdd.$not$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:631$72 ($not). Removed top 1 bits (of 39) from port B of cell FpxxAdd.$le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:648$75 ($le). Removed top 1 bits (of 40) from wire FpxxAdd.n1__mant_b_shift. Removed top 1 bits (of 36) from wire FpxxAdd.n0_mant_b. Removed top 1 bits (of 36) from wire FpxxAdd.n0_mant_a. Removed top 1 bits (of 36) from wire FpxxAdd.n0_mant_a_swap. Removed top 1 bits (of 36) from wire FpxxAdd.n0_mant_b_swap. Removed top 1 bits (of 36) from wire FpxxAdd.n1_n0_mant_a_swap. Removed top 2 bits (of 40) from wire FpxxAdd.n1_mant_a_adj. Removed top 1 bits (of 36) from wire FpxxAdd.n1_n0_mant_b_swap. Removed top 2 bits (of 40) from wire FpxxAdd.n2_n1_mant_a_adj. Removed top 1 bits (of 2) from wire FpxxAdd._zz_n5_exp_add_m_lz_6. Removed top 8 bits (of 9) from wire FpxxAdd._zz_n5_exp_add_m_lz_5. Removed top 1 bits (of 7) from wire FpxxAdd._zz_n1__mant_b_shift_11. Removed top 1 bits (of 7) from wire FpxxAdd._zz_n1__mant_b_shift_10. Removed top 28 bits (of 64) from wire FpxxAdd._zz_n1__mant_b_shift_7. Removed top 1 bits (of 39) from wire FpxxAdd._zz_n1__mant_b_shift_4. Removed top 1 bits (of 39) from wire FpxxAdd._zz_n1_mant_a_adj. 3.16. Executing PEEPOPT pass (run peephole optimizers). 3.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. Removed 0 unused cells and 16 unused wires. 3.18. Executing SHARE pass (SAT-based resource sharing). 3.19. Executing TECHMAP pass (map to technology primitives). 3.19.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 3.19.2. Continuing TECHMAP pass. No more expansions possible. 3.20. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. Removed 0 unused cells and 2 unused wires. 3.22. Executing TECHMAP pass (map to technology primitives). 3.22.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 3.22.2. Continuing TECHMAP pass. No more expansions possible. 3.23. Executing TECHMAP pass (map to technology primitives). 3.23.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. Generating RTLIL representation for module `$__MUL18X18'. Successfully finished Verilog frontend. 3.23.2. Continuing TECHMAP pass. No more expansions possible. 3.24. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top_tommath_add_e8_m35_round_even_sticky_p3: created 0 $alu and 0 $macc cells. Extracting $alu and $macc cells in module FpxxAdd: creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1328$130 ($add). creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1313$127 ($add). creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1299$121 ($add). creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:607$63 ($add). creating $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:592$50 ($sub). creating $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:591$49 ($sub). creating $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:564$13 ($sub). creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:563$12 ($add). creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:442$11 ($add). creating $macc model for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:436$8 ($add). creating $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:433$6 ($sub). creating $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:431$5 ($sub). merging $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:431$5 into $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:607$63. merging $macc model for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:564$13 into $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1328$130. creating $alu model for $macc $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:436$8. creating $alu model for $macc $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:442$11. creating $alu model for $macc $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:563$12. creating $alu model for $macc $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:433$6. creating $alu model for $macc $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:591$49. creating $alu model for $macc $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:592$50. creating $alu model for $macc $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1299$121. creating $alu model for $macc $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1313$127. creating $macc cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:607$63: $auto$alumacc.cc:382:replace_macc$665 creating $macc cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1328$130: $auto$alumacc.cc:382:replace_macc$666 creating $alu model for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1349$134 ($lt): new $alu creating $alu model for $le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:648$75 ($le): new $alu creating $alu model for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:608$64 ($lt): new $alu creating $alu model for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:597$56 ($lt): new $alu creating $alu model for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:597$55 ($lt): new $alu creating $alu model for $le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:593$51 ($le): new $alu creating $alu cell for $le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:593$51: $auto$alumacc.cc:512:replace_alu$673 creating $alu cell for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:597$55: $auto$alumacc.cc:512:replace_alu$684 creating $alu cell for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:597$56: $auto$alumacc.cc:512:replace_alu$691 creating $alu cell for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:608$64: $auto$alumacc.cc:512:replace_alu$696 creating $alu cell for $le$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:648$75: $auto$alumacc.cc:512:replace_alu$703 creating $alu cell for $lt$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1349$134: $auto$alumacc.cc:512:replace_alu$712 creating $alu cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1313$127: $auto$alumacc.cc:512:replace_alu$717 creating $alu cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:1299$121: $auto$alumacc.cc:512:replace_alu$720 creating $alu cell for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:592$50: $auto$alumacc.cc:512:replace_alu$723 creating $alu cell for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:591$49: $auto$alumacc.cc:512:replace_alu$726 creating $alu cell for $sub$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:433$6: $auto$alumacc.cc:512:replace_alu$729 creating $alu cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:563$12: $auto$alumacc.cc:512:replace_alu$732 creating $alu cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:442$11: $auto$alumacc.cc:512:replace_alu$735 creating $alu cell for $add$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:436$8: $auto$alumacc.cc:512:replace_alu$738 created 14 $alu and 2 $macc cells. 3.25. Executing OPT pass (performing simple optimizations). 3.25.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.25.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 6 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 245 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 0 cells. 3.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_add_e8_m35_round_even_sticky_p3.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \FpxxAdd.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/3 on $pmux $procmux$431. Removed 1 multiplexer ports. 3.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing cells in module \FpxxAdd. Performed a total of 0 changes. 3.25.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 6 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 245 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 0 cells. 3.25.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$647 ($dff) from module FpxxAdd. 3.25.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. Removed 3 unused cells and 14 unused wires. 3.25.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.25.9. Rerunning OPT passes. (Maybe there is more to do..) 3.25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_add_e8_m35_round_even_sticky_p3.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \FpxxAdd.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port A of cell $ternary$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:608$65: \_zz_n1__mant_b_shift -> { 1'0 \_zz_n1__mant_b_shift [5:0] } Analyzing evaluation results. Removed 0 multiplexer ports. 3.25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing cells in module \FpxxAdd. Performed a total of 0 changes. 3.25.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 6 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 240 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 0 cells. 3.25.13. Executing OPT_DFF pass (perform DFF optimizations). 3.25.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. 3.25.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.25.16. Finished fast OPT passes. (There is nothing left to do.) 3.26. Executing MEMORY pass. 3.26.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 3.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 3.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 3.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 3.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 3.26.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. 3.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 3.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 3.26.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. 3.26.10. Executing MEMORY_COLLECT pass (generating $mem cells). 3.27. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. 3.28. Executing MEMORY_LIBMAP pass (mapping memories to cells). 3.29. Executing TECHMAP pass (map to technology primitives). 3.29.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 3.29.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/brams_map_16kd.v' to AST representation. Generating RTLIL representation for module `$__DP16KD_'. Generating RTLIL representation for module `$__PDPW16KD_'. Successfully finished Verilog frontend. 3.29.3. Continuing TECHMAP pass. No more expansions possible. 3.30. Executing OPT pass (performing simple optimizations). 3.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 6 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 243 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 0 cells. 3.30.3. Executing OPT_DFF pass (perform DFF optimizations). 3.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. Removed 0 unused cells and 9 unused wires. 3.30.5. Finished fast OPT passes. 3.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 3.32. Executing OPT pass (performing simple optimizations). 3.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 6 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 243 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 0 cells. 3.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_add_e8_m35_round_even_sticky_p3.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \FpxxAdd.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing cells in module \FpxxAdd. Consolidated identical input bits for $mux cell $procmux$588: Old ports: A={ 2'11 $auto$opt_expr.cc:206:group_cell_inputs$883 4'1111 }, B={ 2'00 \n2_n1_mant_a_adj [37:3] 4'0001 }, Y=$2\n2__mant_a_opt_inv[40:0] New ports: A={ $auto$opt_expr.cc:206:group_cell_inputs$883 1'1 }, B={ \n2_n1_mant_a_adj [37:3] 1'0 }, Y={ $2\n2__mant_a_opt_inv[40:0] [38:4] $2\n2__mant_a_opt_inv[40:0] [1] } New connections: { $2\n2__mant_a_opt_inv[40:0] [40:39] $2\n2__mant_a_opt_inv[40:0] [3:2] $2\n2__mant_a_opt_inv[40:0] [0] } = { $2\n2__mant_a_opt_inv[40:0] [1] $2\n2__mant_a_opt_inv[40:0] [1] $2\n2__mant_a_opt_inv[40:0] [1] $2\n2__mant_a_opt_inv[40:0] [1] 1'1 } Consolidated identical input bits for $mux cell $procmux$579: Old ports: A={ 1'0 \n2_n1_mant_b_adj [38:0] 1'1 }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$879 1'1 }, Y=$2\n2__mant_b_opt_inv[40:0] New ports: A={ 1'0 \n2_n1_mant_b_adj [38:0] }, B={ 1'1 $auto$opt_expr.cc:206:group_cell_inputs$879 }, Y=$2\n2__mant_b_opt_inv[40:0] [40:1] New connections: $2\n2__mant_b_opt_inv[40:0] [0] = 1'1 Consolidated identical input bits for $mux cell $procmux$431: Old ports: A={ 2'00 \_zz_switch_Misc_l241_85 [1:0] }, B={ 2'01 \_zz__zz_switch_Misc_l241_92_1 }, Y=\_zz_switch_Misc_l241_92 New ports: A={ 1'0 \_zz_switch_Misc_l241_85 [1:0] }, B={ 1'1 \_zz__zz_switch_Misc_l241_92_1 }, Y=\_zz_switch_Misc_l241_92 [2:0] New connections: \_zz_switch_Misc_l241_92 [3] = 1'0 Consolidated identical input bits for $mux cell $ternary$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:608$65: Old ports: A={ 1'0 \_zz_n1__mant_b_shift [5:0] }, B=7'0000000, Y=\_zz_n1__mant_b_shift_1 New ports: A=\_zz_n1__mant_b_shift [5:0], B=6'000000, Y=\_zz_n1__mant_b_shift_1 [5:0] New connections: \_zz_n1__mant_b_shift_1 [6] = 1'0 Optimizing cells in module \FpxxAdd. Consolidated identical input bits for $mux cell $procmux$594: Old ports: A=$2\n2__mant_a_opt_inv[40:0], B={ 2'00 \n2_n1_mant_a_adj [37:3] 4'0000 }, Y=\n3_n2_mant_a_opt_inv New ports: A={ $2\n2__mant_a_opt_inv[40:0] [38:4] $2\n2__mant_a_opt_inv[40:0] [1] 1'1 }, B={ \n2_n1_mant_a_adj [37:3] 2'00 }, Y={ \n3_n2_mant_a_opt_inv [38:4] \n3_n2_mant_a_opt_inv [1:0] } New connections: { \n3_n2_mant_a_opt_inv [40:39] \n3_n2_mant_a_opt_inv [3:2] } = { \n3_n2_mant_a_opt_inv [1] \n3_n2_mant_a_opt_inv [1] \n3_n2_mant_a_opt_inv [1] \n3_n2_mant_a_opt_inv [1] } Optimizing cells in module \FpxxAdd. Performed a total of 5 changes. 3.32.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 6 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 243 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 0 cells. 3.32.6. Executing OPT_DFF pass (perform DFF optimizations). 3.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. 3.32.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.32.9. Rerunning OPT passes. (Maybe there is more to do..) 3.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_add_e8_m35_round_even_sticky_p3.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \FpxxAdd.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing cells in module \FpxxAdd. Performed a total of 0 changes. 3.32.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 6 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 240 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 0 cells. 3.32.13. Executing OPT_DFF pass (perform DFF optimizations). 3.32.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. Removed 1 unused cells and 4 unused wires. 3.32.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.32.16. Rerunning OPT passes. (Maybe there is more to do..) 3.32.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top_tommath_add_e8_m35_round_even_sticky_p3.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \FpxxAdd.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 3.32.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing cells in module \FpxxAdd. Performed a total of 0 changes. 3.32.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 6 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 238 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 0 cells. 3.32.20. Executing OPT_DFF pass (perform DFF optimizations). 3.32.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. 3.32.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.32.23. Finished fast OPT passes. (There is nothing left to do.) 3.33. Executing TECHMAP pass (map to technology primitives). 3.33.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 3.33.2. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. Generating RTLIL representation for module `\_80_ccu2c_alu'. Successfully finished Verilog frontend. 3.33.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $not. Using template $paramod$35a69cb9a70c12a16833c695168dfe15d5378044\_80_ccu2c_alu for cells of type $alu. Using template $paramod$constmap:430d97977ff0ea3dfd4419fb0290c4b5047d4855$paramod$24b5e7daeeeebc9a3f247d418bb0b333ebbb477f\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshl. Using template $paramod$551b76e8ef61037a5e36afc4637da8405d937c47\_80_ccu2c_alu for cells of type $alu. Using template $paramod$constmap:2dee5fbd0b8e43da282b98a312c70fe60c3e4ed4$paramod$98fbc4f30f247db41cb506bc695e4f8333e17956\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshl. Using template $paramod$31052fbbb32da37efa794482d793b44d51a048f2\_80_ccu2c_alu for cells of type $alu. Using template $paramod$4ccbe221165818e15f326ddee3d1183c7924e12f\_80_ccu2c_alu for cells of type $alu. Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\_80_ccu2c_alu for cells of type $alu. Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ccu2c_alu for cells of type $alu. Using template $paramod$8fa3574f97453f550c94521e755fae442430a32c\_80_ccu2c_alu for cells of type $alu. Using template $paramod$00298f3f8094950cb9a5ff2fda48d0d8bde8806c\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $reduce_and. Using template $paramod$010bffa9f8d85691a30425b91faf138dfe277c60\_80_ccu2c_alu for cells of type $alu. Using template $paramod$150d098cb9cca1819459bc5073194c8c53d2862d\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $xor. Using template $paramod$27059fe7c7204c4ae16c60bdf9e25f6ae41632c4\_80_ccu2c_alu for cells of type $alu. Using template $paramod$003256218b736a5f72fe70a6e5006b2214b99da4\_80_ccu2c_alu for cells of type $alu. Using extmapper maccmap for cells of type $macc_v2. add \n5_n4_exp_add_adj (8 bits, unsigned) add { 1'0 \_zz_n5_mant_rounded [36] } (2 bits, signed) sub \n5_n4_lz (6 bits, unsigned) packed 1 (1) bits / 1 words into adder tree add \n1_n0_exp_diff (6 bits, unsigned) add 7'1111110 (7 bits, unsigned) Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $dff. Using template $paramod$constmap:573c733353fc41645c0045ff576523fe904eb125$paramod$0129a18ec0010fbc77716256828a35341fa99e18\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $logic_or. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $pmux. Using extmapper simplemap for cells of type $adff. Using template $paramod$dbcdc7e8aa1a4080cea2deda6fdc8772064f4d90\_80_ccu2c_alu for cells of type $alu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000001001 for cells of type $fa. Using template $paramod$d2fa05d38998afabc6d4f34471305d0af4b8b2df\_80_ccu2c_alu for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using extmapper simplemap for cells of type $or. No more expansions possible. 3.34. Executing OPT pass (performing simple optimizations). 3.34.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.34.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 135 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 3012 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Computing hashes of 2861 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Computing hashes of 2843 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Computing hashes of 2835 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Computing hashes of 2831 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Computing hashes of 2829 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Computing hashes of 2827 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Computing hashes of 2825 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 187 cells. 3.34.3. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:337:slice$2713 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [6], Q = \n2_n1_mant_b_adj [6], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2714 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [7], Q = \n2_n1_mant_b_adj [7], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2715 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [8], Q = \n2_n1_mant_b_adj [8], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2716 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [9], Q = \n2_n1_mant_b_adj [9], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2717 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [10], Q = \n2_n1_mant_b_adj [10], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2718 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [11], Q = \n2_n1_mant_b_adj [11], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2719 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [12], Q = \n2_n1_mant_b_adj [12], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2720 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [13], Q = \n2_n1_mant_b_adj [13], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2721 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [14], Q = \n2_n1_mant_b_adj [14], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2722 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [15], Q = \n2_n1_mant_b_adj [15], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2723 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [16], Q = \n2_n1_mant_b_adj [16], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2724 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [17], Q = \n2_n1_mant_b_adj [17], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2725 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [18], Q = \n2_n1_mant_b_adj [18], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2726 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [19], Q = \n2_n1_mant_b_adj [19], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2727 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [20], Q = \n2_n1_mant_b_adj [20], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2728 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [21], Q = \n2_n1_mant_b_adj [21], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2729 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$10\buffer[38:0] [22], Q = \n2_n1_mant_b_adj [22], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2730 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$10\buffer[38:0] [23], Q = \n2_n1_mant_b_adj [23], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2731 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$10\buffer[38:0] [24], Q = \n2_n1_mant_b_adj [24], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2732 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$10\buffer[38:0] [25], Q = \n2_n1_mant_b_adj [25], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2733 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$10\buffer[38:0] [26], Q = \n2_n1_mant_b_adj [26], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2734 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$10\buffer[38:0] [27], Q = \n2_n1_mant_b_adj [27], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2735 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$10\buffer[38:0] [28], Q = \n2_n1_mant_b_adj [28], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2736 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$10\buffer[38:0] [29], Q = \n2_n1_mant_b_adj [29], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2737 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$10\buffer[38:0] [30], Q = \n2_n1_mant_b_adj [30], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2738 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$10\buffer[38:0] [31], Q = \n2_n1_mant_b_adj [31], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2739 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [32], Q = \n2_n1_mant_b_adj [32], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2740 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [33], Q = \n2_n1_mant_b_adj [33], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2741 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [34], Q = \n2_n1_mant_b_adj [34], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2742 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [35], Q = \n2_n1_mant_b_adj [35], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2743 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [36], Q = \n2_n1_mant_b_adj [36], rval = 1'0). Adding SRST signal on $auto$ff.cc:337:slice$2744 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$13\buffer[38:0] [37], Q = \n2_n1_mant_b_adj [37], rval = 1'0). Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$2745 ($_SDFF_PP0_) from module FpxxAdd. 3.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. Removed 551 unused cells and 1404 unused wires. 3.34.5. Rerunning OPT passes. (Removed registers in this run.) 3.34.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.34.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 135 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 2312 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Computing hashes of 2281 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Computing hashes of 2272 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 40 cells. 3.34.8. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:337:slice$8160 ($_SDFF_PP0_) from module FpxxAdd (D = $techmap$sshr$/mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/src/tommath_add_e8_m35_round_even_sticky_p3.v:429$3.$10\buffer[38:0] [32], Q = \n2_n1_mant_b_adj [32], rval = 1'0). 3.34.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. Removed 1 unused cells and 40 unused wires. 3.34.10. Rerunning OPT passes. (Removed registers in this run.) 3.34.11. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.34.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 135 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 2272 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 0 cells. 3.34.13. Executing OPT_DFF pass (perform DFF optimizations). 3.34.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. 3.34.15. Finished fast OPT passes. 3.35. Executing ABC pass (technology mapping using ABC). 3.35.1. Summary of detected clock domains: 3 cells in clk=\clk, en={ }, arst={ }, srst=\rst 132 cells in clk=\clk, en={ }, arst={ }, srst={ } 3.35.2. Extracting gate netlist of module `\top_tommath_add_e8_m35_round_even_sticky_p3' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by \rst 3.35.3. Extracting gate netlist of module `\top_tommath_add_e8_m35_round_even_sticky_p3' to `/input.blif'.. Found matching posedge clock domain: \clk 3.35.3.1. Executed ABC. Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 2 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.3.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 4 ABC RESULTS: DFF cells: 2 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 2 ABC RESULTS: output signals: 2 Removing temp directory. 3.35.3.1. Executed ABC. Extracted 132 gates and 264 wires to a netlist network with 132 inputs and 132 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 132 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.3.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 264 ABC RESULTS: DFF cells: 132 ABC RESULTS: internal signals: 0 ABC RESULTS: input signals: 132 ABC RESULTS: output signals: 132 Removing temp directory. 3.35.4. Summary of detected clock domains: 3 cells in clk=\clk, en={ }, arst=\reset, srst={ } 63 cells in clk=\clk, en={ }, arst={ }, srst=\n1_n0_exp_diff_ovfl 55 cells in clk=\clk, en={ }, arst={ }, srst=$auto$opt_dff.cc:275:combine_resets$8091 5 cells in clk=\clk, en={ }, arst={ }, srst=$auto$opt_dff.cc:275:combine_resets$8191 115 cells in clk=\clk, en={ }, arst={ }, srst=$auto$opt_dff.cc:275:combine_resets$8011 2031 cells in clk=\clk, en={ }, arst={ }, srst={ } 3.35.5. Extracting gate netlist of module `\FpxxAdd' to `/input.blif'.. Found matching posedge clock domain: \clk, asynchronously reset by \reset 3.35.6. Extracting gate netlist of module `\FpxxAdd' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by \n1_n0_exp_diff_ovfl 3.35.7. Extracting gate netlist of module `\FpxxAdd' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by $auto$opt_dff.cc:275:combine_resets$8091 3.35.8. Extracting gate netlist of module `\FpxxAdd' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by $auto$opt_dff.cc:275:combine_resets$8191 3.35.9. Extracting gate netlist of module `\FpxxAdd' to `/input.blif'.. Found matching posedge clock domain: \clk, synchronously reset by $auto$opt_dff.cc:275:combine_resets$8011 3.35.10. Extracting gate netlist of module `\FpxxAdd' to `/input.blif'.. Found matching posedge clock domain: \clk 3.35.10.1. Executed ABC. Extracted 3 gates and 4 wires to a netlist network with 1 inputs and 1 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.10.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 4 ABC RESULTS: DFF cells: 3 ABC RESULTS: internal signals: 2 ABC RESULTS: input signals: 1 ABC RESULTS: output signals: 1 Removing temp directory. 3.35.10.1. Executed ABC. Extracted 61 gates and 106 wires to a netlist network with 45 inputs and 15 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.10.2. Re-integrating ABC results. ABC RESULTS: AND cells: 9 ABC RESULTS: ANDNOT cells: 3 ABC RESULTS: BUF cells: 8 ABC RESULTS: DFF cells: 9 ABC RESULTS: NAND cells: 5 ABC RESULTS: NOR cells: 18 ABC RESULTS: NOT cells: 2 ABC RESULTS: XNOR cells: 5 ABC RESULTS: XOR cells: 4 ABC RESULTS: internal signals: 46 ABC RESULTS: input signals: 45 ABC RESULTS: output signals: 15 Removing temp directory. 3.35.10.1. Executed ABC. Extracted 50 gates and 72 wires to a netlist network with 22 inputs and 30 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.10.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 20 ABC RESULTS: DFF cells: 10 ABC RESULTS: NAND cells: 1 ABC RESULTS: XNOR cells: 10 ABC RESULTS: XOR cells: 10 ABC RESULTS: internal signals: 20 ABC RESULTS: input signals: 22 ABC RESULTS: output signals: 30 Removing temp directory. 3.35.10.1. Executed ABC. Extracted 5 gates and 9 wires to a netlist network with 4 inputs and 3 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.10.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 2 ABC RESULTS: DFF cells: 1 ABC RESULTS: NAND cells: 1 ABC RESULTS: XNOR cells: 1 ABC RESULTS: XOR cells: 1 ABC RESULTS: internal signals: 2 ABC RESULTS: input signals: 4 ABC RESULTS: output signals: 3 Removing temp directory. 3.35.10.1. Executed ABC. Extracted 105 gates and 149 wires to a netlist network with 44 inputs and 63 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.10.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 42 ABC RESULTS: DFF cells: 21 ABC RESULTS: NAND cells: 1 ABC RESULTS: XNOR cells: 21 ABC RESULTS: XOR cells: 21 ABC RESULTS: internal signals: 42 ABC RESULTS: input signals: 44 ABC RESULTS: output signals: 63 Removing temp directory. 3.35.10.1. Executed ABC. Extracted 1914 gates and 2235 wires to a netlist network with 319 inputs and 339 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: Warning: 190 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + retime -o -D 1 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 1 ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.35.10.2. Re-integrating ABC results. ABC RESULTS: AND cells: 383 ABC RESULTS: ANDNOT cells: 80 ABC RESULTS: BUF cells: 116 ABC RESULTS: DFF cells: 215 ABC RESULTS: MUX cells: 384 ABC RESULTS: NAND cells: 294 ABC RESULTS: NOR cells: 87 ABC RESULTS: NOT cells: 56 ABC RESULTS: OR cells: 73 ABC RESULTS: ORNOT cells: 51 ABC RESULTS: XNOR cells: 42 ABC RESULTS: XOR cells: 4 ABC RESULTS: internal signals: 1577 ABC RESULTS: input signals: 319 ABC RESULTS: output signals: 339 Removing temp directory. Removing global temp directory. 3.36. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. Removed 0 unused cells and 2218 unused wires. 3.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 3.38. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top_tommath_add_e8_m35_round_even_sticky_p3'. Computing hashes of 135 cells of `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding duplicate cells in `\top_tommath_add_e8_m35_round_even_sticky_p3'. Finding identical cells in module `\FpxxAdd'. Computing hashes of 1960 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Computing hashes of 1957 cells of `\FpxxAdd'. Finding duplicate cells in `\FpxxAdd'. Removed a total of 3 cells. 3.39. Executing TECHMAP pass (map to technology primitives). 3.39.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 3.39.2. Continuing TECHMAP pass. Using template $_DFF_PP0_ for cells of type $_DFF_PP0_. Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. No more expansions possible. 3.40. Executing OPT_EXPR pass (perform const folding). Optimizing module top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing module FpxxAdd. 3.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). 3.42. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in top_tommath_add_e8_m35_round_even_sticky_p3. Handling GSR in FpxxAdd. 3.43. Executing ATTRMVCP pass (move or copy attributes). 3.44. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top_tommath_add_e8_m35_round_even_sticky_p3.. Finding unused cells or wires in module \FpxxAdd.. Removed 0 unused cells and 1621 unused wires. 3.45. Executing ABC pass (technology mapping using ABC). 3.45.1. Extracting gate netlist of module `\top_tommath_add_e8_m35_round_even_sticky_p3' to `/input.blif'.. 3.45.1.1. Executed ABC. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 3.45.2. Extracting gate netlist of module `\FpxxAdd' to `/input.blif'.. 3.45.2.1. Executed ABC. Extracted 1564 gates and 2043 wires to a netlist network with 479 inputs and 408 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.45.2.2. Re-integrating ABC results. ABC RESULTS: AND cells: 397 ABC RESULTS: ANDNOT cells: 84 ABC RESULTS: MUX cells: 376 ABC RESULTS: NAND cells: 338 ABC RESULTS: NOR cells: 87 ABC RESULTS: NOT cells: 22 ABC RESULTS: OR cells: 78 ABC RESULTS: ORNOT cells: 73 ABC RESULTS: XNOR cells: 103 ABC RESULTS: XOR cells: 5 ABC RESULTS: internal signals: 1156 ABC RESULTS: input signals: 479 ABC RESULTS: output signals: 408 Removing temp directory. Removing global temp directory. 3.46. Executing TECHMAP pass (map to technology primitives). 3.46.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/latches_map.v' to AST representation. Generating RTLIL representation for module `$_DLATCH_N_'. Generating RTLIL representation for module `$_DLATCH_P_'. Successfully finished Verilog frontend. 3.46.2. Continuing TECHMAP pass. No more expansions possible. 3.47. Executing ABC pass (technology mapping using ABC). 3.47.1. Summary of detected clock domains: 135 cells in clk={ }, en={ }, arst={ }, srst={ } 3.47.2. Extracting gate netlist of module `\top_tommath_add_e8_m35_round_even_sticky_p3' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 3.47.2.1. Executed ABC. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Don't call ABC as there is nothing to map. Removing temp directory. 3.47.3. Summary of detected clock domains: 1956 cells in clk={ }, en={ }, arst={ }, srst={ } 3.47.4. Extracting gate netlist of module `\FpxxAdd' to `/input.blif'.. No matching clock domain found. Not extracting any FF cells. 3.47.4.1. Executed ABC. Extracted 1563 gates and 2042 wires to a netlist network with 479 inputs and 408 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled May 12 2026 04:40:36) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_lut /lutdefs.txt ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + dress /input.blif ABC: Total number of equiv classes = 743. ABC: Participating nodes from both networks = 1500. ABC: Participating nodes from the first network = 744. ( 88.47 % of nodes) ABC: Participating nodes from the second network = 756. ( 89.89 % of nodes) ABC: Node pairs (any polarity) = 744. ( 88.47 % of names can be moved) ABC: Node pairs (same polarity) = 523. ( 62.19 % of names can be moved) ABC: Total runtime = 0.09 sec ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 3.47.4.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 840 ABC RESULTS: internal signals: 1155 ABC RESULTS: input signals: 479 ABC RESULTS: output signals: 408 Removing temp directory. Removing global temp directory. Removed 0 unused cells and 4017 unused wires. 3.48. Executing TECHMAP pass (map to technology primitives). 3.48.1. Executing Verilog-2005 frontend: /mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v Parsing Verilog input from `/mnt/storage/synth_eval/oss-cad-suite/lib/../share/yosys/lattice/cells_map_trellis.v' to AST representation. Generating RTLIL representation for module `$_DFF_N_'. Generating RTLIL representation for module `$_DFF_P_'. Generating RTLIL representation for module `$_DFFE_NN_'. Generating RTLIL representation for module `$_DFFE_PN_'. Generating RTLIL representation for module `$_DFFE_NP_'. Generating RTLIL representation for module `$_DFFE_PP_'. Generating RTLIL representation for module `$_DFF_NP0_'. Generating RTLIL representation for module `$_DFF_NP1_'. Generating RTLIL representation for module `$_DFF_PP0_'. Generating RTLIL representation for module `$_DFF_PP1_'. Generating RTLIL representation for module `$_SDFF_NP0_'. Generating RTLIL representation for module `$_SDFF_NP1_'. Generating RTLIL representation for module `$_SDFF_PP0_'. Generating RTLIL representation for module `$_SDFF_PP1_'. Generating RTLIL representation for module `$_DFFE_NP0P_'. Generating RTLIL representation for module `$_DFFE_NP1P_'. Generating RTLIL representation for module `$_DFFE_PP0P_'. Generating RTLIL representation for module `$_DFFE_PP1P_'. Generating RTLIL representation for module `$_DFFE_NP0N_'. Generating RTLIL representation for module `$_DFFE_NP1N_'. Generating RTLIL representation for module `$_DFFE_PP0N_'. Generating RTLIL representation for module `$_DFFE_PP1N_'. Generating RTLIL representation for module `$_SDFFE_NP0P_'. Generating RTLIL representation for module `$_SDFFE_NP1P_'. Generating RTLIL representation for module `$_SDFFE_PP0P_'. Generating RTLIL representation for module `$_SDFFE_PP1P_'. Generating RTLIL representation for module `$_SDFFE_NP0N_'. Generating RTLIL representation for module `$_SDFFE_NP1N_'. Generating RTLIL representation for module `$_SDFFE_PP0N_'. Generating RTLIL representation for module `$_SDFFE_PP1N_'. Generating RTLIL representation for module `$_ALDFF_NP_'. Generating RTLIL representation for module `$_ALDFF_PP_'. Generating RTLIL representation for module `$_ALDFFE_NPN_'. Generating RTLIL representation for module `$_ALDFFE_NPP_'. Generating RTLIL representation for module `$_ALDFFE_PPN_'. Generating RTLIL representation for module `$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `$lut'. Successfully finished Verilog frontend. 3.48.2. Continuing TECHMAP pass. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod$af763bca85949884aefa417266a961f9c91132de$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$3ef319efded008eed5f930491a82ee1762b3c0df$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$55ea4d369b62b80ca31c97667e9ba7aa7693ff2c$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod$d0c781e4a36ac0013b2d78b8ee2ce48e393ac618$lut for cells of type $lut. Using template $paramod$e86054c31a8f8bd607e0c7634fce3d3ef046bd23$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. Using template $paramod$345e594e3e86fb5714f53304e99d8ef40a9499ad$lut for cells of type $lut. Using template $paramod$d94f7d3127937b5dc7a66ea8cc409d7cf91bc488$lut for cells of type $lut. Using template $paramod$4c95bdff5d842ab85bf332a23fe200c407cf9d5b$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod$fe4be41ca99978dcdb8f8c64fa471e60bfede3a5$lut for cells of type $lut. Using template $paramod$c59732e0777887c330ebe0863f73e820579c73da$lut for cells of type $lut. Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1$lut for cells of type $lut. Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542$lut for cells of type $lut. Using template $paramod$d6cf0a4b6f6ccd87588da28c41b5b6c258da2509$lut for cells of type $lut. Using template $paramod$267497b3f56977867d129f4ce6dbb4f66333a3b6$lut for cells of type $lut. Using template $paramod$43cab06b29c2f8f5d9ea07f90c6884a8069b9c72$lut for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut. Using template $paramod$71d951b20e73043168c1656217d126e617052faa$lut for cells of type $lut. Using template $paramod$8e34e782f9ef59eee1c50ab93ef54fb5ebb3e307$lut for cells of type $lut. Using template $paramod$46aa79a8c20e4a0c55b9a14d851111ee1ddc630d$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$1a6ea9151e749fe94446f4fb089a0baf2adde081$lut for cells of type $lut. Using template $paramod$052ca015f1400ebf950f85d5f181f7a5865c336c$lut for cells of type $lut. Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011$lut for cells of type $lut. Using template $paramod$ebf910d4087eb067cc21d5b758d87e5b874b2f90$lut for cells of type $lut. Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288$lut for cells of type $lut. Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$ba05b8a1a425003df083aea0e69541f5cbdc68f2$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. Using template $paramod$f44e1eab45e047e709d5dfed32527eb1f7745488$lut for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut. Using template $paramod$d52cb446bc89fafcaa49f2b908e540f513a4d760$lut for cells of type $lut. Using template $paramod$9584aa2727eb7e8f18fd83f6b4dce96c8937579b$lut for cells of type $lut. Using template $paramod$cd6c4b4da6d8737b72fd2dc8f5d83d8967445809$lut for cells of type $lut. Using template $paramod$cd05f04889088c47a0a5abae8c2d644fd314805e$lut for cells of type $lut. Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba$lut for cells of type $lut. Using template $paramod$d1022fa7cdd5136084608347e8cb6964dc95123e$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$ec8f389d3b0c4ac15bc66a5f07b2ffe4e8f89d74$lut for cells of type $lut. Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa$lut for cells of type $lut. Using template $paramod$040791c04ea86e31acd675021d95f3dbcc5a17ea$lut for cells of type $lut. Using template $paramod$cbd58858e3882f0938c6a2ef4a7555808a69fcaa$lut for cells of type $lut. Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5$lut for cells of type $lut. Using template $paramod$854cb5e72c2ab19ae4eb96a2afe38e4d2b7f8e27$lut for cells of type $lut. Using template $paramod$868876e6fbf32fc8a062709fbe4f313e5420f9a8$lut for cells of type $lut. Using template $paramod$f63fe32f78d5f3c5de711945c592c8c5ec2303ae$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$f3cb6f7d2ed2f8804f8cf4ebe92aa5d1a7b5d611$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$7b7877bc6d511c605e59081d29c32f7eb7eba305$lut for cells of type $lut. Using template $paramod$6a34cd5b50e324824168b4186d0b04ba5e83b039$lut for cells of type $lut. Using template $paramod$1a64f21ea15b05b7fc930804a66f6689ebbd6394$lut for cells of type $lut. Using template $paramod$4aaf6434b027bbf943d2a203e1697ba4b20c1592$lut for cells of type $lut. Using template $paramod$7f8c1e083929502ef137736f54435c7ebf8aab7d$lut for cells of type $lut. Using template $paramod$33c1b38a495cb5b629be9643a1b749c5a8d8a8da$lut for cells of type $lut. Using template $paramod$09194da5f2c8e08bed8f609fd0e254d8629b24b3$lut for cells of type $lut. Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc$lut for cells of type $lut. Using template $paramod$6db0b990494a79d755d22c84bb4f8db411b424ea$lut for cells of type $lut. Using template $paramod$c7d224180c69c0d5fbef7598cd9ab1e40bba59d7$lut for cells of type $lut. Using template $paramod$56d36648044d0bf0f892c2050a60c21ad090a3b1$lut for cells of type $lut. Using template $paramod$fc820968f8a52f0e175e7c980fdbf752d7af351f$lut for cells of type $lut. Using template $paramod$c9259688dfaffa396aaff58d59279135aa54dabb$lut for cells of type $lut. Using template $paramod$b6688cf2da3a849aa71010a626a9619f3de35fa5$lut for cells of type $lut. Using template $paramod$2d3ba667e1bb663616320ee027494ac84a318704$lut for cells of type $lut. Using template $paramod$0f52647588235a7349ddd3f3432c9ac1e33ad9e1$lut for cells of type $lut. Using template $paramod$b062bca4221cf547385aa6b9bdf170b591219686$lut for cells of type $lut. Using template $paramod$048d4aa2263b685fba6c6b0d38f6224df0dc3042$lut for cells of type $lut. Using template $paramod$494cbca903b9af44b925758232af52ad14c00140$lut for cells of type $lut. Using template $paramod$a4610de96840032448d91e86fc7c4f7d845a4540$lut for cells of type $lut. Using template $paramod$a4df2b5be2b644499880e088a11556935f22b401$lut for cells of type $lut. Using template $paramod$8b367233aef4cc96995cd878ca7655b761db5ed6$lut for cells of type $lut. Using template $paramod$d2e6d37235ab843778c678747f5760d5e87de899$lut for cells of type $lut. Using template $paramod$33a01f71ce1120f8d5dbc904e37771e37d5e6f4e$lut for cells of type $lut. Using template $paramod$d07e6f78e690df8ae9a58e59314df836e41fc9c9$lut for cells of type $lut. Using template $paramod$a383eec00d339ff2318773b66d8a893c3986f4d3$lut for cells of type $lut. Using template $paramod$6d494330fd261ad16788e47f8e3f9eccfab42476$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut. Using template $paramod$ad3a97108c9f4d10f8acfa309b668b9455d3d733$lut for cells of type $lut. Using template $paramod$703a13a751e631ef123f38f7d2125aeabec0f94c$lut for cells of type $lut. Using template $paramod$933f4f3e373a784da64d137def3625bdd36d1695$lut for cells of type $lut. Using template $paramod$af93a13affe53c4f5a06fcdc671398ec67c09fc3$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut. Using template $paramod$1190cb0eedfd6f6ea6f0df73b4975e9de5820eb6$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod$2625f1d5feaeb525cf0a725b0365cca8d070effd$lut for cells of type $lut. Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2$lut for cells of type $lut. Using template $paramod$ad823946862e656cf7f96d606b18b8f972dc6d6c$lut for cells of type $lut. Using template $paramod$a02aa475020dd7ab0f723d2eecf34d2b00f64605$lut for cells of type $lut. Using template $paramod$1285796a813c4979d4135797f15991ce9ef18181$lut for cells of type $lut. Using template $paramod$96ded5e2c67999481e15c29a47cf2d5014acc000$lut for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut. Using template $paramod$29afb7ea1c761a1e022adb061ff4873ea3d5d649$lut for cells of type $lut. Using template $paramod$7a988de7554d6c5e09a742c0a2d36472e50c73b1$lut for cells of type $lut. Using template $paramod$8eb41c7dd3e946d2e3b66574f23f2c980395454e$lut for cells of type $lut. Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5$lut for cells of type $lut. Using template $paramod$4bf9dd1982798e5f3593c2885638870535a3f381$lut for cells of type $lut. Using template $paramod$a99abd614bd6fe1cabf1d4224511463f736b08c5$lut for cells of type $lut. Using template $paramod$cd0c2a3d5302372e3760f1a1037771a8cae61f4b$lut for cells of type $lut. Using template $paramod$a616192409c5a9e813bb7653dd0023b96d60b6e2$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut. Using template $paramod$cbfd30b70b4f0ac8dd1d3ed758215fbf49783a3b$lut for cells of type $lut. Using template $paramod$38f9bf4dd2329347b8471f0a98443dd323386889$lut for cells of type $lut. Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9$lut for cells of type $lut. Using template $paramod$5d4f83c6afad2fcdedc550e36d8f6afb5c85a2d9$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. Using template $paramod$979b7ee0d33f001d0cf3a713a590cc783b5c6182$lut for cells of type $lut. Using template $paramod$778cfa89a311116b4664a0be7522bd19e4c50232$lut for cells of type $lut. Using template $paramod$7724c45ed4c7630287ed4bf5f0cac6957aa6bc69$lut for cells of type $lut. Using template $paramod$02eefd9b74acf66558bff242fcbe62a514559f6a$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110001 for cells of type $lut. Using template $paramod$7295da7c5b19f528a428229f2570e0a23ad372af$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$e0bde73e598487237493c8a43ca52c95a3727354$lut for cells of type $lut. Using template $paramod$8c2c1e59c8876a3c2b20cc33cb8585da498e9286$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111000 for cells of type $lut. Using template $paramod$e5f53fb2cb3e702c9422ebddd3ba952e5a8f3401$lut for cells of type $lut. Using template $paramod$70ebb6cf5bc7d63c5c1a98ccefefa2af79e8f2a9$lut for cells of type $lut. Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. Using template $paramod$fa4f9b366e9253c4a2a22fe16973aa8a9118e5d1$lut for cells of type $lut. Using template $paramod$cc08dba3aac8677e797984bdf18a09dd37547dd3$lut for cells of type $lut. Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14$lut for cells of type $lut. Using template $paramod$82a829e63f420d967ac0993f25cc70667cca902d$lut for cells of type $lut. Using template $paramod$7c9db00ac3840ff315c6e2d674c34f83bb8d42d0$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$b297295e19b03521716155b85537bbe86d6a9ae6$lut for cells of type $lut. Using template $paramod$107906fddf7d89ab854e4846eb6fd13bd75a6fed$lut for cells of type $lut. Using template $paramod$a50be0e6fa3a01511bb234559cb74fb8bd3e2061$lut for cells of type $lut. Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775$lut for cells of type $lut. Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b$lut for cells of type $lut. Using template $paramod$a15fd389a2f54cb7b94707b25934d226e68d9e2e$lut for cells of type $lut. Using template $paramod$c5b694ec89d7629b942ccf6a9be1d39e24f8edec$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. Using template $paramod$b3996eaf69323687b39c8eb55a63a3f2e74fa6df$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f$lut for cells of type $lut. Using template $paramod$8aa914641d9da3ceaab54a09681d988e5887c82c$lut for cells of type $lut. Using template $paramod$c24ed72ebb67e9ead6029e42e909ef7fc0abbb11$lut for cells of type $lut. Using template $paramod$1f1c2285d3199e0f5231afa4adf5ed82133f9995$lut for cells of type $lut. Using template $paramod$a2280512f80c783e53ab598de7cc957e97033112$lut for cells of type $lut. Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod$f85118f727cbfc385385a0fcb2d977c74c137bb0$lut for cells of type $lut. Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149$lut for cells of type $lut. Using template $paramod$eac49467755a2a64585b1a602c05d89b5ec6a603$lut for cells of type $lut. Using template $paramod$3f9690f3686c157edaf50719dc5276d55022a111$lut for cells of type $lut. Using template $paramod$77689864380962fabea47328e5773ea09d66b7d5$lut for cells of type $lut. Using template $paramod$283ee0eec66c3dec15fd580adfa20cf64b62c705$lut for cells of type $lut. Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b$lut for cells of type $lut. Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072$lut for cells of type $lut. Using template $paramod$fb5ee0bdef1c4e74aaf1fd8efae98b46a2f5e564$lut for cells of type $lut. Using template $paramod$16773ebb5e5d8dbce266b8a86bb4af4574d61ffd$lut for cells of type $lut. No more expansions possible. 3.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in top_tommath_add_e8_m35_round_even_sticky_p3. Optimizing LUTs in FpxxAdd. Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12712.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12715.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12721.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12724.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12727.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12731.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13319.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13321.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13328.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13251.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13251.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13251.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13229.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13358.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12964.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13253.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13255.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13374.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13375.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12969.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13189.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13191.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13193.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13381.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13248.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13248.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13248.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12754.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12752.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12756.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12757.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12760.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12763.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12765.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12771.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12778.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12783.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12785.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12804.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12797.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12821.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13067.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13091.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13415.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13420.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13125.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13129.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13159.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13161.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13179.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13400.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13185.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13413.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13378.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13248.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13251.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13207.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13321.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12963.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13284.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13351.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13299.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13361.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13364.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13367.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13375.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13376.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$12976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13410.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$12585$auto$blifparse.cc:557:parse_blif$13420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Removed 0 unused cells and 1941 unused wires. 3.50. Executing AUTONAME pass. Renamed 134 objects in module top_tommath_add_e8_m35_round_even_sticky_p3 (4 iterations). Renamed 3399 objects in module FpxxAdd (513 iterations). 3.51. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `top_tommath_add_e8_m35_round_even_sticky_p3'. Setting top module to top_tommath_add_e8_m35_round_even_sticky_p3. 3.51.1. Analyzing design hierarchy.. Top module: \top_tommath_add_e8_m35_round_even_sticky_p3 Used module: \FpxxAdd 3.51.2. Analyzing design hierarchy.. Top module: \top_tommath_add_e8_m35_round_even_sticky_p3 Used module: \FpxxAdd Removed 0 unused modules. 3.52. Printing statistics. === top_tommath_add_e8_m35_round_even_sticky_p3 === +----------Local Count, excluding submodules. | 17 wires 359 wire bits 17 public wires 359 public wire bits 7 ports 136 port bits 135 submodules 1 FpxxAdd 134 TRELLIS_FF === FpxxAdd === +----------Local Count, excluding submodules. | 1473 wires 4680 wire bits 1473 public wires 4680 public wire bits 13 ports 136 port bits 2029 submodules 134 CCU2C 103 L6MUX21 1238 LUT4 295 PFUMX 259 TRELLIS_FF === design hierarchy === +----------Count including submodules. | - top_tommath_add_e8_m35_round_even_sticky_p3 +----------Count including submodules. | 1490 wires 5039 wire bits 1490 public wires 5039 public wire bits 20 ports 272 port bits - memories - memory bits - processes - cells 135 submodules 1 FpxxAdd 134 TRELLIS_FF 3.53. Executing CHECK pass (checking for obvious problems). Checking module top_tommath_add_e8_m35_round_even_sticky_p3... Checking module FpxxAdd... Found and reported 0 problems. 3.54. Executing JSON backend. End of script. Logfile hash: 7201de5cc5, time: 2.84s, user: 1.85s, system: 0.09s, MEM: 89.28 MB peak Yosys 0.64+215 (git sha1 54866d154, clang++ 18.1.8 -fPIC -O3) Time spent: 43% 3x abc (1 sec), 12% 1x autoname (0 sec), ... $ yosys -s /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/ecp5-yosys/rows/tommath_add_e8_m35_round_even_sticky_p3/yosys.ys [exit code 0]