Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2025.2.1 (lin64) Build 6403652 Thu Mar 19 13:47:00 MDT 2026
| Date         : Sun May 24 14:45:19 2026
| Host         : deep-thought running 64-bit Manjaro Linux
| Command      : report_timing_summary -file /mnt/storage/test/zkf-vs-flopoco/artifacts/targets/spartan7-vivado/rows/tommath_div_e8_m17_large_p2/timing_summary.rpt -max_paths 10 -nworst 10
| Design       : top_tommath_div_e8_m17_large_p2
| Device       : 7s50-csga324
| Speed File   : -1  PRODUCTION 1.23 2018-06-13
| Design State : Routed
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (54)
6. checking no_output_delay (27)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (54)
-------------------------------
 There are 54 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (27)
--------------------------------
 There are 27 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.921        0.000                      0                  439        0.107        0.000                      0                  439        2.783        0.000                       0                   197  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock  Waveform(ns)         Period(ns)      Frequency(MHz)
-----  ------------         ----------      --------------
clk    {0.000 3.333}        6.667           149.993         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
clk                 0.921        0.000                      0                  439        0.107        0.000                      0                  439        2.783        0.000                       0                   197  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  clk
  To Clock:  clk

Setup :            0  Failing Endpoints,  Worst Slack        0.921ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.107ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.783ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.921ns  (required time - arrival time)
  Source:                 u_dut/div_full_p4/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/div_p5_reg/PCIN[0]
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        4.262ns  (logic 4.206ns (98.691%)  route 0.056ns (1.309%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.973     0.973    u_dut/clk
    DSP48_X1Y29          DSP48E1                                      r  u_dut/div_full_p4/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X1Y29          DSP48E1 (Prop_dsp48e1_CLK_PCOUT[0])
                                                      4.206     5.179 r  u_dut/div_full_p4/PCOUT[0]
                         net (fo=1, routed)           0.056     5.235    u_dut/div_full_p4_n_153
    DSP48_X1Y30          DSP48E1                                      r  u_dut/div_p5_reg/PCIN[0]
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=196, unset)          0.924     7.591    u_dut/clk
    DSP48_X1Y30          DSP48E1                                      r  u_dut/div_p5_reg/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    DSP48_X1Y30          DSP48E1 (Setup_dsp48e1_CLK_PCIN[0])
                                                     -1.400     6.156    u_dut/div_p5_reg
  -------------------------------------------------------------------
                         required time                          6.156    
                         arrival time                          -5.235    
  -------------------------------------------------------------------
                         slack                                  0.921    

Slack (MET) :             0.921ns  (required time - arrival time)
  Source:                 u_dut/div_full_p4/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/div_p5_reg/PCIN[0]
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        4.262ns  (logic 4.206ns (98.691%)  route 0.056ns (1.309%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.973     0.973    u_dut/clk
    DSP48_X1Y29          DSP48E1                                      r  u_dut/div_full_p4/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X1Y29          DSP48E1 (Prop_dsp48e1_CLK_PCOUT[0])
                                                      4.206     5.179 f  u_dut/div_full_p4/PCOUT[0]
                         net (fo=1, routed)           0.056     5.235    u_dut/div_full_p4_n_153
    DSP48_X1Y30          DSP48E1                                      f  u_dut/div_p5_reg/PCIN[0]
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=196, unset)          0.924     7.591    u_dut/clk
    DSP48_X1Y30          DSP48E1                                      r  u_dut/div_p5_reg/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    DSP48_X1Y30          DSP48E1 (Setup_dsp48e1_CLK_PCIN[0])
                                                     -1.400     6.156    u_dut/div_p5_reg
  -------------------------------------------------------------------
                         required time                          6.156    
                         arrival time                          -5.235    
  -------------------------------------------------------------------
                         slack                                  0.921    

Slack (MET) :             0.921ns  (required time - arrival time)
  Source:                 u_dut/div_full_p4/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/div_p5_reg/PCIN[10]
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        4.262ns  (logic 4.206ns (98.691%)  route 0.056ns (1.309%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.973     0.973    u_dut/clk
    DSP48_X1Y29          DSP48E1                                      r  u_dut/div_full_p4/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X1Y29          DSP48E1 (Prop_dsp48e1_CLK_PCOUT[10])
                                                      4.206     5.179 r  u_dut/div_full_p4/PCOUT[10]
                         net (fo=1, routed)           0.056     5.235    u_dut/div_full_p4_n_143
    DSP48_X1Y30          DSP48E1                                      r  u_dut/div_p5_reg/PCIN[10]
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=196, unset)          0.924     7.591    u_dut/clk
    DSP48_X1Y30          DSP48E1                                      r  u_dut/div_p5_reg/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    DSP48_X1Y30          DSP48E1 (Setup_dsp48e1_CLK_PCIN[10])
                                                     -1.400     6.156    u_dut/div_p5_reg
  -------------------------------------------------------------------
                         required time                          6.156    
                         arrival time                          -5.235    
  -------------------------------------------------------------------
                         slack                                  0.921    

Slack (MET) :             0.921ns  (required time - arrival time)
  Source:                 u_dut/div_full_p4/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/div_p5_reg/PCIN[10]
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        4.262ns  (logic 4.206ns (98.691%)  route 0.056ns (1.309%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.973     0.973    u_dut/clk
    DSP48_X1Y29          DSP48E1                                      r  u_dut/div_full_p4/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X1Y29          DSP48E1 (Prop_dsp48e1_CLK_PCOUT[10])
                                                      4.206     5.179 f  u_dut/div_full_p4/PCOUT[10]
                         net (fo=1, routed)           0.056     5.235    u_dut/div_full_p4_n_143
    DSP48_X1Y30          DSP48E1                                      f  u_dut/div_p5_reg/PCIN[10]
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=196, unset)          0.924     7.591    u_dut/clk
    DSP48_X1Y30          DSP48E1                                      r  u_dut/div_p5_reg/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    DSP48_X1Y30          DSP48E1 (Setup_dsp48e1_CLK_PCIN[10])
                                                     -1.400     6.156    u_dut/div_p5_reg
  -------------------------------------------------------------------
                         required time                          6.156    
                         arrival time                          -5.235    
  -------------------------------------------------------------------
                         slack                                  0.921    

Slack (MET) :             0.921ns  (required time - arrival time)
  Source:                 u_dut/div_full_p4/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/div_p5_reg/PCIN[11]
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        4.262ns  (logic 4.206ns (98.691%)  route 0.056ns (1.309%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.973     0.973    u_dut/clk
    DSP48_X1Y29          DSP48E1                                      r  u_dut/div_full_p4/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X1Y29          DSP48E1 (Prop_dsp48e1_CLK_PCOUT[11])
                                                      4.206     5.179 r  u_dut/div_full_p4/PCOUT[11]
                         net (fo=1, routed)           0.056     5.235    u_dut/div_full_p4_n_142
    DSP48_X1Y30          DSP48E1                                      r  u_dut/div_p5_reg/PCIN[11]
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=196, unset)          0.924     7.591    u_dut/clk
    DSP48_X1Y30          DSP48E1                                      r  u_dut/div_p5_reg/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    DSP48_X1Y30          DSP48E1 (Setup_dsp48e1_CLK_PCIN[11])
                                                     -1.400     6.156    u_dut/div_p5_reg
  -------------------------------------------------------------------
                         required time                          6.156    
                         arrival time                          -5.235    
  -------------------------------------------------------------------
                         slack                                  0.921    

Slack (MET) :             0.921ns  (required time - arrival time)
  Source:                 u_dut/div_full_p4/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/div_p5_reg/PCIN[11]
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        4.262ns  (logic 4.206ns (98.691%)  route 0.056ns (1.309%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.973     0.973    u_dut/clk
    DSP48_X1Y29          DSP48E1                                      r  u_dut/div_full_p4/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X1Y29          DSP48E1 (Prop_dsp48e1_CLK_PCOUT[11])
                                                      4.206     5.179 f  u_dut/div_full_p4/PCOUT[11]
                         net (fo=1, routed)           0.056     5.235    u_dut/div_full_p4_n_142
    DSP48_X1Y30          DSP48E1                                      f  u_dut/div_p5_reg/PCIN[11]
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=196, unset)          0.924     7.591    u_dut/clk
    DSP48_X1Y30          DSP48E1                                      r  u_dut/div_p5_reg/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    DSP48_X1Y30          DSP48E1 (Setup_dsp48e1_CLK_PCIN[11])
                                                     -1.400     6.156    u_dut/div_p5_reg
  -------------------------------------------------------------------
                         required time                          6.156    
                         arrival time                          -5.235    
  -------------------------------------------------------------------
                         slack                                  0.921    

Slack (MET) :             0.921ns  (required time - arrival time)
  Source:                 u_dut/div_full_p4/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/div_p5_reg/PCIN[12]
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        4.262ns  (logic 4.206ns (98.691%)  route 0.056ns (1.309%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.973     0.973    u_dut/clk
    DSP48_X1Y29          DSP48E1                                      r  u_dut/div_full_p4/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X1Y29          DSP48E1 (Prop_dsp48e1_CLK_PCOUT[12])
                                                      4.206     5.179 r  u_dut/div_full_p4/PCOUT[12]
                         net (fo=1, routed)           0.056     5.235    u_dut/div_full_p4_n_141
    DSP48_X1Y30          DSP48E1                                      r  u_dut/div_p5_reg/PCIN[12]
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=196, unset)          0.924     7.591    u_dut/clk
    DSP48_X1Y30          DSP48E1                                      r  u_dut/div_p5_reg/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    DSP48_X1Y30          DSP48E1 (Setup_dsp48e1_CLK_PCIN[12])
                                                     -1.400     6.156    u_dut/div_p5_reg
  -------------------------------------------------------------------
                         required time                          6.156    
                         arrival time                          -5.235    
  -------------------------------------------------------------------
                         slack                                  0.921    

Slack (MET) :             0.921ns  (required time - arrival time)
  Source:                 u_dut/div_full_p4/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/div_p5_reg/PCIN[12]
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        4.262ns  (logic 4.206ns (98.691%)  route 0.056ns (1.309%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.973     0.973    u_dut/clk
    DSP48_X1Y29          DSP48E1                                      r  u_dut/div_full_p4/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X1Y29          DSP48E1 (Prop_dsp48e1_CLK_PCOUT[12])
                                                      4.206     5.179 f  u_dut/div_full_p4/PCOUT[12]
                         net (fo=1, routed)           0.056     5.235    u_dut/div_full_p4_n_141
    DSP48_X1Y30          DSP48E1                                      f  u_dut/div_p5_reg/PCIN[12]
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=196, unset)          0.924     7.591    u_dut/clk
    DSP48_X1Y30          DSP48E1                                      r  u_dut/div_p5_reg/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    DSP48_X1Y30          DSP48E1 (Setup_dsp48e1_CLK_PCIN[12])
                                                     -1.400     6.156    u_dut/div_p5_reg
  -------------------------------------------------------------------
                         required time                          6.156    
                         arrival time                          -5.235    
  -------------------------------------------------------------------
                         slack                                  0.921    

Slack (MET) :             0.921ns  (required time - arrival time)
  Source:                 u_dut/div_full_p4/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/div_p5_reg/PCIN[13]
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        4.262ns  (logic 4.206ns (98.691%)  route 0.056ns (1.309%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.973     0.973    u_dut/clk
    DSP48_X1Y29          DSP48E1                                      r  u_dut/div_full_p4/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X1Y29          DSP48E1 (Prop_dsp48e1_CLK_PCOUT[13])
                                                      4.206     5.179 r  u_dut/div_full_p4/PCOUT[13]
                         net (fo=1, routed)           0.056     5.235    u_dut/div_full_p4_n_140
    DSP48_X1Y30          DSP48E1                                      r  u_dut/div_p5_reg/PCIN[13]
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=196, unset)          0.924     7.591    u_dut/clk
    DSP48_X1Y30          DSP48E1                                      r  u_dut/div_p5_reg/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    DSP48_X1Y30          DSP48E1 (Setup_dsp48e1_CLK_PCIN[13])
                                                     -1.400     6.156    u_dut/div_p5_reg
  -------------------------------------------------------------------
                         required time                          6.156    
                         arrival time                          -5.235    
  -------------------------------------------------------------------
                         slack                                  0.921    

Slack (MET) :             0.921ns  (required time - arrival time)
  Source:                 u_dut/div_full_p4/CLK
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/div_p5_reg/PCIN[13]
                            (rising edge-triggered cell DSP48E1 clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.667ns  (clk rise@6.667ns - clk rise@0.000ns)
  Data Path Delay:        4.262ns  (logic 4.206ns (98.691%)  route 0.056ns (1.309%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.924ns = ( 7.591 - 6.667 ) 
    Source Clock Delay      (SCD):    0.973ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.973     0.973    u_dut/clk
    DSP48_X1Y29          DSP48E1                                      r  u_dut/div_full_p4/CLK
  -------------------------------------------------------------------    -------------------
    DSP48_X1Y29          DSP48E1 (Prop_dsp48e1_CLK_PCOUT[13])
                                                      4.206     5.179 f  u_dut/div_full_p4/PCOUT[13]
                         net (fo=1, routed)           0.056     5.235    u_dut/div_full_p4_n_140
    DSP48_X1Y30          DSP48E1                                      f  u_dut/div_p5_reg/PCIN[13]
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        6.667     6.667 r  
                                                      0.000     6.667 r  clk (IN)
                         net (fo=196, unset)          0.924     7.591    u_dut/clk
    DSP48_X1Y30          DSP48E1                                      r  u_dut/div_p5_reg/CLK
                         clock pessimism              0.000     7.591    
                         clock uncertainty           -0.035     7.556    
    DSP48_X1Y30          DSP48E1 (Setup_dsp48e1_CLK_PCIN[13])
                                                     -1.400     6.156    u_dut/div_p5_reg
  -------------------------------------------------------------------
                         required time                          6.156    
                         arrival time                          -5.235    
  -------------------------------------------------------------------
                         slack                                  0.921    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.107ns  (arrival time - required time)
  Source:                 a_r_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/mant_a_p1_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.204ns  (logic 0.141ns (69.047%)  route 0.063ns (30.953%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.410     0.410    clk
    SLICE_X57Y73         FDRE                                         r  a_r_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y73         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  a_r_reg[15]/Q
                         net (fo=2, routed)           0.063     0.614    u_dut/io_op_a_mant[15]
    SLICE_X56Y73         FDRE                                         r  u_dut/mant_a_p1_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.432     0.432    u_dut/clk
    SLICE_X56Y73         FDRE                                         r  u_dut/mant_a_p1_reg[15]/C
                         clock pessimism              0.000     0.432    
    SLICE_X56Y73         FDRE (Hold_fdre_C_D)         0.076     0.508    u_dut/mant_a_p1_reg[15]
  -------------------------------------------------------------------
                         required time                         -0.508    
                         arrival time                           0.614    
  -------------------------------------------------------------------
                         slack                                  0.107    

Slack (MET) :             0.107ns  (arrival time - required time)
  Source:                 a_r_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/mant_a_p1_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.204ns  (logic 0.141ns (69.047%)  route 0.063ns (30.953%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.410     0.410    clk
    SLICE_X57Y73         FDRE                                         r  a_r_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y73         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  a_r_reg[15]/Q
                         net (fo=2, routed)           0.063     0.614    u_dut/io_op_a_mant[15]
    SLICE_X56Y73         FDRE                                         f  u_dut/mant_a_p1_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.432     0.432    u_dut/clk
    SLICE_X56Y73         FDRE                                         r  u_dut/mant_a_p1_reg[15]/C
                         clock pessimism              0.000     0.432    
    SLICE_X56Y73         FDRE (Hold_fdre_C_D)         0.076     0.508    u_dut/mant_a_p1_reg[15]
  -------------------------------------------------------------------
                         required time                         -0.508    
                         arrival time                           0.614    
  -------------------------------------------------------------------
                         slack                                  0.107    

Slack (MET) :             0.158ns  (arrival time - required time)
  Source:                 u_dut/sign_p2_reg/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/sign_p3_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.257ns  (logic 0.141ns (54.795%)  route 0.116ns (45.205%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.410     0.410    u_dut/clk
    SLICE_X49Y76         FDRE                                         r  u_dut/sign_p2_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y76         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/sign_p2_reg/Q
                         net (fo=1, routed)           0.116     0.667    u_dut/sign_p2
    SLICE_X51Y76         FDRE                                         r  u_dut/sign_p3_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.432     0.432    u_dut/clk
    SLICE_X51Y76         FDRE                                         r  u_dut/sign_p3_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X51Y76         FDRE (Hold_fdre_C_D)         0.078     0.510    u_dut/sign_p3_reg
  -------------------------------------------------------------------
                         required time                         -0.510    
                         arrival time                           0.667    
  -------------------------------------------------------------------
                         slack                                  0.158    

Slack (MET) :             0.158ns  (arrival time - required time)
  Source:                 u_dut/sign_p2_reg/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/sign_p3_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.257ns  (logic 0.141ns (54.795%)  route 0.116ns (45.205%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.410     0.410    u_dut/clk
    SLICE_X49Y76         FDRE                                         r  u_dut/sign_p2_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y76         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/sign_p2_reg/Q
                         net (fo=1, routed)           0.116     0.667    u_dut/sign_p2
    SLICE_X51Y76         FDRE                                         f  u_dut/sign_p3_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.432     0.432    u_dut/clk
    SLICE_X51Y76         FDRE                                         r  u_dut/sign_p3_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X51Y76         FDRE (Hold_fdre_C_D)         0.078     0.510    u_dut/sign_p3_reg
  -------------------------------------------------------------------
                         required time                         -0.510    
                         arrival time                           0.667    
  -------------------------------------------------------------------
                         slack                                  0.158    

Slack (MET) :             0.159ns  (arrival time - required time)
  Source:                 u_dut/exp_full_p4_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/exp_full_p5_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.251ns  (logic 0.141ns (56.174%)  route 0.110ns (43.826%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.410     0.410    u_dut/clk
    SLICE_X53Y77         FDRE                                         r  u_dut/exp_full_p4_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y77         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/exp_full_p4_reg[0]/Q
                         net (fo=1, routed)           0.110     0.661    u_dut/exp_full_p4[0]
    SLICE_X53Y76         FDRE                                         r  u_dut/exp_full_p5_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.432     0.432    u_dut/clk
    SLICE_X53Y76         FDRE                                         r  u_dut/exp_full_p5_reg[0]/C
                         clock pessimism              0.000     0.432    
    SLICE_X53Y76         FDRE (Hold_fdre_C_D)         0.070     0.502    u_dut/exp_full_p5_reg[0]
  -------------------------------------------------------------------
                         required time                         -0.502    
                         arrival time                           0.661    
  -------------------------------------------------------------------
                         slack                                  0.159    

Slack (MET) :             0.159ns  (arrival time - required time)
  Source:                 u_dut/exp_full_p4_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/exp_full_p5_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.251ns  (logic 0.141ns (56.174%)  route 0.110ns (43.826%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.410     0.410    u_dut/clk
    SLICE_X53Y77         FDRE                                         r  u_dut/exp_full_p4_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y77         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/exp_full_p4_reg[0]/Q
                         net (fo=1, routed)           0.110     0.661    u_dut/exp_full_p4[0]
    SLICE_X53Y76         FDRE                                         f  u_dut/exp_full_p5_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.432     0.432    u_dut/clk
    SLICE_X53Y76         FDRE                                         r  u_dut/exp_full_p5_reg[0]/C
                         clock pessimism              0.000     0.432    
    SLICE_X53Y76         FDRE (Hold_fdre_C_D)         0.070     0.502    u_dut/exp_full_p5_reg[0]
  -------------------------------------------------------------------
                         required time                         -0.502    
                         arrival time                           0.661    
  -------------------------------------------------------------------
                         slack                                  0.159    

Slack (MET) :             0.159ns  (arrival time - required time)
  Source:                 u_dut/exp_full_p4_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/exp_full_p5_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.251ns  (logic 0.141ns (56.174%)  route 0.110ns (43.826%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.410     0.410    u_dut/clk
    SLICE_X53Y77         FDRE                                         r  u_dut/exp_full_p4_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y77         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/exp_full_p4_reg[8]/Q
                         net (fo=1, routed)           0.110     0.661    u_dut/exp_full_p4[8]
    SLICE_X53Y78         FDRE                                         r  u_dut/exp_full_p5_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.432     0.432    u_dut/clk
    SLICE_X53Y78         FDRE                                         r  u_dut/exp_full_p5_reg[8]/C
                         clock pessimism              0.000     0.432    
    SLICE_X53Y78         FDRE (Hold_fdre_C_D)         0.070     0.502    u_dut/exp_full_p5_reg[8]
  -------------------------------------------------------------------
                         required time                         -0.502    
                         arrival time                           0.661    
  -------------------------------------------------------------------
                         slack                                  0.159    

Slack (MET) :             0.159ns  (arrival time - required time)
  Source:                 u_dut/exp_full_p4_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/exp_full_p5_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.251ns  (logic 0.141ns (56.174%)  route 0.110ns (43.826%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.410     0.410    u_dut/clk
    SLICE_X53Y77         FDRE                                         r  u_dut/exp_full_p4_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y77         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/exp_full_p4_reg[8]/Q
                         net (fo=1, routed)           0.110     0.661    u_dut/exp_full_p4[8]
    SLICE_X53Y78         FDRE                                         f  u_dut/exp_full_p5_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.432     0.432    u_dut/clk
    SLICE_X53Y78         FDRE                                         r  u_dut/exp_full_p5_reg[8]/C
                         clock pessimism              0.000     0.432    
    SLICE_X53Y78         FDRE (Hold_fdre_C_D)         0.070     0.502    u_dut/exp_full_p5_reg[8]
  -------------------------------------------------------------------
                         required time                         -0.502    
                         arrival time                           0.661    
  -------------------------------------------------------------------
                         slack                                  0.159    

Slack (MET) :             0.163ns  (arrival time - required time)
  Source:                 u_dut/sign_p1_reg/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/sign_p2_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.255ns  (logic 0.141ns (55.385%)  route 0.114ns (44.615%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.410     0.410    u_dut/clk
    SLICE_X48Y77         FDRE                                         r  u_dut/sign_p1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y77         FDRE (Prop_fdre_C_Q)         0.141     0.551 r  u_dut/sign_p1_reg/Q
                         net (fo=1, routed)           0.114     0.665    u_dut/sign_p1
    SLICE_X49Y76         FDRE                                         r  u_dut/sign_p2_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.432     0.432    u_dut/clk
    SLICE_X49Y76         FDRE                                         r  u_dut/sign_p2_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X49Y76         FDRE (Hold_fdre_C_D)         0.070     0.502    u_dut/sign_p2_reg
  -------------------------------------------------------------------
                         required time                         -0.502    
                         arrival time                           0.665    
  -------------------------------------------------------------------
                         slack                                  0.163    

Slack (MET) :             0.163ns  (arrival time - required time)
  Source:                 u_dut/sign_p1_reg/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Destination:            u_dut/sign_p2_reg/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@3.333ns period=6.667ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.255ns  (logic 0.141ns (55.385%)  route 0.114ns (44.615%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.432ns
    Source Clock Delay      (SCD):    0.410ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.410     0.410    u_dut/clk
    SLICE_X48Y77         FDRE                                         r  u_dut/sign_p1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y77         FDRE (Prop_fdre_C_Q)         0.141     0.551 f  u_dut/sign_p1_reg/Q
                         net (fo=1, routed)           0.114     0.665    u_dut/sign_p1
    SLICE_X49Y76         FDRE                                         f  u_dut/sign_p2_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
                                                      0.000     0.000 r  clk (IN)
                         net (fo=196, unset)          0.432     0.432    u_dut/clk
    SLICE_X49Y76         FDRE                                         r  u_dut/sign_p2_reg/C
                         clock pessimism              0.000     0.432    
    SLICE_X49Y76         FDRE (Hold_fdre_C_D)         0.070     0.502    u_dut/sign_p2_reg
  -------------------------------------------------------------------
                         required time                         -0.502    
                         arrival time                           0.665    
  -------------------------------------------------------------------
                         slack                                  0.163    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk
Waveform(ns):       { 0.000 3.333 }
Period(ns):         6.667
Sources:            { clk }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     DSP48E1/CLK         n/a            3.884         6.667       2.783      DSP48_X1Y30   u_dut/div_p5_reg/CLK
Min Period        n/a     DSP48E1/CLK         n/a            3.687         6.667       2.980      DSP48_X1Y28   u_dut/x_mul_yhyl_p3_reg/CLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576         6.667       4.091      RAMB18_X1Y30  u_dut/_zz_div_table_port0_reg/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.576         6.667       4.091      RAMB18_X1Y30  u_dut/_zz_div_table_port0_reg/CLKBWRCLK
Min Period        n/a     DSP48E1/CLK         n/a            2.154         6.667       4.513      DSP48_X1Y29   u_dut/div_full_p4/CLK
Min Period        n/a     FDRE/C              n/a            1.000         6.667       5.667      SLICE_X57Y73  a_r_reg[0]/C
Min Period        n/a     FDRE/C              n/a            1.000         6.667       5.667      SLICE_X51Y72  a_r_reg[10]/C
Min Period        n/a     FDRE/C              n/a            1.000         6.667       5.667      SLICE_X55Y73  a_r_reg[11]/C
Min Period        n/a     FDRE/C              n/a            1.000         6.667       5.667      SLICE_X55Y73  a_r_reg[12]/C
Min Period        n/a     FDRE/C              n/a            1.000         6.667       5.667      SLICE_X57Y71  a_r_reg[13]/C
Low Pulse Width   Slow    FDRE/C              n/a            0.500         3.333       2.833      SLICE_X57Y73  a_r_reg[0]/C
Low Pulse Width   Fast    FDRE/C              n/a            0.500         3.334       2.834      SLICE_X57Y73  a_r_reg[0]/C
Low Pulse Width   Slow    FDRE/C              n/a            0.500         3.333       2.833      SLICE_X51Y72  a_r_reg[10]/C
Low Pulse Width   Fast    FDRE/C              n/a            0.500         3.334       2.834      SLICE_X51Y72  a_r_reg[10]/C
Low Pulse Width   Slow    FDRE/C              n/a            0.500         3.333       2.833      SLICE_X55Y73  a_r_reg[11]/C
Low Pulse Width   Fast    FDRE/C              n/a            0.500         3.334       2.834      SLICE_X55Y73  a_r_reg[11]/C
Low Pulse Width   Slow    FDRE/C              n/a            0.500         3.333       2.833      SLICE_X55Y73  a_r_reg[12]/C
Low Pulse Width   Fast    FDRE/C              n/a            0.500         3.334       2.834      SLICE_X55Y73  a_r_reg[12]/C
Low Pulse Width   Slow    FDRE/C              n/a            0.500         3.333       2.833      SLICE_X57Y71  a_r_reg[13]/C
Low Pulse Width   Fast    FDRE/C              n/a            0.500         3.334       2.834      SLICE_X57Y71  a_r_reg[13]/C
High Pulse Width  Slow    FDRE/C              n/a            0.500         3.334       2.834      SLICE_X57Y73  a_r_reg[0]/C
High Pulse Width  Fast    FDRE/C              n/a            0.500         3.333       2.833      SLICE_X57Y73  a_r_reg[0]/C
High Pulse Width  Slow    FDRE/C              n/a            0.500         3.334       2.834      SLICE_X51Y72  a_r_reg[10]/C
High Pulse Width  Fast    FDRE/C              n/a            0.500         3.333       2.833      SLICE_X51Y72  a_r_reg[10]/C
High Pulse Width  Slow    FDRE/C              n/a            0.500         3.334       2.834      SLICE_X55Y73  a_r_reg[11]/C
High Pulse Width  Fast    FDRE/C              n/a            0.500         3.333       2.833      SLICE_X55Y73  a_r_reg[11]/C
High Pulse Width  Slow    FDRE/C              n/a            0.500         3.334       2.834      SLICE_X55Y73  a_r_reg[12]/C
High Pulse Width  Fast    FDRE/C              n/a            0.500         3.333       2.833      SLICE_X55Y73  a_r_reg[12]/C
High Pulse Width  Slow    FDRE/C              n/a            0.500         3.334       2.834      SLICE_X57Y71  a_r_reg[13]/C
High Pulse Width  Fast    FDRE/C              n/a            0.500         3.333       2.833      SLICE_X57Y71  a_r_reg[13]/C



